Hello, I am trying use the MAC/PHY 82559 (rev C I think) on an interrupt base manner. The interrupt line of the chip is connected directly to the PPC (INT0), so I use the EPIC in direct mode. When the IVPR0[P] is active low configured and IVPR[S] is level sensitive configured I receive continuously an interrupt which is normal (I think the IRQ line of the chip is configured active high) When it is another configuration I receive nothing.

I think, it is a problem with the configuration of the chip since with Linux the chip send well interrupts (every ms) but with Linux, the problem is the EPIC config. Does someone have an idea to solve this or better documentation than the one of Intel ? ---------------------------------------------------------------------------- ------ Benoit Callebaut Software Development Engineer Barco | Control Rooms Noordlaan 5, 8520 Kuurne, Belgium

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