[U-Boot] [PATCH V6 00/11] ARM: OMAP3-DRA7: CP15 erratum workarounds and improvements
The sixth revision should be proper, I hope. (skipping all the blurb and pointing to v1 for the blurb).
Changes since v5: - omap_smc1 is now in omap_common.h - I hope we can pick up Matt's Tested-by tag from previous rev.. http://article.gmane.org/gmane.comp.boot-loaders.u-boot/214277
v5: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/214219 v4: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213863 V3: http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/213207/focus=213307 V2: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/213060 V1: http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/212174
This time, the series is based on u-boot master git://git.denx.de/u-boot.git master 62f3aaf89d01 Merge branch 'buildman' of git://git.denx.de/u-boot-x86
Git tree: https://gitorious.org/nm-kernel/u-boot-nm (at least till gitorious is around..) branch errata-v6-master-62f3aaf89d01
Git link: https://gitorious.org/nm-kernel/u-boot-nm.git errata-v6-master-62f3aaf89d01
Nishanth Menon (10): ARM: Introduce erratum workaround for 798870 ARM: Introduce erratum workaround for 454179 ARM: Introduce erratum workaround for 430973 ARM: Introduce erratum workaround for 621766 ARM: OMAP: Change set_pl310_ctrl_reg to be generic ARM: OMAP3: Rename omap3.h to omap.h to be generic as all SoCs ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1 ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configuration ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766 ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
Praveen Rao (1): ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870
README | 8 +++ arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/cp15.c | 29 +++++++++ arch/arm/cpu/armv7/omap-common/Makefile | 2 +- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 20 +++--- arch/arm/cpu/armv7/omap3/board.c | 60 +++++++----------- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 11 ---- arch/arm/cpu/armv7/omap4/hwinit.c | 4 +- arch/arm/cpu/armv7/omap5/hwinit.c | 23 +++++++ arch/arm/cpu/armv7/start.S | 64 +++++++++++++++++++- .../arm/include/asm/arch-omap3/{omap3.h => omap.h} | 0 arch/arm/include/asm/arch-omap3/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 4 +- arch/arm/include/asm/arch-omap5/sys_proto.h | 3 + arch/arm/include/asm/armv7.h | 5 ++ arch/arm/include/asm/omap_common.h | 2 + board/nokia/rx51/rx51.c | 19 +++--- include/configs/am3517_crane.h | 6 +- include/configs/am3517_evm.h | 6 +- include/configs/cm_t35.h | 6 +- include/configs/cm_t3517.h | 6 +- include/configs/dig297.h | 6 +- include/configs/mcx.h | 6 +- include/configs/nokia_rx51.h | 6 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_evm_common.h | 4 ++ include/configs/omap3_evm_quick_mmc.h | 2 +- include/configs/omap3_evm_quick_nand.h | 2 +- include/configs/omap3_logic.h | 6 +- include/configs/omap3_mvblx.h | 6 +- include/configs/omap3_pandora.h | 6 +- include/configs/omap3_sdp3430.h | 6 +- include/configs/omap3_zoom1.h | 2 +- include/configs/tam3517-common.h | 6 +- include/configs/tao3530.h | 6 +- include/configs/ti_omap3_common.h | 7 ++- include/configs/ti_omap5_common.h | 3 + include/configs/tricorder.h | 6 +- 38 files changed, 274 insertions(+), 90 deletions(-) create mode 100644 arch/arm/cpu/armv7/cp15.c rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)
Regards, Nishanth Menon
Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon nm@ti.com --- README | 5 +++++ arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/cp15.c | 23 +++++++++++++++++++++++ arch/arm/cpu/armv7/start.S | 25 ++++++++++++++++++++++++- arch/arm/include/asm/armv7.h | 3 +++ 5 files changed, 56 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/cp15.c
diff --git a/README b/README index 676f41e7f09f..9a0106066b1c 100644 --- a/README +++ b/README @@ -690,6 +690,11 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply!
+ NOTE: The following can be machine specific errata. These + do have ability to provide rudimentary version and machine + specific checks, but expect no product checks. + CONFIG_ARM_ERRATA_798870 + - Driver Model Driver model is a new framework for devices in U-Boot introduced in early 2014. U-Boot is being progressively diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index ad22489e1a1f..1312a9db9e84 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -9,7 +9,7 @@ extra-y := start.o
obj-y += cache_v7.o
-obj-y += cpu.o +obj-y += cpu.o cp15.o obj-y += syslib.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),) diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c new file mode 100644 index 000000000000..8ac81c9ba147 --- /dev/null +++ b/arch/arm/cpu/armv7/cp15.c @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2015 Texas Insturments + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * CP15 specific code + */ + +#include <common.h> +#include <command.h> +#include <asm/system.h> +#include <asm/cache.h> +#include <asm/armv7.h> +#include <linux/compiler.h> + +void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr, + u32 cpu_rev_comb, u32 cpu_variant, + u32 cpu_rev) +{ + asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr)); +} diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 9b49ece2d650..89637e26395d 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -166,7 +166,30 @@ ENTRY(cpu_init_cp15) mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif
- mov pc, lr @ back to my caller + mov r5, lr @ Store my Caller + mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR) + mov r3, r1, lsr #20 @ get variant field + and r3, r3, #0xf @ r3 has CPU variant + and r4, r1, #0xf @ r4 has CPU revision + mov r2, r3, lsl #4 @ shift variant field for combined value + orr r2, r4, r2 @ r2 has combined CPU variant + revision + +#ifdef CONFIG_ARM_ERRATA_798870 + cmp r2, #0x30 @ Applies to lower than R3p0 + bge skip_errata_798870 @ skip if not affected rev + cmp r2, #0x20 @ Applies to including and above R2p0 + blt skip_errata_798870 @ skip if not affected rev + + mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg + orr r0, r0, #1 << 7 @ Enable hazard-detect timeout + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_l2aux_ctrl + isb @ Recommended ISB after l2actlr update + pop {r1-r5} @ Restore the cpu info - fall through +skip_errata_798870: +#endif + + mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index edb3b80015ba..69abc4791ae5 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -138,6 +138,9 @@ extern char __secure_end[];
#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, + u32 cpu_rev_comb, u32 cpu_variant, + u32 cpu_rev); #endif /* ! __ASSEMBLY__ */
#endif
On Mon, Mar 09, 2015 at 05:11:59PM -0500, Nishanth Menon wrote:
Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Mon, Mar 09, 2015 at 05:11:59PM -0500, Nishanth Menon wrote:
Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different.
Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com --- README | 1 + arch/arm/cpu/armv7/cp15.c | 6 ++++++ arch/arm/cpu/armv7/start.S | 13 +++++++++++++ arch/arm/include/asm/armv7.h | 2 ++ 4 files changed, 22 insertions(+)
diff --git a/README b/README index 9a0106066b1c..259dbdbd2075 100644 --- a/README +++ b/README @@ -693,6 +693,7 @@ The following options need to be configured: NOTE: The following can be machine specific errata. These do have ability to provide rudimentary version and machine specific checks, but expect no product checks. + CONFIG_ARM_ERRATA_454179 CONFIG_ARM_ERRATA_798870
- Driver Model diff --git a/arch/arm/cpu/armv7/cp15.c b/arch/arm/cpu/armv7/cp15.c index 8ac81c9ba147..b44c9f94a822 100644 --- a/arch/arm/cpu/armv7/cp15.c +++ b/arch/arm/cpu/armv7/cp15.c @@ -21,3 +21,9 @@ void __weak v7_arch_cp15_set_l2aux_ctrl(u32 l2actlr, u32 cpu_midr, { asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(l2actlr)); } + +void __weak v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) +{ + asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(acr)); +} diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 89637e26395d..8483687879ed 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -189,6 +189,19 @@ ENTRY(cpu_init_cp15) skip_errata_798870: #endif
+#ifdef CONFIG_ARM_ERRATA_454179 + cmp r2, #0x21 @ Only on < r2p1 + bge skip_errata_454179 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through + +skip_errata_454179: +#endif + mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15)
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 69abc4791ae5..e9a00e20002c 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -141,6 +141,8 @@ extern char __secure_end[]; void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, u32 cpu_rev_comb, u32 cpu_variant, u32 cpu_rev); +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev); #endif /* ! __ASSEMBLY__ */
#endif
On Mon, Mar 09, 2015 at 05:12:00PM -0500, Nishanth Menon wrote:
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Mon, Mar 09, 2015 at 05:12:00PM -0500, Nishanth Menon wrote:
454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1
Also provide a hook for SoC specific handling to take place if needed.
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com --- README | 1 + arch/arm/cpu/armv7/start.S | 13 +++++++++++++ 2 files changed, 14 insertions(+)
diff --git a/README b/README index 259dbdbd2075..82f7e10c71d6 100644 --- a/README +++ b/README @@ -693,6 +693,7 @@ The following options need to be configured: NOTE: The following can be machine specific errata. These do have ability to provide rudimentary version and machine specific checks, but expect no product checks. + CONFIG_ARM_ERRATA_430973 CONFIG_ARM_ERRATA_454179 CONFIG_ARM_ERRATA_798870
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 8483687879ed..41fb24cf321b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -202,6 +202,19 @@ skip_errata_798870: skip_errata_454179: #endif
+#ifdef CONFIG_ARM_ERRATA_430973 + cmp r2, #0x21 @ Only on < r2p1 + bge skip_errata_430973 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x1 << 6) @ Set IBE bit + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through + +skip_errata_430973: +#endif + mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15)
On Mon, Mar 09, 2015 at 05:12:01PM -0500, Nishanth Menon wrote:
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Mon, Mar 09, 2015 at 05:12:01PM -0500, Nishanth Menon wrote:
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com --- README | 1 + arch/arm/cpu/armv7/start.S | 13 +++++++++++++ 2 files changed, 14 insertions(+)
diff --git a/README b/README index 82f7e10c71d6..e7e90a08145e 100644 --- a/README +++ b/README @@ -695,6 +695,7 @@ The following options need to be configured: specific checks, but expect no product checks. CONFIG_ARM_ERRATA_430973 CONFIG_ARM_ERRATA_454179 + CONFIG_ARM_ERRATA_621766 CONFIG_ARM_ERRATA_798870
- Driver Model diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 41fb24cf321b..5050021e0210 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -215,6 +215,19 @@ skip_errata_454179: skip_errata_430973: #endif
+#ifdef CONFIG_ARM_ERRATA_621766 + cmp r2, #0x21 @ Only on < r2p1 + bge skip_errata_621766 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x1 << 5) @ Set L1NEON bit + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through + +skip_errata_621766: +#endif + mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15)
On Mon, Mar 09, 2015 at 05:12:02PM -0500, Nishanth Menon wrote:
621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Mon, Mar 09, 2015 at 05:12:02PM -0500, Nishanth Menon wrote:
621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1
Based on ARM errata Document revision 20.0 (13 Nov 2010)
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.
While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread: http://marc.info/?t=142542166800001&r=1&w=2
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 18 +++++++++++------- arch/arm/cpu/armv7/omap4/hwinit.c | 4 ++-- arch/arm/include/asm/arch-omap4/sys_proto.h | 4 +++- arch/arm/include/asm/omap_common.h | 2 ++ 4 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index e19c7aececdd..80619b04df5d 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -22,11 +22,15 @@ ENTRY(save_boot_params) b save_boot_params_ret ENDPROC(save_boot_params)
-ENTRY(set_pl310_ctrl_reg) - PUSH {r4-r11, lr} @ save registers - ROM code may pollute +ENTRY(omap_smc1) + PUSH {r4-r12, lr} @ save registers - ROM code may pollute @ our registers - LDR r12, =0x102 @ Set PL310 control register - value in R0 - .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 - @ call ROM Code API to set control register - POP {r4-r11, pc} -ENDPROC(set_pl310_ctrl_reg) + MOV r12, r0 @ Service + MOV r0, r1 @ Argument + DSB + DMB + .word 0xe1600070 @ SMC #0 - hand assembled for GCC versions + @ call ROM Code API for the service requested + + POP {r4-r12, pc} +ENDPROC(omap_smc1) diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index db16548fac49..9792761d40a0 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -159,11 +159,11 @@ void init_omap_revision(void) #ifndef CONFIG_SYS_L2CACHE_OFF void v7_outer_cache_enable(void) { - set_pl310_ctrl_reg(1); + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); }
void v7_outer_cache_disable(void) { - set_pl310_ctrl_reg(0); + omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); } #endif /* !CONFIG_SYS_L2CACHE_OFF */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index e19975efaf50..f30f86539130 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -37,7 +37,6 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, int size); void set_muxconf_regs_essential(void); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); -void set_pl310_ctrl_reg(u32 val); void setup_clocks_for_console(void); void prcm_init(void); void bypass_dpll(u32 const base); @@ -57,4 +56,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void setup_warmreset_time(void); + +#define OMAP4_SERVICE_PL310_CONTROL_REG_SET 0x102 + #endif diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 323952f5f1b4..123c84ff9593 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -579,6 +579,8 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
void usb_fake_mac_from_die_id(u32 *id);
+void omap_smc1(u32 service, u32 val); + /* ABB */ #define OMAP_ABB_NOMINAL_OPP 0 #define OMAP_ABB_FAST_OPP 1
On Mon, Mar 09, 2015 at 05:12:03PM -0500, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.
While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread: http://marc.info/?t=142542166800001&r=1&w=2
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Mon, Mar 09, 2015 at 05:12:03PM -0500, Nishanth Menon wrote:
set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function.
So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation.
While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread: http://marc.info/?t=142542166800001&r=1&w=2
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon nm@ti.com --- .../arm/include/asm/arch-omap3/{omap3.h => omap.h} | 0 include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/cm_t35.h | 2 +- include/configs/cm_t3517.h | 2 +- include/configs/dig297.h | 2 +- include/configs/mcx.h | 2 +- include/configs/nokia_rx51.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_evm_quick_mmc.h | 2 +- include/configs/omap3_evm_quick_nand.h | 2 +- include/configs/omap3_logic.h | 2 +- include/configs/omap3_mvblx.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_sdp3430.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/tam3517-common.h | 2 +- include/configs/tao3530.h | 2 +- include/configs/ti_omap3_common.h | 2 +- include/configs/tricorder.h | 2 +- 20 files changed, 19 insertions(+), 19 deletions(-) rename arch/arm/include/asm/arch-omap3/{omap3.h => omap.h} (100%)
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap.h similarity index 100% rename from arch/arm/include/asm/arch-omap3/omap3.h rename to arch/arm/include/asm/arch-omap3/omap.h diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 290a6a3e0640..87c850e05df1 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -23,7 +23,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 3de50799621e..c4e19e79b95a 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -23,7 +23,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 9feca1b47b38..e2d5bbb0955d 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -30,7 +30,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index 918032bd753a..ee1b7a0cb5a7 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -30,7 +30,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/dig297.h b/include/configs/dig297.h index c8739ed29490..8791199fc61d 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -36,7 +36,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 26eb2203540f..2cf66c40d6fe 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -26,7 +26,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#define CONFIG_OF_LIBFDT #define CONFIG_FIT diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 46fc91e5e197..442e16ae686b 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -42,7 +42,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #include <asm/arch/mem.h> #include <linux/stringify.h>
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 8bdc08f5864c..4e587e10ffd3 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -18,7 +18,7 @@ #define __OMAP3EVM_CONFIG_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_evm_quick_mmc.h b/include/configs/omap3_evm_quick_mmc.h index 1185f425501f..a7acc1becbeb 100644 --- a/include/configs/omap3_evm_quick_mmc.h +++ b/include/configs/omap3_evm_quick_mmc.h @@ -13,7 +13,7 @@ #define __OMAP3_EVM_QUICK_MMC_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_evm_quick_nand.h b/include/configs/omap3_evm_quick_nand.h index 4427e88b7e4b..c6cad9388961 100644 --- a/include/configs/omap3_evm_quick_nand.h +++ b/include/configs/omap3_evm_quick_nand.h @@ -13,7 +13,7 @@ #define __OMAP3_EVM_QUICK_NAND_H
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* ---------------------------------------------------------------------------- * Supported U-boot commands diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index aeb385f5ff6b..fcef46735835 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -24,7 +24,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index bf1d34dedb4d..20ec3ad15439 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 45feeb577320..b92d67abccf9 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -21,7 +21,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index ac307eb45629..bf5c7a8faf77 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * NOTE: these #defines presume standard SDP jumper settings. diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index c5d742c2bd80..611cd5e1a350 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -22,7 +22,7 @@ #define CONFIG_NAND #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h> #include <configs/ti_omap3_common.h>
/* Remove SPL boot option - we do not support that on LDP yet */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 38288f69aaa5..dea4044d9fbb 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -25,7 +25,7 @@ #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index dd69d4ebabfe..f3e0088d5a00 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -27,7 +27,7 @@ #define CONFIG_SDRC /* Has an SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
/* * Display CPU and Board information diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 840e108e0536..4b4f10410543 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -16,7 +16,7 @@
#include <asm/arch/cpu.h> -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#ifndef CONFIG_SPL_BUILD # define CONFIG_OMAP_SERIAL diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index 10ac4a46bc4a..b105ffd9f18b 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -32,7 +32,7 @@ #define CONFIG_SDRC /* The chip has SDRC controller */
#include <asm/arch/cpu.h> /* get chip and board defs */ -#include <asm/arch/omap3.h> +#include <asm/arch/omap.h>
#define CONFIG_SYS_GENERIC_BOARD
On Mon, Mar 09, 2015 at 05:12:04PM -0500, Nishanth Menon wrote:
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Mon, Mar 09, 2015 at 05:12:04PM -0500, Nishanth Menon wrote:
This is in preperation of using generic cross OMAP code.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap-common/Makefile | 2 +- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 2 ++ arch/arm/cpu/armv7/omap3/board.c | 6 ++---- arch/arm/cpu/armv7/omap3/lowlevel_init.S | 11 ----------- arch/arm/include/asm/arch-omap3/sys_proto.h | 1 - 5 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 7695e16d36f5..f3725b267c99 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -28,7 +28,7 @@ endif
ifeq ($(CONFIG_OMAP34XX),) obj-y += boot-common.o -obj-y += lowlevel_init.o endif +obj-y += lowlevel_init.o
obj-y += mem-common.o diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 80619b04df5d..746df922c27d 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -16,11 +16,13 @@ #include <asm/arch/spl.h> #include <linux/linkage.h>
+#ifndef CONFIG_OMAP34XX ENTRY(save_boot_params) ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS str r0, [r1] b save_boot_params_ret ENDPROC(save_boot_params) +#endif
ENTRY(omap_smc1) PUSH {r4-r12, lr} @ save registers - ROM code may pollute diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index dd53b207f850..6e6a95762b8d 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -429,8 +429,7 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) acr |= set_bits;
if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR, - acr); + omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); } else { struct emu_hal_params emu_romcode_params; emu_romcode_params.num_params = 1; @@ -470,8 +469,7 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) static void omap3_invalidate_l2_cache_secure(void) { if (get_device_type() == GP_DEVICE) { - omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, - 0); + omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0); } else { struct emu_hal_params emu_romcode_params; emu_romcode_params.num_params = 1; diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 80cb2639f60c..7a691519bb6b 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -27,17 +27,6 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) #endif
-ENTRY(omap3_gp_romcode_call) - PUSH {r4-r12, lr} @ Save all registers from ROM code! - MOV r12, r0 @ Copy the Service ID in R12 - MOV r0, r1 @ Copy parameter to R0 - mcr p15, 0, r0, c7, c10, 4 @ DSB - mcr p15, 0, r0, c7, c10, 5 @ DMB - .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled - @ because we use -march=armv5 - POP {r4-r12, pc} -ENDPROC(omap3_gp_romcode_call) - /* * Funtion for making PPA HAL API calls in secure devices * Input: diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index bcf92fbe658b..0c77a22ccfff 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -73,6 +73,5 @@ void power_init_r(void); void dieid_num_r(void); void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); -void omap3_gp_romcode_call(u32 service_id, u32 parameter); u32 warm_reset(void); #endif
On Mon, Mar 09, 2015 at 05:12:05PM -0500, Nishanth Menon wrote:
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
But I've always wondered, does OMAP3 not actually pass in the same info in the same location / manner as OMAP4 and later?
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini trini@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:12:05PM -0500, Nishanth Menon wrote:
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
But I've always wondered, does OMAP3 not actually pass in the same info in the same location / manner as OMAP4 and later?
For smc call, the calls are similar, but the parameters change
On Wed, Mar 11, 2015 at 10:53:41AM -0500, Nishanth Menon wrote:
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini trini@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:12:05PM -0500, Nishanth Menon wrote:
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
But I've always wondered, does OMAP3 not actually pass in the same info in the same location / manner as OMAP4 and later?
For smc call, the calls are similar, but the parameters change
Right, sorry but I mean for boot params as that's what's still being omap3-specific in lowlevel_init.S
On Wed, Mar 11, 2015 at 11:00 AM, Tom Rini trini@konsulko.com wrote:
On Wed, Mar 11, 2015 at 10:53:41AM -0500, Nishanth Menon wrote:
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini trini@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:12:05PM -0500, Nishanth Menon wrote:
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
But I've always wondered, does OMAP3 not actually pass in the same info in the same location / manner as OMAP4 and later?
For smc call, the calls are similar, but the parameters change
Right, sorry but I mean for boot params as that's what's still being omap3-specific in lowlevel_init.S
There seemed to be differences w.r.t bootdevice detection logic which seems to be extensive in omap3 :( had'nt dug too much there :(
Le mercredi 11 mars 2015 à 11:04 -0500, Nishanth Menon a écrit :
On Wed, Mar 11, 2015 at 11:00 AM, Tom Rini trini@konsulko.com wrote:
On Wed, Mar 11, 2015 at 10:53:41AM -0500, Nishanth Menon wrote:
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini trini@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:12:05PM -0500, Nishanth Menon wrote:
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
But I've always wondered, does OMAP3 not actually pass in the same info in the same location / manner as OMAP4 and later?
For smc call, the calls are similar, but the parameters change
Right, sorry but I mean for boot params as that's what's still being omap3-specific in lowlevel_init.S
There seemed to be differences w.r.t bootdevice detection logic which seems to be extensive in omap3 :( had'nt dug too much there :(
As far as I can see, the main difference is that omap4/5 are using SRAM to store various bits such as the boot device (OMAP_SRAM_SCRATCH_BOOT_PARAMS). On omap3, that logic is not used and a global variable (omap3_boot_device) is there instead.
We could easily make that logic fit omap3 as well and get rid of the global variable. I also see a few functions from omap-common's hwinit-common.c that could be reused on omap3.
I could start looking into that, even though again, I don't have many OMAP devices to test with.
On Wed, Mar 11, 2015 at 09:26:43PM +0100, Paul Kocialkowski wrote:
Le mercredi 11 mars 2015 à 11:04 -0500, Nishanth Menon a écrit :
On Wed, Mar 11, 2015 at 11:00 AM, Tom Rini trini@konsulko.com wrote:
On Wed, Mar 11, 2015 at 10:53:41AM -0500, Nishanth Menon wrote:
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini trini@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:12:05PM -0500, Nishanth Menon wrote:
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
But I've always wondered, does OMAP3 not actually pass in the same info in the same location / manner as OMAP4 and later?
For smc call, the calls are similar, but the parameters change
Right, sorry but I mean for boot params as that's what's still being omap3-specific in lowlevel_init.S
There seemed to be differences w.r.t bootdevice detection logic which seems to be extensive in omap3 :( had'nt dug too much there :(
As far as I can see, the main difference is that omap4/5 are using SRAM to store various bits such as the boot device (OMAP_SRAM_SCRATCH_BOOT_PARAMS). On omap3, that logic is not used and a global variable (omap3_boot_device) is there instead.
We could easily make that logic fit omap3 as well and get rid of the global variable. I also see a few functions from omap-common's hwinit-common.c that could be reused on omap3.
I could start looking into that, even though again, I don't have many OMAP devices to test with.
Right, but is the data format the same or did it change, in what we're reading?
Le mercredi 11 mars 2015 à 17:16 -0400, Tom Rini a écrit :
On Wed, Mar 11, 2015 at 09:26:43PM +0100, Paul Kocialkowski wrote:
Le mercredi 11 mars 2015 à 11:04 -0500, Nishanth Menon a écrit :
On Wed, Mar 11, 2015 at 11:00 AM, Tom Rini trini@konsulko.com wrote:
On Wed, Mar 11, 2015 at 10:53:41AM -0500, Nishanth Menon wrote:
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini trini@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:12:05PM -0500, Nishanth Menon wrote:
> omap_smc1 is now generic enough to remove duplicate > omap3_gp_romcode_call logic that omap3 introduced. > > As part of this change, move to using the generic lowlevel_init.S for > omap3 as well. > > Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
But I've always wondered, does OMAP3 not actually pass in the same info in the same location / manner as OMAP4 and later?
For smc call, the calls are similar, but the parameters change
Right, sorry but I mean for boot params as that's what's still being omap3-specific in lowlevel_init.S
There seemed to be differences w.r.t bootdevice detection logic which seems to be extensive in omap3 :( had'nt dug too much there :(
As far as I can see, the main difference is that omap4/5 are using SRAM to store various bits such as the boot device (OMAP_SRAM_SCRATCH_BOOT_PARAMS). On omap3, that logic is not used and a global variable (omap3_boot_device) is there instead.
We could easily make that logic fit omap3 as well and get rid of the global variable. I also see a few functions from omap-common's hwinit-common.c that could be reused on omap3.
I could start looking into that, even though again, I don't have many OMAP devices to test with.
Right, but is the data format the same or did it change, in what we're reading?
The boot structure is very similar (at least between omap3 and omap4). This is chapter 27.4.8.4 Image Execution of the OMAP4430 TRM and chapter 26.4.8.4 Image Execution of the OMAP36xx TRM.
There is some padding difference between omap3 and omap4, but nothing we can't deal with in omap-common.c's save_omap_boot_params: some offsets are already defined at omap_boot.h, we probably just need to adjust those for omap3.
On Mon, Mar 09, 2015 at 05:12:05PM -0500, Nishanth Menon wrote:
omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced.
As part of this change, move to using the generic lowlevel_init.S for omap3 as well.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
From: Praveen Rao prao@ti.com
This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well.
Signed-off-by: Praveen Rao prao@ti.com Signed-off-by: Angela Stegmaier angelabaker@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/hwinit.c | 7 +++++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 3 +++ include/configs/ti_omap5_common.h | 3 +++ 3 files changed, 13 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index a8a474a88be9..f8060555b680 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -381,3 +381,10 @@ void setup_warmreset_time(void) rst_val |= rst_time; writel(rst_val, (*prcm)->prm_rsttime); } + +void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, + u32 cpu_rev_comb, u32 cpu_variant, + u32 cpu_rev) +{ + omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl); +} diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 103830319a41..ea84665f5b97 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -66,4 +66,7 @@ static inline u32 usec_to_32k(u32 usec) { return div_round_up(32768 * usec, 1000000); } + +#define OMAP5_SERVICE_L2ACTLR_SET 0x104 + #endif diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 925cb42dd38d..09f05f18a75d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -21,6 +21,9 @@ #define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ARCH_CPU_INIT
+/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_798870 + #define CONFIG_SYS_CACHELINE_SIZE 64
/* Use General purpose timer 1 */
On Mon, Mar 09, 2015 at 05:12:06PM -0500, Nishanth Menon wrote:
From: Praveen Rao prao@ti.com
This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well.
Signed-off-by: Praveen Rao prao@ti.com Signed-off-by: Angela Stegmaier angelabaker@ti.com Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Mon, Mar 09, 2015 at 05:12:06PM -0500, Nishanth Menon wrote:
From: Praveen Rao prao@ti.com
This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock."
An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well.
Signed-off-by: Praveen Rao prao@ti.com Signed-off-by: Angela Stegmaier angelabaker@ti.com Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala vchengalvala@ti.com Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap5/hwinit.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index f8060555b680..8d6b59eeb044 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -304,6 +304,21 @@ void config_data_eye_leveling_samples(u32 emif_base) (*ctrl)->control_emif2_sdram_config_ext); }
+void init_cpu_configuration(void) +{ + u32 l2actlr; + + asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr)); + /* + * L2ACTLR: Ensure to enable the following: + * 3: Disable clean/evict push to external + * 4: Disable WriteUnique and WriteLineUnique transactions from master + * 8: Disable DVM/CMO message broadcast + */ + l2actlr |= 0x118; + omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr); +} + void init_omap_revision(void) { /* @@ -342,6 +357,7 @@ void init_omap_revision(void) default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } + init_cpu_configuration(); }
void reset_cpu(ulong ignored)
On Mon, Mar 09, 2015 at 05:12:07PM -0500, Nishanth Menon wrote:
Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala vchengalvala@ti.com Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Mon, Mar 09, 2015 at 05:12:07PM -0500, Nishanth Menon wrote:
Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance.
These apply to both OMAP5 and DRA7.
Reported-by: Vivek Chengalvala vchengalvala@ti.com Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap3/board.c | 31 ++++++++++--------------------- include/configs/am3517_crane.h | 4 ++++ include/configs/am3517_evm.h | 4 ++++ include/configs/cm_t35.h | 4 ++++ include/configs/cm_t3517.h | 4 ++++ include/configs/dig297.h | 4 ++++ include/configs/mcx.h | 4 ++++ include/configs/omap3_evm_common.h | 4 ++++ include/configs/omap3_logic.h | 4 ++++ include/configs/omap3_mvblx.h | 4 ++++ include/configs/omap3_pandora.h | 4 ++++ include/configs/omap3_sdp3430.h | 4 ++++ include/configs/tam3517-common.h | 4 ++++ include/configs/tao3530.h | 4 ++++ include/configs/ti_omap3_common.h | 5 +++++ include/configs/tricorder.h | 4 ++++ 16 files changed, 71 insertions(+), 21 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 6e6a95762b8d..51a1c5816c3e 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -35,7 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
/* Declarations */ extern omap3_sysinfo sysinfo; -static void omap3_setup_aux_cr(void); #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_invalidate_l2_cache_secure(void); #endif @@ -244,9 +243,6 @@ void s_init(void)
try_unlock_memory();
- /* Errata workarounds */ - omap3_setup_aux_cr(); - #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ omap3_invalidate_l2_cache_secure(); @@ -419,15 +415,9 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); }
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) { - u32 acr; - - /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - if (get_device_type() == GP_DEVICE) { omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); } else { @@ -439,16 +429,15 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) } }
-static void omap3_setup_aux_cr(void) +static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) { - /* Workaround for Cortex-A8 errata: #454179 #430973 - * Set "IBE" bit - * Set "Disable Branch Size Mispredicts" bit - * Workaround for erratum #621766 - * Enable L1NEON bit - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0 - */ - omap3_update_aux_cr_secure(0xE0, 0); + u32 acr; + + /* Read ACR */ + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); + acr &= ~clear_bits; + acr |= set_bits; + v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); }
#ifndef CONFIG_SYS_L2CACHE_OFF diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 87c850e05df1..c3c9169d0555 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -19,6 +19,10 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index c4e19e79b95a..31e758d81bdd 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -19,6 +19,10 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index e2d5bbb0955d..3eb7886eb69e 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -26,6 +26,10 @@ #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index ee1b7a0cb5a7..8c6313832250 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -17,6 +17,10 @@ #define CONFIG_CM_T3517 /* working with CM-T3517 */ #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 8791199fc61d..932640112b3a 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -23,6 +23,10 @@ #define MACH_TYPE_OMAP3_CPS 2751 #endif #define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
/* * High Level Configuration Options diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 2cf66c40d6fe..3fd31842451d 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -16,6 +16,10 @@ #define CONFIG_OMAP3_MCX /* working with mcx */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define MACH_TYPE_MCX 3656 #define CONFIG_MACH_TYPE MACH_TYPE_MCX diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index e7df15400d37..370f21e3ee6d 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -15,6 +15,10 @@ #define CONFIG_OMAP /* This is TI OMAP core */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index fcef46735835..13cd35b16a03 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -18,6 +18,10 @@ #define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80400000
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h index 20ec3ad15439..b61297f9ee94 100644 --- a/include/configs/omap3_mvblx.h +++ b/include/configs/omap3_mvblx.h @@ -23,6 +23,10 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index b92d67abccf9..11d7b86eb10d 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -17,6 +17,10 @@ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index bf5c7a8faf77..1ca79d4ee4dd 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -23,6 +23,10 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SDRC /* The chip has SDRC controller */
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index dea4044d9fbb..2d12e86566cd 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -17,6 +17,10 @@ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_SYS_TEXT_BASE 0x80008000
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index f3e0088d5a00..49ed79ffbc0b 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -21,6 +21,10 @@ #define CONFIG_OMAP_GPIO #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define MACH_TYPE_OMAP3_TAO3530 2836
diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 4b4f10410543..429b109afa23 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -22,6 +22,11 @@ # define CONFIG_OMAP_SERIAL #endif
+/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 + /* The chip has SDRC controller */ #define CONFIG_SDRC
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index b105ffd9f18b..7426bde8a0c2 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -19,6 +19,10 @@ /* High Level Configuration Options */ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER /*
On Mon, Mar 09, 2015 at 05:12:08PM -0500, Nishanth Menon wrote:
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On Mon, Mar 09, 2015 at 05:12:08PM -0500, Nishanth Menon wrote:
Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this.
While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766.
Signed-off-by: Nishanth Menon nm@ti.com --- arch/arm/cpu/armv7/omap3/board.c | 45 ++++++++++++--------------- arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + board/nokia/rx51/rx51.c | 19 ++++++----- include/configs/nokia_rx51.h | 4 +++ 4 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index 51a1c5816c3e..b064c0cc8343 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -415,31 +415,30 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); }
-void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, - u32 cpu_variant, u32 cpu_rev) +void __weak omap3_set_aux_cr_secure(u32 acr) { - if (get_device_type() == GP_DEVICE) { - omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); - } else { - struct emu_hal_params emu_romcode_params; - emu_romcode_params.num_params = 1; - emu_romcode_params.param1 = acr; - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, - (u32 *)&emu_romcode_params); - } + struct emu_hal_params emu_romcode_params; + + emu_romcode_params.num_params = 1; + emu_romcode_params.param1 = acr; + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, + (u32 *)&emu_romcode_params); }
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits) +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, + u32 cpu_variant, u32 cpu_rev) { - u32 acr; + /* Write ACR - affects secure banked bits */ + if (get_device_type() == GP_DEVICE) + omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr); + else + omap3_set_aux_cr_secure(acr);
- /* Read ACR */ - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); - acr &= ~clear_bits; - acr |= set_bits; - v7_arch_cp15_set_acr(acr, 0, 0, 0, 0); + /* Write ACR - affects non-secure banked bits - some erratas need it */ + asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); }
+ #ifndef CONFIG_SYS_L2CACHE_OFF static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) { @@ -449,9 +448,8 @@ static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); acr &= ~clear_bits; acr |= set_bits; + v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
- /* Write ACR - affects non-secure banked bits */ - asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr)); }
/* Invalidate the entire L2 cache from secure mode */ @@ -470,10 +468,9 @@ static void omap3_invalidate_l2_cache_secure(void)
void v7_outer_cache_enable(void) { - /* Set L2EN */ - omap3_update_aux_cr_secure(0x2, 0);
/* + * Set L2EN * On some revisions L2EN bit is banked on some revisions it's not * No harm in setting both banked bits(in fact this is required * by an erratum) @@ -483,10 +480,8 @@ void v7_outer_cache_enable(void)
void omap3_outer_cache_disable(void) { - /* Clear L2EN */ - omap3_update_aux_cr_secure(0, 0x2); - /* + * Clear L2EN * On some revisions L2EN bit is banked on some revisions it's not * No harm in clearing both banked bits(in fact this is required * by an erratum) diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 0c77a22ccfff..3e45ce184ba4 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -73,5 +73,6 @@ void power_init_r(void); void dieid_num_r(void); void get_dieid(u32 *id); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); +void omap3_set_aux_cr_secure(u32 acr); u32 warm_reset(void); #endif diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c index 08fcaf21b3c6..3d019b01428b 100644 --- a/board/nokia/rx51/rx51.c +++ b/board/nokia/rx51/rx51.c @@ -341,6 +341,17 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA); }
+void omap3_set_aux_cr_secure(u32 acr) +{ + struct emu_hal_params_rx51 emu_romcode_params = { 0, }; + + emu_romcode_params.num_params = 2; + emu_romcode_params.param1 = acr; + + omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, + (u32 *)&emu_romcode_params); +} + /* * Routine: omap3_update_aux_cr_secure_rx51 * Description: Modify the contents Auxiliary Control Register. @@ -350,19 +361,13 @@ static void omap3_emu_romcode_call(u32 service_id, u32 *parameters) */ static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits) { - struct emu_hal_params_rx51 emu_romcode_params = { 0, }; u32 acr;
/* Read ACR */ asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr)); acr &= ~clear_bits; acr |= set_bits; - - emu_romcode_params.num_params = 2; - emu_romcode_params.param1 = acr; - - omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR, - (u32 *)&emu_romcode_params); + omap3_set_aux_cr_secure(acr); }
/* diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 442e16ae686b..152a6e564b00 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -29,6 +29,10 @@ #define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ #define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766
#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
On Mon, Mar 09, 2015 at 05:12:09PM -0500, Nishanth Menon wrote:
RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this.
While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766.
Signed-off-by: Nishanth Menon nm@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
But I'd really like to see a test on real hardware, Pali?
On Mon, Mar 09, 2015 at 05:12:09PM -0500, Nishanth Menon wrote:
RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this.
While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766.
Signed-off-by: Nishanth Menon nm@ti.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!
On Mon, Mar 09, 2015 at 05:11:58PM -0500, Nishanth Menon wrote:
The sixth revision should be proper, I hope. (skipping all the blurb and pointing to v1 for the blurb).
Changes since v5:
- omap_smc1 is now in omap_common.h
- I hope we can pick up Matt's Tested-by tag from previous rev.. http://article.gmane.org/gmane.comp.boot-loaders.u-boot/214277
In the future please collect those :) Or would that be too different from kernel policy?
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini trini@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:11:58PM -0500, Nishanth Menon wrote:
The sixth revision should be proper, I hope. (skipping all the blurb and pointing to v1 for the blurb).
Changes since v5: - omap_smc1 is now in omap_common.h - I hope we can pick up Matt's Tested-by tag from previous rev.. http://article.gmane.org/gmane.comp.boot-loaders.u-boot/214277
In the future please collect those :) Or would that be too different from kernel policy?
I did change code as per rev5 review comments, so was'nt too sure if i could carry the "tested-by" tag over..
Regards, Nishanth Menon
On Wed, Mar 11, 2015 at 10:51:12AM -0500, Nishanth Menon wrote:
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini trini@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:11:58PM -0500, Nishanth Menon wrote:
The sixth revision should be proper, I hope. (skipping all the blurb and pointing to v1 for the blurb).
Changes since v5: - omap_smc1 is now in omap_common.h - I hope we can pick up Matt's Tested-by tag from previous rev.. http://article.gmane.org/gmane.comp.boot-loaders.u-boot/214277
In the future please collect those :) Or would that be too different from kernel policy?
I did change code as per rev5 review comments, so was'nt too sure if i could carry the "tested-by" tag over..
Ah yes. Matt, would you have time to test it all again? Thanks!
On Wed, Mar 11, 2015 at 12:00:59PM -0400, Tom Rini wrote:
On Wed, Mar 11, 2015 at 10:51:12AM -0500, Nishanth Menon wrote:
On Wed, Mar 11, 2015 at 10:48 AM, Tom Rini trini@konsulko.com wrote:
On Mon, Mar 09, 2015 at 05:11:58PM -0500, Nishanth Menon wrote:
The sixth revision should be proper, I hope. (skipping all the blurb and pointing to v1 for the blurb).
Changes since v5: - omap_smc1 is now in omap_common.h - I hope we can pick up Matt's Tested-by tag from previous rev.. http://article.gmane.org/gmane.comp.boot-loaders.u-boot/214277
In the future please collect those :) Or would that be too different from kernel policy?
I did change code as per rev5 review comments, so was'nt too sure if i could carry the "tested-by" tag over..
Ah yes. Matt, would you have time to test it all again? Thanks!
Yes.
Reconfirmed that v6 is working properly on both beagles. The xM has the erratum workaround applied and the omap3530 beagleboard does not have it applied as expected. Feel free to keep my Tested-by.
-Matt
participants (4)
-
Matt Porter -
Nishanth Menon -
Paul Kocialkowski -
Tom Rini