From: Ryan Chen ryan_chen@aspeedtech.com

This patch adds the clock control driver for the AST2600 SoC.

Signed-off-by: Ryan Chen ryan_chen@aspeedtech.com Signed-off-by: Chia-Wei, Wang chiawei_wang@aspeedtech.com --- .../arm/include/asm/arch-aspeed/scu_ast2600.h | 338 +++++ drivers/clk/aspeed/Makefile | 1 + drivers/clk/aspeed/clk_ast2600.c | 1173 +++++++++++++++++ include/dt-bindings/clock/ast2600-clock.h | 62 + 4 files changed, 1574 insertions(+) create mode 100644 arch/arm/include/asm/arch-aspeed/scu_ast2600.h create mode 100644 drivers/clk/aspeed/clk_ast2600.c create mode 100644 include/dt-bindings/clock/ast2600-clock.h

diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2600.h b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h new file mode 100644 index 0000000000..a205fb1f76 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2600.h @@ -0,0 +1,338 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef _ASM_ARCH_SCU_AST2600_H +#define _ASM_ARCH_SCU_AST2600_H + +#define SCU_UNLOCK_KEY 0x1688a8a8 + +#define SCU_CLKGATE1_EMMC BIT(27) +#define SCU_CLKGATE1_MAC2 BIT(21) +#define SCU_CLKGATE1_MAC1 BIT(20) +#define SCU_CLKGATE1_USB_HUB BIT(14) +#define SCU_CLKGATE1_USB_HOST2 BIT(7) + +#define SCU_CLKGATE2_FSI BIT(30) +#define SCU_CLKGATE2_MAC4 BIT(21) +#define SCU_CLKGATE2_MAC3 BIT(20) +#define SCU_CLKGATE2_SDIO BIT(4) + +#define SCU_DRAM_HDSHK_SOC_INIT BIT(7) +#define SCU_DRAM_HDSHK_RDY BIT(6) + +#define SCU_CLKSRC1_ECC_RSA_DIV_MASK GENMASK(27, 26) +#define SCU_CLKSRC1_ECC_RSA_DIV_SHIFT 26 +#define SCU_CLKSRC1_PCLK_DIV_MASK GENMASK(25, 23) +#define SCU_CLKSRC1_PCLK_DIV_SHIFT 23 +#define SCU_CLKSRC1_BCLK_DIV_MASK GENMASK(22, 20) +#define SCU_CLKSRC1_BCLK_DIV_SHIFT 20 +#define SCU_CLKSRC1_ECC_RSA BIT(19) +#define SCU_CLKSRC1_MAC_DIV_MASK GENMASK(18, 16) +#define SCU_CLKSRC1_MAC_DIV_SHIFT 16 +#define SCU_CLKSRC1_EMMC_EN BIT(15) +#define SCU_CLKSRC1_EMMC_DIV_MASK GENMASK(14, 12) +#define SCU_CLKSRC1_EMMC_DIV_SHIFT 12 +#define SCU_CLKSRC1_EMMC BIT(11) + +#define SCU_CLKSRC2_RMII12 BIT(19) +#define SCU_CLKSRC2_RMII12_DIV_MASK GENMASK(18, 16) +#define SCU_CLKSRC2_RMII12_DIV_SHIFT 16 +#define SCU_CLKSRC2_UART5 BIT(14) + +#define SCU_CLKSRC4_SDIO_EN BIT(31) +#define SCU_CLKSRC4_SDIO_DIV_MASK GENMASK(30, 28) +#define SCU_CLKSRC4_SDIO_DIV_SHIFT 28 +#define SCU_CLKSRC4_MAC_DIV_MASK GENMASK(26, 24) +#define SCU_CLKSRC4_MAC_DIV_SHIFT 24 +#define SCU_CLKSRC4_RMII34_DIV_MASK GENMASK(18, 16) +#define SCU_CLKSRC4_RMII34_DIV_SHIFT 16 +#define SCU_CLKSRC4_PCLK_DIV_MASK GENMASK(11, 9) +#define SCU_CLKSRC4_PCLK_DIV_SHIFT 9 +#define SCU_CLKSRC4_SDIO BIT(8) +#define SCU_CLKSRC4_UART6 BIT(5) +#define SCU_CLKSRC4_UART4 BIT(3) +#define SCU_CLKSRC4_UART3 BIT(2) +#define SCU_CLKSRC4_UART2 BIT(1) +#define SCU_CLKSRC4_UART1 BIT(0) + +#define SCU_CLKSRC5_UART13 BIT(12) +#define SCU_CLKSRC5_UART12 BIT(11) +#define SCU_CLKSRC5_UART11 BIT(10) +#define SCU_CLKSRC5_UART10 BIT(9) +#define SCU_CLKSRC5_UART9 BIT(8) +#define SCU_CLKSRC5_UART8 BIT(7) +#define SCU_CLKSRC5_UART7 BIT(6) +#define SCU_CLKSRC5_HUXCLK_MASK GENMASK(5, 3) +#define SCU_CLKSRC5_HUXCLK_SHIFT 3 +#define SCU_CLKSRC5_UXCLK_MASK GENMASK(2, 0) +#define SCU_CLKSRC5_UXCLK_SHIFT 0 + +#define SCU_PINCTRL1_EMMC_MASK GENMASK(31, 24) +#define SCU_PINCTRL1_EMMC_SHIFT 24 + +#define SCU_PINCTRL16_MAC4_DRIVING_MASK GENMASK(3, 2) +#define SCU_PINCTRL16_MAC4_DRIVING_SHIFT 2 +#define SCU_PINCTRL16_MAC3_DRIVING_MASK GENMASK(1, 0) +#define SCU_PINCTRL16_MAC3_DRIVING_SHIFT 0 + +#define SCU_HWSTRAP1_CPU_AXI_CLK_RATIO BIT(16) +#define SCU_HWSTRAP1_VGA_MEM_MASK GENMASK(14, 13) +#define SCU_HWSTRAP1_VGA_MEM_SHIFT 13 +#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK GENMASK(12, 11) +#define SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT 11 +#define SCU_HWSTRAP1_CPU_FREQ_MASK GENMASK(10, 8) +#define SCU_HWSTRAP1_CPU_FREQ_SHIFT 8 +#define SCU_HWSTRAP1_MAC2_INTF BIT(7) +#define SCU_HWSTRAP1_MAC1_INTF BIT(6) + +#define SCU_EFUSE_DIS_DP BIT(17) +#define SCU_EFUSE_DIS_VGA BIT(14) +#define SCU_EFUSE_DIS_PCIE_EP BIT(13) +#define SCU_EFUSE_DIS_USB BIT(12) +#define SCU_EFUSE_DIS_RVAS BIT(10) +#define SCU_EFUSE_DIS_VIDEO_DEC BIT(9) +#define SCU_EFUSE_DIS_VIDEO BIT(8) +#define SCU_EFUSE_DIS_PCIE_RC BIT(7) +#define SCU_EFUSE_DIS_CM3 BIT(6) +#define SCU_EFUSE_DIS_CA7 BIT(5) + +#define SCU_PLL_RST BIT(25) +#define SCU_PLL_BYPASS BIT(24) +#define SCU_PLL_OFF BIT(23) +#define SCU_PLL_DIV_MASK GENMASK(22, 19) +#define SCU_PLL_DIV_SHIFT 19 +#define SCU_PLL_DENUM_MASK GENMASK(18, 13) +#define SCU_PLL_DENUM_SHIFT 13 +#define SCU_PLL_NUM_MASK GENMASK(12, 0) +#define SCU_PLL_NUM_SHIFT 0 + +#define SCU_UART_CLKGEN_N_MASK GENMASK(17, 8) +#define SCU_UART_CLKGEN_N_SHIFT 8 +#define SCU_UART_CLKGEN_R_MASK GENMASK(7, 0) +#define SCU_UART_CLKGEN_R_SHIFT 0 + +#define SCU_HUART_CLKGEN_N_MASK GENMASK(17, 8) +#define SCU_HUART_CLKGEN_N_SHIFT 8 +#define SCU_HUART_CLKGEN_R_MASK GENMASK(7, 0) +#define SCU_HUART_CLKGEN_R_SHIFT 0 + +#define SCU_MISC_CTRL1_UART5_DIV BIT(12) + +#ifndef __ASSEMBLY__ +struct ast2600_scu { + uint32_t prot_key1; /* 0x000 */ + uint32_t chip_id1; /* 0x004 */ + uint32_t rsv_0x08; /* 0x008 */ + uint32_t rsv_0x0c; /* 0x00C */ + uint32_t prot_key2; /* 0x010 */ + uint32_t chip_id2; /* 0x014 */ + uint32_t rsv_0x18[10]; /* 0x018 ~ 0x03C */ + uint32_t modrst_ctrl1; /* 0x040 */ + uint32_t modrst_clr1; /* 0x044 */ + uint32_t rsv_0x48; /* 0x048 */ + uint32_t rsv_0x4C; /* 0x04C */ + uint32_t modrst_ctrl2; /* 0x050 */ + uint32_t modrst_clr2; /* 0x054 */ + uint32_t rsv_0x58; /* 0x058 */ + uint32_t rsv_0x5C; /* 0x05C */ + uint32_t extrst_sel1; /* 0x060 */ + uint32_t sysrst_sts1_1; /* 0x064 */ + uint32_t sysrst_sts1_2; /* 0x068 */ + uint32_t sysrst_sts1_3; /* 0x06C */ + uint32_t extrst_sel2; /* 0x070 */ + uint32_t sysrst_sts2_1; /* 0x074 */ + uint32_t sysrst_sts2_2; /* 0x078 */ + uint32_t stsrst_sts3_2; /* 0x07C */ + uint32_t clkgate_ctrl1; /* 0x080 */ + uint32_t clkgate_clr1; /* 0x084 */ + uint32_t rsv_0x88; /* 0x088 */ + uint32_t rsv_0x8C; /* 0x08C */ + uint32_t clkgate_ctrl2; /* 0x090 */ + uint32_t clkgate_clr2; /* 0x094 */ + uint32_t rsv_0x98[10]; /* 0x098 ~ 0x0BC */ + uint32_t misc_ctrl1; /* 0x0C0 */ + uint32_t misc_ctrl2; /* 0x0C4 */ + uint32_t debug_ctrl1; /* 0x0C8 */ + uint32_t rsv_0xCC; /* 0x0CC */ + uint32_t misc_ctrl3; /* 0x0D0 */ + uint32_t misc_ctrl4; /* 0x0D4 */ + uint32_t debug_ctrl2; /* 0x0D8 */ + uint32_t rsv_0xdc[9]; /* 0x0DC ~ 0x0FC */ + uint32_t dram_hdshk; /* 0x100 */ + uint32_t soc_scratch[3]; /* 0x104 ~ 0x10C */ + uint32_t rsv_0x110[4]; /* 0x110 ~ 0x11C*/ + uint32_t cpu_scratch_wp; /* 0x120 */ + uint32_t rsv_0x124[23]; /* 0x124 */ + uint32_t smp_boot[12]; /* 0x180 */ + uint32_t cpu_scratch[20]; /* 0x1b0 */ + uint32_t hpll; /* 0x200 */ + uint32_t hpll_ext; /* 0x204 */ + uint32_t rsv_0x208[2]; /* 0x208 ~ 0x20C */ + uint32_t apll; /* 0x210 */ + uint32_t apll_ext; /* 0x214 */ + uint32_t rsv_0x218[2]; /* 0x218 ~ 0x21C */ + uint32_t mpll; /* 0x220 */ + uint32_t mpll_ext; /* 0x224 */ + uint32_t rsv_0x228[6]; /* 0x228 ~ 0x23C */ + uint32_t epll; /* 0x240 */ + uint32_t epll_ext; /* 0x244 */ + uint32_t rsv_0x248[6]; /* 0x248 ~ 0x25C */ + uint32_t dpll; /* 0x260 */ + uint32_t dpll_ext; /* 0x264 */ + uint32_t rsv_0x268[38]; /* 0x268 ~ 0x2FC */ + uint32_t clksrc1; /* 0x300 */ + uint32_t clksrc2; /* 0x304 */ + uint32_t clksrc3; /* 0x308 */ + uint32_t rsv_0x30c; /* 0x30C */ + uint32_t clksrc4; /* 0x310 */ + uint32_t clksrc5; /* 0x314 */ + uint32_t rsv_0x318[2]; /* 0x318 ~ 0x31C */ + uint32_t freq_counter_ctrl1; /* 0x320 */ + uint32_t freq_counter_cmp1; /* 0x324 */ + uint32_t rsv_0x328[2]; /* 0x328 ~ 0x32C */ + uint32_t freq_counter_ctrl2; /* 0x330 */ + uint32_t freq_counter_cmp2; /* 0x334 */ + uint32_t uart_clkgen; /* 0x338 */ + uint32_t huart_clkgen; /* 0x33C */ + uint32_t mac12_clk_delay; /* 0x340 */ + uint32_t rsv_0x344; /* 0x344 */ + uint32_t mac12_clk_delay_100M; /* 0x348 */ + uint32_t mac12_clk_delay_10M; /* 0x34C */ + uint32_t mac34_clk_delay; /* 0x350 */ + uint32_t rsv_0x354; /* 0x354 */ + uint32_t mac34_clk_delay_100M; /* 0x358 */ + uint32_t mac34_clk_delay_10M; /* 0x35C */ + uint32_t clkduty_meas_ctrl; /* 0x360 */ + uint32_t clkduty1; /* 0x364 */ + uint32_t clkduty2; /* 0x368 */ + uint32_t clkduty_meas_res; /* 0x36C */ + uint32_t clkduty_meas_ctrl2; /* 0x370 */ + uint32_t clkduty3; /* 0x374 */ + uint32_t rsv_0x378[34]; /* 0x378 ~ 0x3FC */ + uint32_t pinmux1; /* 0x400 */ + uint32_t pinmux2; /* 0x404 */ + uint32_t rsv_0x408; /* 0x408 */ + uint32_t pinmux3; /* 0x40C */ + uint32_t pinmux4; /* 0x410 */ + uint32_t pinmux5; /* 0x414 */ + uint32_t pinmux6; /* 0x418 */ + uint32_t pinmux7; /* 0x41C */ + uint32_t rsv_0x420[4]; /* 0x420 ~ 0x42C */ + uint32_t pinmux8; /* 0x430 */ + uint32_t pinmux9; /* 0x434 */ + uint32_t pinmux10; /* 0x438 */ + uint32_t rsv_0x43c; /* 0x43C */ + uint32_t pinmux12; /* 0x440 */ + uint32_t pinmux13; /* 0x444 */ + uint32_t rsv_0x448[2]; /* 0x448 ~ 0x44C */ + uint32_t pinmux14; /* 0x450 */ + uint32_t pinmux15; /* 0x454 */ + uint32_t pinmux16; /* 0x458 */ + uint32_t rsv_0x45c[21]; /* 0x45C ~ 0x4AC */ + uint32_t pinmux17; /* 0x4B0 */ + uint32_t pinmux18; /* 0x4B4 */ + uint32_t pinmux19; /* 0x4B8 */ + uint32_t pinmux20; /* 0x4BC */ + uint32_t rsv_0x4c0[5]; /* 0x4C0 ~ 0x4D0 */ + uint32_t pinmux22; /* 0x4D4 */ + uint32_t pinmux23; /* 0x4D8 */ + uint32_t rsv_0x4dc[9]; /* 0x4DC ~ 0x4FC */ + uint32_t hwstrap1; /* 0x500 */ + uint32_t hwstrap_clr1; /* 0x504 */ + uint32_t hwstrap_prot1; /* 0x508 */ + uint32_t rsv_0x50c; /* 0x50C */ + uint32_t hwstrap2; /* 0x510 */ + uint32_t hwstrap_clr2; /* 0x514 */ + uint32_t hwstrap_prot2; /* 0x518 */ + uint32_t rsv_0x51c; /* 0x51C */ + uint32_t rng_ctrl; /* 0x520 */ + uint32_t rng_data; /* 0x524 */ + uint32_t rsv_0x528[6]; /* 0x528 ~ 0x53C */ + uint32_t pwr_save_wakeup_en1; /* 0x540 */ + uint32_t pwr_save_wakeup_ctrl1; /* 0x544 */ + uint32_t rsv_0x548[2]; /* 0x548 */ + uint32_t pwr_save_wakeup_en2; /* 0x550 */ + uint32_t pwr_save_wakeup_ctrl2; /* 0x554 */ + uint32_t rsv_0x558[2]; /* 0x558 */ + uint32_t intr1_ctrl_sts; /* 0x560 */ + uint32_t rsv_0x564[3]; /* 0x564 */ + uint32_t intr2_ctrl_sts; /* 0x570 */ + uint32_t rsv_0x574[7]; /* 0x574 ~ 0x58C */ + uint32_t otp_ctrl; /* 0x590 */ + uint32_t efuse; /* 0x594 */ + uint32_t rsv_0x598[6]; /* 0x598 */ + uint32_t chip_unique_id[8]; /* 0x5B0 */ + uint32_t rsv_0x5e0[8]; /* 0x5E0 ~ 0x5FC */ + uint32_t disgpio_in_pull_down0; /* 0x610 */ + uint32_t disgpio_in_pull_down1; /* 0x614 */ + uint32_t disgpio_in_pull_down2; /* 0x618 */ + uint32_t disgpio_in_pull_down3; /* 0x61C */ + uint32_t rsv_0x620[4]; /* 0x620 ~ 0x62C */ + uint32_t disgpio_in_pull_down4; /* 0x630 */ + uint32_t disgpio_in_pull_down5; /* 0x634 */ + uint32_t disgpio_in_pull_down6; /* 0x638 */ + uint32_t rsv_0x63c[5]; /* 0x63C ~ 0x64C */ + uint32_t sli_driving_strength; /* 0x650 */ + uint32_t rsv_0x654[107]; /* 0x654 ~ 0x7FC */ + uint32_t ca7_ctrl1; /* 0x800 */ + uint32_t ca7_ctrl2; /* 0x804 */ + uint32_t ca7_ctrl3; /* 0x808 */ + uint32_t ca7_ctrl4; /* 0x80C */ + uint32_t rsv_0x810[4]; /* 0x810 ~ 0x81C */ + uint32_t ca7_parity_chk; /* 0x820 */ + uint32_t ca7_parity_clr; /* 0x824 */ + uint32_t rsv_0x828[118]; /* 0x828 ~ 0x9FC */ + uint32_t cm3_ctrl; /* 0xA00 */ + uint32_t cm3_base; /* 0xA04 */ + uint32_t cm3_imem_addr; /* 0xA08 */ + uint32_t cm3_dmem_addr; /* 0xA0C */ + uint32_t rsv_0xa10[12]; /* 0xA10 ~ 0xA3C */ + uint32_t cm3_cache_area; /* 0xA40 */ + uint32_t cm3_cache_invd_ctrl; /* 0xA44 */ + uint32_t cm3_cache_func_ctrl; /* 0xA48 */ + uint32_t rsv_0xa4c[108]; /* 0xA4C ~ 0xBFC */ + uint32_t pci_cfg[3]; /* 0xC00 */ + uint32_t rsv_0xc0c[5]; /* 0xC0C ~ 0xC1C */ + uint32_t pcie_cfg; /* 0xC20 */ + uint32_t mmio_decode; /* 0xC24 */ + uint32_t reloc_ctrl_decode[2]; /* 0xC28 */ + uint32_t rsv_0xc30[4]; /* 0xC30 ~ 0xC3C */ + uint32_t mbox_decode; /* 0xC40 */ + uint32_t shared_sram_decode[2]; /* 0xC44 */ + uint32_t bmc_rev_id; /* 0xC4C */ + uint32_t rsv_0xc50[5]; /* 0xC50 ~ 0xC60 */ + uint32_t bmc_device_id; /* 0xC64 */ + uint32_t rsv_0xc68[102]; /* 0xC68 ~ 0xDFC */ + uint32_t vga_scratch1; /* 0xE00 */ + uint32_t vga_scratch2; /* 0xE04 */ + uint32_t vga_scratch3; /* 0xE08 */ + uint32_t vga_scratch4; /* 0xE0C */ + uint32_t rsv_0xe10[4]; /* 0xE10 ~ 0xE1C */ + uint32_t vga_scratch5; /* 0xE20 */ + uint32_t vga_scratch6; /* 0xE24 */ + uint32_t vga_scratch7; /* 0xE28 */ + uint32_t vga_scratch8; /* 0xE2C */ + uint32_t rsv_0xe30[52]; /* 0xE30 ~ 0xEFC */ + uint32_t wr_prot1; /* 0xF00 */ + uint32_t wr_prot2; /* 0xF04 */ + uint32_t wr_prot3; /* 0xF08 */ + uint32_t wr_prot4; /* 0xF0C */ + uint32_t wr_prot5; /* 0xF10 */ + uint32_t wr_prot6; /* 0xF18 */ + uint32_t wr_prot7; /* 0xF1C */ + uint32_t wr_prot8; /* 0xF20 */ + uint32_t wr_prot9; /* 0xF24 */ + uint32_t rsv_0xf28[2]; /* 0xF28 ~ 0xF2C */ + uint32_t wr_prot10; /* 0xF30 */ + uint32_t wr_prot11; /* 0xF34 */ + uint32_t wr_prot12; /* 0xF38 */ + uint32_t wr_prot13; /* 0xF3C */ + uint32_t wr_prot14; /* 0xF40 */ + uint32_t rsv_0xf44; /* 0xF44 */ + uint32_t wr_prot15; /* 0xF48 */ + uint32_t rsv_0xf4c[5]; /* 0xF4C ~ 0xF5C */ + uint32_t wr_prot16; /* 0xF60 */ +}; +#endif +#endif diff --git a/drivers/clk/aspeed/Makefile b/drivers/clk/aspeed/Makefile index 81764b4391..84776e5265 100644 --- a/drivers/clk/aspeed/Makefile +++ b/drivers/clk/aspeed/Makefile @@ -4,3 +4,4 @@ #

obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o +obj-$(CONFIG_ASPEED_AST2600) += clk_ast2600.o diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c new file mode 100644 index 0000000000..b29c5d0294 --- /dev/null +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -0,0 +1,1173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <asm/io.h> +#include <dm/lists.h> +#include <linux/delay.h> +#include <asm/arch/scu_ast2600.h> +#include <dt-bindings/clock/ast2600-clock.h> +#include <dt-bindings/reset/ast2600-reset.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CLKIN_25M 25000000UL + +/* MAC Clock Delay settings */ +#define MAC12_DEF_DELAY_1G 0x0041b75d +#define MAC12_DEF_DELAY_100M 0x00417410 +#define MAC12_DEF_DELAY_10M 0x00417410 +#define MAC34_DEF_DELAY_1G 0x0010438a +#define MAC34_DEF_DELAY_100M 0x00104208 +#define MAC34_DEF_DELAY_10M 0x00104208 + +/* + * 3-bit encode of CPU freqeucy + * Some code is duplicated + */ +enum ast2600_cpu_freq { + CPU_FREQ_1200M_1, + CPU_FREQ_1600M_1, + CPU_FREQ_1200M_2, + CPU_FREQ_1600M_2, + CPU_FREQ_800M_1, + CPU_FREQ_800M_2, + CPU_FREQ_800M_3, + CPU_FREQ_800M_4, +}; + +struct ast2600_clk_priv { + struct ast2600_scu *scu; +}; + +/* + * Clock divider/multiplier configuration struct. + * For H-PLL and M-PLL the formula is + * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) + * M - Numerator + * N - Denumerator + * P - Post Divider + * They have the same layout in their control register. + * + * D-PLL and D2-PLL have extra divider (OD + 1), which is not + * yet needed and ignored by clock configurations. + */ +union ast2600_pll_reg { + uint32_t w; + struct { + unsigned int m : 13; + unsigned int n : 6; + unsigned int p : 4; + unsigned int off : 1; + unsigned int bypass : 1; + unsigned int reset : 1; + unsigned int reserved : 6; + } b; +}; + +struct ast2600_pll_cfg { + union ast2600_pll_reg reg; + unsigned int ext_reg; +}; + +struct ast2600_pll_desc { + uint32_t in; + uint32_t out; + struct ast2600_pll_cfg cfg; +}; + +static const struct ast2600_pll_desc ast2600_pll_lookup[] = { + { + .in = CLKIN_25M, + .out = 400000000, + .cfg.reg.b.m = 95, + .cfg.reg.b.n = 2, + .cfg.reg.b.p = 1, + .cfg.ext_reg = 0x31, + }, + { + .in = CLKIN_25M, + .out = 200000000, + .cfg.reg.b.m = 127, + .cfg.reg.b.n = 0, + .cfg.reg.b.p = 15, + .cfg.ext_reg = 0x3f, + }, + { + .in = CLKIN_25M, + .out = 334000000, + .cfg.reg.b.m = 667, + .cfg.reg.b.n = 4, + .cfg.reg.b.p = 9, + .cfg.ext_reg = 0x14d, + }, + { + .in = CLKIN_25M, + .out = 1000000000, + .cfg.reg.b.m = 119, + .cfg.reg.b.n = 2, + .cfg.reg.b.p = 0, + .cfg.ext_reg = 0x3d, + }, + { + .in = CLKIN_25M, + .out = 50000000, + .cfg.reg.b.m = 95, + .cfg.reg.b.n = 2, + .cfg.reg.b.p = 15, + .cfg.ext_reg = 0x31, + }, +}; + +/* divisor tables */ +static uint32_t axi_ahb_div0_table[] = { + 3, 2, 3, 4, +}; + +static uint32_t axi_ahb_div1_table[] = { + 3, 4, 6, 8, +}; + +static uint32_t axi_ahb_default_table[] = { + 3, 4, 3, 4, 2, 2, 2, 2, +}; + +extern uint32_t ast2600_get_pll_rate(struct ast2600_scu *scu, int pll_idx) +{ + union ast2600_pll_reg pll_reg; + uint32_t hwstrap1; + uint32_t cpu_freq; + uint32_t mul = 1, div = 1; + + switch (pll_idx) { + case ASPEED_CLK_APLL: + pll_reg.w = readl(&scu->apll); + break; + case ASPEED_CLK_DPLL: + pll_reg.w = readl(&scu->dpll); + break; + case ASPEED_CLK_EPLL: + pll_reg.w = readl(&scu->epll); + break; + case ASPEED_CLK_HPLL: + pll_reg.w = readl(&scu->hpll); + break; + case ASPEED_CLK_MPLL: + pll_reg.w = readl(&scu->mpll); + break; + } + + if (!pll_reg.b.bypass) { + /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) + * HPLL Numerator (M) = fix 0x5F when SCU500[10]=1 + * Fixed 0xBF when SCU500[10]=0 and SCU500[8]=1 + * SCU200[12:0] (default 0x8F) when SCU510[10]=0 and SCU510[8]=0 + * HPLL Denumerator (N) = SCU200[18:13] (default 0x2) + * HPLL Divider (P) = SCU200[22:19] (default 0x0) + * HPLL Bandwidth Adj (NB) = fix 0x2F when SCU500[10]=1 + * Fixed 0x5F when SCU500[10]=0 and SCU500[8]=1 + * SCU204[11:0] (default 0x31) when SCU500[10]=0 and SCU500[8]=0 + */ + if (pll_idx == ASPEED_CLK_HPLL) { + hwstrap1 = readl(&scu->hwstrap1); + cpu_freq = (hwstrap1 & SCU_HWSTRAP1_CPU_FREQ_MASK) >> + SCU_HWSTRAP1_CPU_FREQ_SHIFT; + + switch (cpu_freq) { + case CPU_FREQ_800M_1: + case CPU_FREQ_800M_2: + case CPU_FREQ_800M_3: + case CPU_FREQ_800M_4: + pll_reg.b.m = 0x5f; + break; + case CPU_FREQ_1600M_1: + case CPU_FREQ_1600M_2: + pll_reg.b.m = 0xbf; + break; + default: + pll_reg.b.m = 0x8f; + break; + } + } + + mul = (pll_reg.b.m + 1) / (pll_reg.b.n + 1); + div = (pll_reg.b.p + 1); + } + + return ((CLKIN_25M * mul) / div); +} + +static uint32_t ast2600_get_hclk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); + uint32_t axi_div, ahb_div; + uint32_t hwstrap1 = readl(&scu->hwstrap1); + uint32_t cpu_freq = (hwstrap1 & SCU_HWSTRAP1_CPU_FREQ_MASK) >> + SCU_HWSTRAP1_CPU_FREQ_SHIFT; + uint32_t axi_ahb_ratio = (hwstrap1 & SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_MASK) >> + SCU_HWSTRAP1_AXI_AHB_CLK_RATIO_SHIFT; + + if (hwstrap1 & SCU_HWSTRAP1_CPU_AXI_CLK_RATIO) { + axi_ahb_div1_table[0] = axi_ahb_default_table[cpu_freq] * 2; + axi_div = 1; + ahb_div = axi_ahb_div1_table[axi_ahb_ratio]; + } else { + axi_ahb_div0_table[0] = axi_ahb_default_table[cpu_freq]; + axi_div = 2; + ahb_div = axi_ahb_div0_table[axi_ahb_ratio]; + } + + return (rate / axi_div / ahb_div); +} + +static uint32_t ast2600_get_bclk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); + uint32_t clksrc1 = readl(&scu->clksrc1); + uint32_t bclk_div = (clksrc1 & SCU_CLKSRC1_BCLK_DIV_MASK) >> + SCU_CLKSRC1_BCLK_DIV_SHIFT; + + return (rate / ((bclk_div + 1) * 4)); +} + +static uint32_t ast2600_get_pclk1_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); + uint32_t clksrc1 = readl(&scu->clksrc1); + uint32_t pclk_div = (clksrc1 & SCU_CLKSRC1_PCLK_DIV_MASK) >> + SCU_CLKSRC1_PCLK_DIV_SHIFT; + + return (rate / ((pclk_div + 1) * 4)); +} + +static uint32_t ast2600_get_pclk2_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_hclk_rate(scu); + uint32_t clksrc4 = readl(&scu->clksrc4); + uint32_t pclk_div = (clksrc4 & SCU_CLKSRC4_PCLK_DIV_MASK) >> + SCU_CLKSRC4_PCLK_DIV_SHIFT; + + return (rate / ((pclk_div + 1) * 2)); +} + +static uint32_t ast2600_get_uxclk_in_rate(struct ast2600_scu *scu) +{ + uint32_t rate = 0; + uint32_t clksrc5 = readl(&scu->clksrc5); + uint32_t uxclk = (clksrc5 & SCU_CLKSRC5_UXCLK_MASK) >> + SCU_CLKSRC5_UXCLK_SHIFT; + + switch (uxclk) { + case 0: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 4; + break; + case 1: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 2; + break; + case 2: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL); + break; + case 3: + rate = ast2600_get_hclk_rate(scu); + break; + } + + return rate; +} + +static uint32_t ast2600_get_huxclk_in_rate(struct ast2600_scu *scu) +{ + uint32_t rate = 0; + uint32_t clksrc5 = readl(&scu->clksrc5); + uint32_t huxclk = (clksrc5 & SCU_CLKSRC5_HUXCLK_MASK) >> + SCU_CLKSRC5_HUXCLK_SHIFT; + + switch (huxclk) { + case 0: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 4; + break; + case 1: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL) / 2; + break; + case 2: + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL); + break; + case 3: + rate = ast2600_get_hclk_rate(scu); + break; + } + + return rate; +} + +static uint32_t ast2600_get_uart_uxclk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_uxclk_in_rate(scu); + uint32_t uart_clkgen = readl(&scu->uart_clkgen); + uint32_t n = (uart_clkgen & SCU_UART_CLKGEN_N_MASK) >> + SCU_UART_CLKGEN_N_SHIFT; + uint32_t r = (uart_clkgen & SCU_UART_CLKGEN_R_MASK) >> + SCU_UART_CLKGEN_R_SHIFT; + + return ((rate * r) / (n * 2)); +} + +static uint32_t ast2600_get_uart_huxclk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_huxclk_in_rate(scu); + uint32_t huart_clkgen = readl(&scu->huart_clkgen); + uint32_t n = (huart_clkgen & SCU_HUART_CLKGEN_N_MASK) >> + SCU_HUART_CLKGEN_N_SHIFT; + uint32_t r = (huart_clkgen & SCU_HUART_CLKGEN_R_MASK) >> + SCU_HUART_CLKGEN_R_SHIFT; + + return ((rate * r) / (n * 2)); +} + +static uint32_t ast2600_get_sdio_clk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = 0; + uint32_t clksrc4 = readl(&scu->clksrc4); + uint32_t sdio_div = (clksrc4 & SCU_CLKSRC4_SDIO_DIV_MASK) >> + SCU_CLKSRC4_SDIO_DIV_SHIFT; + + if (clksrc4 & SCU_CLKSRC4_SDIO) + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL); + else + rate = ast2600_get_hclk_rate(scu); + + return (rate / ((sdio_div + 1) * 2)); +} + +static uint32_t ast2600_get_emmc_clk_rate(struct ast2600_scu *scu) +{ + uint32_t rate = ast2600_get_pll_rate(scu, ASPEED_CLK_HPLL); + uint32_t clksrc1 = readl(&scu->clksrc1); + uint32_t emmc_div = (clksrc1 & SCU_CLKSRC1_EMMC_DIV_MASK) >> + SCU_CLKSRC1_EMMC_DIV_SHIFT; + + return (rate / ((emmc_div + 1) * 4)); +} + +static uint32_t ast2600_get_uart_clk_rate(struct ast2600_scu *scu, int uart_idx) +{ + uint32_t rate = 0; + uint32_t uart5_clk = 0; + uint32_t clksrc2 = readl(&scu->clksrc2); + uint32_t clksrc4 = readl(&scu->clksrc4); + uint32_t clksrc5 = readl(&scu->clksrc5); + uint32_t misc_ctrl1 = readl(&scu->misc_ctrl1); + + switch (uart_idx) { + case 1: + case 2: + case 3: + case 4: + case 6: + if (clksrc4 & BIT(uart_idx - 1)) + rate = ast2600_get_uart_huxclk_rate(scu); + else + rate = ast2600_get_uart_uxclk_rate(scu); + break; + case 5: + /* + * SCU0C[12] and SCU304[14] together decide + * the UART5 clock generation + */ + if (misc_ctrl1 & SCU_MISC_CTRL1_UART5_DIV) + uart5_clk = 0x1 << 1; + + if (clksrc2 & SCU_CLKSRC2_UART5) + uart5_clk |= 0x1; + + switch (uart5_clk) { + case 0: + rate = 24000000; + break; + case 1: + rate = 192000000; + break; + case 2: + rate = 24000000 / 13; + break; + case 3: + rate = 192000000 / 13; + break; + } + + break; + case 7: + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + if (clksrc5 & BIT(uart_idx - 1)) + rate = ast2600_get_uart_huxclk_rate(scu); + else + rate = ast2600_get_uart_uxclk_rate(scu); + break; + } + + return rate; +} + +static ulong ast2600_clk_get_rate(struct clk *clk) +{ + struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + switch (clk->id) { + case ASPEED_CLK_HPLL: + case ASPEED_CLK_EPLL: + case ASPEED_CLK_DPLL: + case ASPEED_CLK_MPLL: + case ASPEED_CLK_APLL: + rate = ast2600_get_pll_rate(priv->scu, clk->id); + break; + case ASPEED_CLK_AHB: + rate = ast2600_get_hclk_rate(priv->scu); + break; + case ASPEED_CLK_APB1: + rate = ast2600_get_pclk1_rate(priv->scu); + break; + case ASPEED_CLK_APB2: + rate = ast2600_get_pclk2_rate(priv->scu); + break; + case ASPEED_CLK_GATE_UART1CLK: + rate = ast2600_get_uart_clk_rate(priv->scu, 1); + break; + case ASPEED_CLK_GATE_UART2CLK: + rate = ast2600_get_uart_clk_rate(priv->scu, 2); + break; + case ASPEED_CLK_GATE_UART3CLK: + rate = ast2600_get_uart_clk_rate(priv->scu, 3); + break; + case ASPEED_CLK_GATE_UART4CLK: + rate = ast2600_get_uart_clk_rate(priv->scu, 4); + break; + case ASPEED_CLK_GATE_UART5CLK: + rate = ast2600_get_uart_clk_rate(priv->scu, 5); + break; + case ASPEED_CLK_BCLK: + rate = ast2600_get_bclk_rate(priv->scu); + break; + case ASPEED_CLK_SDIO: + rate = ast2600_get_sdio_clk_rate(priv->scu); + break; + case ASPEED_CLK_EMMC: + rate = ast2600_get_emmc_clk_rate(priv->scu); + break; + case ASPEED_CLK_UARTX: + rate = ast2600_get_uart_uxclk_rate(priv->scu); + break; + case ASPEED_CLK_HUARTX: + rate = ast2600_get_uart_huxclk_rate(priv->scu); + break; + default: + debug("can't get clk rate\n"); + return -ENOENT; + } + + return rate; +} + +/** + * @brief lookup PLL divider config by input/output rate + * @param[in] *pll - PLL descriptor + * @return true - if PLL divider config is found, false - else + * The function caller shall fill "pll->in" and "pll->out", + * then this function will search the lookup table + * to find a valid PLL divider configuration. + */ +static bool ast2600_search_clock_config(struct ast2600_pll_desc *pll) +{ + uint32_t i; + const struct ast2600_pll_desc *def_desc; + bool is_found = false; + + for (i = 0; i < ARRAY_SIZE(ast2600_pll_lookup); i++) { + def_desc = &ast2600_pll_lookup[i]; + + if (def_desc->in == pll->in && def_desc->out == pll->out) { + is_found = true; + pll->cfg.reg.w = def_desc->cfg.reg.w; + pll->cfg.ext_reg = def_desc->cfg.ext_reg; + break; + } + } + return is_found; +} + +static uint32_t ast2600_configure_pll(struct ast2600_scu *scu, + struct ast2600_pll_cfg *p_cfg, int pll_idx) +{ + uint32_t addr, addr_ext; + uint32_t reg; + + switch (pll_idx) { + case ASPEED_CLK_HPLL: + addr = (uint32_t)(&scu->hpll); + addr_ext = (uint32_t)(&scu->hpll_ext); + break; + case ASPEED_CLK_MPLL: + addr = (uint32_t)(&scu->mpll); + addr_ext = (uint32_t)(&scu->mpll_ext); + break; + case ASPEED_CLK_DPLL: + addr = (uint32_t)(&scu->dpll); + addr_ext = (uint32_t)(&scu->dpll_ext); + break; + case ASPEED_CLK_EPLL: + addr = (uint32_t)(&scu->epll); + addr_ext = (uint32_t)(&scu->epll_ext); + break; + case ASPEED_CLK_APLL: + addr = (uint32_t)(&scu->apll); + addr_ext = (uint32_t)(&scu->apll_ext); + break; + default: + debug("unknown PLL index\n"); + return 1; + } + + p_cfg->reg.b.bypass = 0; + p_cfg->reg.b.off = 1; + p_cfg->reg.b.reset = 1; + + reg = readl(addr); + reg &= ~GENMASK(25, 0); + reg |= p_cfg->reg.w; + writel(reg, addr); + + /* write extend parameter */ + writel(p_cfg->ext_reg, addr_ext); + udelay(100); + p_cfg->reg.b.off = 0; + p_cfg->reg.b.reset = 0; + reg &= ~GENMASK(25, 0); + reg |= p_cfg->reg.w; + writel(reg, addr); + while (!(readl(addr_ext) & BIT(31))) + ; + + return 0; +} + +static uint32_t ast2600_configure_ddr(struct ast2600_scu *scu, ulong rate) +{ + struct ast2600_pll_desc mpll; + + mpll.in = CLKIN_25M; + mpll.out = rate; + if (ast2600_search_clock_config(&mpll) == false) { + printf("error!! unable to find valid DDR clock setting\n"); + return 0; + } + ast2600_configure_pll(scu, &mpll.cfg, ASPEED_CLK_MPLL); + + return ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); +} + +static ulong ast2600_clk_set_rate(struct clk *clk, ulong rate) +{ + struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate; + + switch (clk->id) { + case ASPEED_CLK_MPLL: + new_rate = ast2600_configure_ddr(priv->scu, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static uint32_t ast2600_configure_mac12_clk(struct ast2600_scu *scu) +{ + /* scu340[25:0]: 1G default delay */ + clrsetbits_le32(&scu->mac12_clk_delay, GENMASK(25, 0), + MAC12_DEF_DELAY_1G); + + /* set 100M/10M default delay */ + writel(MAC12_DEF_DELAY_100M, &scu->mac12_clk_delay_100M); + writel(MAC12_DEF_DELAY_10M, &scu->mac12_clk_delay_10M); + + /* MAC AHB = HPLL / 6 */ + clrsetbits_le32(&scu->clksrc1, SCU_CLKSRC1_MAC_DIV_MASK, + (0x2 << SCU_CLKSRC1_MAC_DIV_SHIFT)); + + return 0; +} + +static uint32_t ast2600_configure_mac34_clk(struct ast2600_scu *scu) +{ + /* + * scu350[31] RGMII 125M source: 0 = from IO pin + * scu350[25:0] MAC 1G delay + */ + clrsetbits_le32(&scu->mac34_clk_delay, (BIT(31) | GENMASK(25, 0)), + MAC34_DEF_DELAY_1G); + writel(MAC34_DEF_DELAY_100M, &scu->mac34_clk_delay_100M); + writel(MAC34_DEF_DELAY_10M, &scu->mac34_clk_delay_10M); + + /* + * clock source seletion and divider + * scu310[26:24] : MAC AHB bus clock = HCLK / 2 + * scu310[18:16] : RMII 50M = HCLK_200M / 4 + */ + clrsetbits_le32(&scu->clksrc4, + (SCU_CLKSRC4_MAC_DIV_MASK | SCU_CLKSRC4_RMII34_DIV_MASK), + ((0x0 << SCU_CLKSRC4_MAC_DIV_SHIFT) + | (0x3 << SCU_CLKSRC4_RMII34_DIV_SHIFT))); + + /* + * set driving strength + * scu458[3:2] : MAC4 driving strength + * scu458[1:0] : MAC3 driving strength + */ + clrsetbits_le32(&scu->pinmux16, + SCU_PINCTRL16_MAC4_DRIVING_MASK | SCU_PINCTRL16_MAC3_DRIVING_MASK, + (0x3 << SCU_PINCTRL16_MAC4_DRIVING_SHIFT) + | (0x3 << SCU_PINCTRL16_MAC3_DRIVING_SHIFT)); + + return 0; +} + +/** + * ast2600 RGMII clock source tree + * 125M from external PAD -------->|\ + * HPLL -->|\ | |---->RGMII 125M for MAC#1 & MAC#2 + * | |---->| divider |---->|/ + + * EPLL -->|/ | + * | + * +---------<-----------|RGMIICK PAD output enable|<-------------+ + * | + * +--------------------------->|\ + * | |----> RGMII 125M for MAC#3 & MAC#4 + * HCLK 200M ---->|divider|---->|/ + * To simplify the control flow: + * 1. RGMII 1/2 always use EPLL as the internal clock source + * 2. RGMII 3/4 always use RGMIICK pad as the RGMII 125M source + * 125M from external PAD -------->|\ + * | |---->RGMII 125M for MAC#1 & MAC#2 + * EPLL---->| divider |--->|/ + + * | + * +<--------------------|RGMIICK PAD output enable|<-------------+ + * | + * +--------------------------->RGMII 125M for MAC#3 & MAC#4 + */ +#define RGMIICK_SRC_PAD 0 +#define RGMIICK_SRC_EPLL 1 /* recommended */ +#define RGMIICK_SRC_HPLL 2 + +#define RGMIICK_DIV2 1 +#define RGMIICK_DIV3 2 +#define RGMIICK_DIV4 3 +#define RGMIICK_DIV5 4 +#define RGMIICK_DIV6 5 +#define RGMIICK_DIV7 6 +#define RGMIICK_DIV8 7 /* recommended */ + +#define RMIICK_DIV4 0 +#define RMIICK_DIV8 1 +#define RMIICK_DIV12 2 +#define RMIICK_DIV16 3 +#define RMIICK_DIV20 4 /* recommended */ +#define RMIICK_DIV24 5 +#define RMIICK_DIV28 6 +#define RMIICK_DIV32 7 + +struct ast2600_mac_clk_div { + uint32_t src; /* 0=external PAD, 1=internal PLL */ + uint32_t fin; /* divider input speed */ + uint32_t n; /* 0=div2, 1=div2, 2=div3, 3=div4,...,7=div8 */ + uint32_t fout; /* fout = fin / n */ +}; + +struct ast2600_mac_clk_div rgmii_clk_defconfig = { + .src = ASPEED_CLK_EPLL, + .fin = 1000000000, + .n = RGMIICK_DIV8, + .fout = 125000000, +}; + +struct ast2600_mac_clk_div rmii_clk_defconfig = { + .src = ASPEED_CLK_EPLL, + .fin = 1000000000, + .n = RMIICK_DIV20, + .fout = 50000000, +}; + +static void ast2600_init_mac_pll(struct ast2600_scu *p_scu, + struct ast2600_mac_clk_div *p_cfg) +{ + struct ast2600_pll_desc pll; + + pll.in = CLKIN_25M; + pll.out = p_cfg->fin; + if (ast2600_search_clock_config(&pll) == false) { + pr_err("unable to find valid ETHNET MAC clock setting\n"); + return; + } + ast2600_configure_pll(p_scu, &pll.cfg, p_cfg->src); +} + +static void ast2600_init_rgmii_clk(struct ast2600_scu *p_scu, + struct ast2600_mac_clk_div *p_cfg) +{ + uint32_t reg_304 = readl(&p_scu->clksrc2); + uint32_t reg_340 = readl(&p_scu->mac12_clk_delay); + uint32_t reg_350 = readl(&p_scu->mac34_clk_delay); + + reg_340 &= ~GENMASK(31, 29); + /* scu340[28]: RGMIICK PAD output enable (to MAC 3/4) */ + reg_340 |= BIT(28); + if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { + /* + * re-init PLL if the current PLL output frequency doesn't match + * the divider setting + */ + if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) + ast2600_init_mac_pll(p_scu, p_cfg); + /* scu340[31]: select RGMII 125M from internal source */ + reg_340 |= BIT(31); + } + + reg_304 &= ~GENMASK(23, 20); + + /* set clock divider */ + reg_304 |= (p_cfg->n & 0x7) << 20; + + /* select internal clock source */ + if (p_cfg->src == ASPEED_CLK_HPLL) + reg_304 |= BIT(23); + + /* RGMII 3/4 clock source select */ + reg_350 &= ~BIT(31); + + writel(reg_304, &p_scu->clksrc2); + writel(reg_340, &p_scu->mac12_clk_delay); + writel(reg_350, &p_scu->mac34_clk_delay); +} + +/** + * ast2600 RMII/NCSI clock source tree + * HPLL -->|\ + * | |---->| divider |----> RMII 50M for MAC#1 & MAC#2 + * EPLL -->|/ + * HCLK(SCLICLK)---->| divider |----> RMII 50M for MAC#3 & MAC#4 + */ +static void ast2600_init_rmii_clk(struct ast2600_scu *p_scu, + struct ast2600_mac_clk_div *p_cfg) +{ + uint32_t clksrc2 = readl(&p_scu->clksrc2); + uint32_t clksrc4 = readl(&p_scu->clksrc4); + + if (p_cfg->src == ASPEED_CLK_EPLL || p_cfg->src == ASPEED_CLK_HPLL) { + /* + * re-init PLL if the current PLL output frequency doesn't match + * the divider setting + */ + if (p_cfg->fin != ast2600_get_pll_rate(p_scu, p_cfg->src)) + ast2600_init_mac_pll(p_scu, p_cfg); + } + + clksrc2 &= ~(SCU_CLKSRC2_RMII12 | SCU_CLKSRC2_RMII12_DIV_MASK); + + /* set RMII 1/2 clock divider */ + clksrc2 |= (p_cfg->n & 0x7) << 16; + + /* RMII clock source selection */ + if (p_cfg->src == ASPEED_CLK_HPLL) + clksrc2 |= SCU_CLKSRC2_RMII12; + + /* set RMII 3/4 clock divider */ + clksrc4 &= ~SCU_CLKSRC4_RMII34_DIV_MASK; + clksrc4 |= (0x3 << SCU_CLKSRC4_RMII34_DIV_SHIFT); + + writel(clksrc2, &p_scu->clksrc2); + writel(clksrc4, &p_scu->clksrc4); +} + +static uint32_t ast2600_configure_mac(struct ast2600_scu *scu, int index) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + switch (index) { + case 1: + reset_bit = BIT(ASPEED_RESET_MAC1); + clkgate_bit = SCU_CLKGATE1_MAC1; + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr1); + mdelay(10); + writel(reset_bit, &scu->modrst_clr1); + break; + case 2: + reset_bit = BIT(ASPEED_RESET_MAC2); + clkgate_bit = SCU_CLKGATE1_MAC2; + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr1); + mdelay(10); + writel(reset_bit, &scu->modrst_clr1); + break; + case 3: + reset_bit = BIT(ASPEED_RESET_MAC3 - 32); + clkgate_bit = SCU_CLKGATE2_MAC3; + writel(reset_bit, &scu->modrst_ctrl2); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr2); + mdelay(10); + writel(reset_bit, &scu->modrst_clr2); + break; + case 4: + reset_bit = BIT(ASPEED_RESET_MAC4 - 32); + clkgate_bit = SCU_CLKGATE2_MAC4; + writel(reset_bit, &scu->modrst_ctrl2); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr2); + mdelay(10); + writel(reset_bit, &scu->modrst_clr2); + break; + default: + return -EINVAL; + } + + return 0; +} + +static void ast2600_configure_rsa_ecc_clk(struct ast2600_scu *scu) +{ + uint32_t clksrc1 = readl(&scu->clksrc1); + + /* Configure RSA clock = HPLL/3 */ + clksrc1 |= SCU_CLKSRC1_ECC_RSA; + clksrc1 &= ~SCU_CLKSRC1_ECC_RSA_DIV_MASK; + clksrc1 |= (2 << SCU_CLKSRC1_ECC_RSA_DIV_SHIFT); + + writel(clksrc1, &scu->clksrc1); +} + +static ulong ast2600_enable_sdclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_SD - 32); + clkgate_bit = SCU_CLKGATE2_SDIO; + + writel(reset_bit, &scu->modrst_ctrl2); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr2); + mdelay(10); + writel(reset_bit, &scu->modrst_clr2); + + return 0; +} + +static ulong ast2600_enable_extsdclk(struct ast2600_scu *scu) +{ + int i = 0; + uint32_t div = 0; + uint32_t rate = 0; + uint32_t clksrc4 = readl(&scu->clksrc4); + + /* + * ast2600 SD controller max clk is 200Mhz + * use apll for clock source 800/4 = 200 + * controller max is 200mhz + */ + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_APLL); + for (i = 0; i < 8; i++) { + div = (i + 1) * 2; + if ((rate / div) <= 200000000) + break; + } + clksrc4 &= ~SCU_CLKSRC4_SDIO_DIV_MASK; + clksrc4 |= (i << SCU_CLKSRC4_SDIO_DIV_SHIFT); + clksrc4 |= SCU_CLKSRC4_SDIO; + writel(clksrc4, &scu->clksrc4); + + setbits_le32(&scu->clksrc4, SCU_CLKSRC4_SDIO_EN); + + return 0; +} + +static ulong ast2600_enable_emmcclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_EMMC); + clkgate_bit = SCU_CLKGATE1_EMMC; + + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr1); + mdelay(10); + writel(reset_bit, &scu->modrst_clr1); + + return 0; +} + +static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) +{ + int i = 0; + uint32_t div = 0; + uint32_t rate = 0; + uint32_t clksrc1 = readl(&scu->clksrc1); + + /* + * ast2600 eMMC controller max clk is 200Mhz + * HPll->1/2->|\ + * |->SCU300[11]->SCU300[14:12][1/N] + + * MPLL------>|/ | + * +----------------------------------------------+ + * | + * +---------> EMMC12C[15:8][1/N]-> eMMC clk + */ + rate = ast2600_get_pll_rate(scu, ASPEED_CLK_MPLL); + for (i = 0; i < 8; i++) { + div = (i + 1) * 2; + if ((rate / div) <= 200000000) + break; + } + + clksrc1 &= ~SCU_CLKSRC1_EMMC_DIV_MASK; + clksrc1 |= (i << SCU_CLKSRC1_EMMC_DIV_SHIFT); + clksrc1 |= SCU_CLKSRC1_EMMC; + writel(clksrc1, &scu->clksrc1); + + setbits_le32(&scu->clksrc1, SCU_CLKSRC1_EMMC_EN); + + return 0; +} + +static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_FSI % 32); + clkgate_bit = SCU_CLKGATE2_FSI; + + /* The FSI clock is shared between masters. If it's already on + * don't touch it, as that will reset the existing master. + */ + if (!(readl(&scu->clkgate_ctrl2) & clkgate_bit)) { + debug("%s: already running, not touching it\n", __func__); + return 0; + } + + writel(reset_bit, &scu->modrst_ctrl2); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr2); + mdelay(10); + writel(reset_bit, &scu->modrst_clr2); + + return 0; +} + +static ulong ast2600_enable_usbahclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_EHCI_P1); + clkgate_bit = SCU_CLKGATE1_USB_HUB; + + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_ctrl1); + mdelay(20); + writel(reset_bit, &scu->modrst_clr1); + + return 0; +} + +static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) +{ + uint32_t reset_bit; + uint32_t clkgate_bit; + + reset_bit = BIT(ASPEED_RESET_EHCI_P2); + clkgate_bit = SCU_CLKGATE1_USB_HOST2; + + writel(reset_bit, &scu->modrst_ctrl1); + udelay(100); + writel(clkgate_bit, &scu->clkgate_clr1); + mdelay(20); + writel(reset_bit, &scu->modrst_clr1); + + return 0; +} + +static int ast2600_clk_enable(struct clk *clk) +{ + struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case ASPEED_CLK_GATE_MAC1CLK: + ast2600_configure_mac(priv->scu, 1); + break; + case ASPEED_CLK_GATE_MAC2CLK: + ast2600_configure_mac(priv->scu, 2); + break; + case ASPEED_CLK_GATE_MAC3CLK: + ast2600_configure_mac(priv->scu, 3); + break; + case ASPEED_CLK_GATE_MAC4CLK: + ast2600_configure_mac(priv->scu, 4); + break; + case ASPEED_CLK_GATE_SDCLK: + ast2600_enable_sdclk(priv->scu); + break; + case ASPEED_CLK_GATE_SDEXTCLK: + ast2600_enable_extsdclk(priv->scu); + break; + case ASPEED_CLK_GATE_EMMCCLK: + ast2600_enable_emmcclk(priv->scu); + break; + case ASPEED_CLK_GATE_EMMCEXTCLK: + ast2600_enable_extemmcclk(priv->scu); + break; + case ASPEED_CLK_GATE_FSICLK: + ast2600_enable_fsiclk(priv->scu); + break; + case ASPEED_CLK_GATE_USBPORT1CLK: + ast2600_enable_usbahclk(priv->scu); + break; + case ASPEED_CLK_GATE_USBPORT2CLK: + ast2600_enable_usbbhclk(priv->scu); + break; + default: + pr_err("can't enable clk\n"); + return -ENOENT; + } + + return 0; +} + +struct clk_ops ast2600_clk_ops = { + .get_rate = ast2600_clk_get_rate, + .set_rate = ast2600_clk_set_rate, + .enable = ast2600_clk_enable, +}; + +static int ast2600_clk_probe(struct udevice *dev) +{ + struct ast2600_clk_priv *priv = dev_get_priv(dev); + + priv->scu = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->scu)) + return PTR_ERR(priv->scu); + + ast2600_init_rgmii_clk(priv->scu, &rgmii_clk_defconfig); + ast2600_init_rmii_clk(priv->scu, &rmii_clk_defconfig); + ast2600_configure_mac12_clk(priv->scu); + ast2600_configure_mac34_clk(priv->scu); + ast2600_configure_rsa_ecc_clk(priv->scu); + + return 0; +} + +static int ast2600_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); + if (ret) + debug("Warning: No reset driver: ret=%d\n", ret); + + return 0; +} + +struct aspeed_clks { + ulong id; + const char *name; +}; + +static struct aspeed_clks aspeed_clk_names[] = { + { ASPEED_CLK_HPLL, "hpll" }, + { ASPEED_CLK_MPLL, "mpll" }, + { ASPEED_CLK_APLL, "apll" }, + { ASPEED_CLK_EPLL, "epll" }, + { ASPEED_CLK_DPLL, "dpll" }, + { ASPEED_CLK_AHB, "hclk" }, + { ASPEED_CLK_APB1, "pclk1" }, + { ASPEED_CLK_APB2, "pclk2" }, + { ASPEED_CLK_BCLK, "bclk" }, + { ASPEED_CLK_UARTX, "uxclk" }, + { ASPEED_CLK_HUARTX, "huxclk" }, +}; + +int soc_clk_dump(void) +{ + struct udevice *dev; + struct clk clk; + unsigned long rate; + int i, ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, DM_GET_DRIVER(aspeed_scu), + &dev); + if (ret) + return ret; + + printf("Clk\t\tHz\n"); + + for (i = 0; i < ARRAY_SIZE(aspeed_clk_names); i++) { + clk.id = aspeed_clk_names[i].id; + ret = clk_request(dev, &clk); + if (ret < 0) { + debug("%s clk_request() failed: %d\n", __func__, ret); + continue; + } + + ret = clk_get_rate(&clk); + rate = ret; + + clk_free(&clk); + + if (ret == -ENOTSUPP) { + printf("clk ID %lu not supported yet\n", + aspeed_clk_names[i].id); + continue; + } + if (ret < 0) { + printf("%s %lu: get_rate err: %d\n", __func__, + aspeed_clk_names[i].id, ret); + continue; + } + + printf("%s(%3lu):\t%lu\n", aspeed_clk_names[i].name, + aspeed_clk_names[i].id, rate); + } + + return 0; +} + +static const struct udevice_id ast2600_clk_ids[] = { + { .compatible = "aspeed,ast2600-scu", }, + { }, +}; + +U_BOOT_DRIVER(aspeed_ast2600_scu) = { + .name = "aspeed_ast2600_scu", + .id = UCLASS_CLK, + .of_match = ast2600_clk_ids, + .priv_auto_alloc_size = sizeof(struct ast2600_clk_priv), + .ops = &ast2600_clk_ops, + .bind = ast2600_clk_bind, + .probe = ast2600_clk_probe, +}; diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h new file mode 100644 index 0000000000..36294a5140 --- /dev/null +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_LCLK 6 +#define ASPEED_CLK_GATE_YCLK 7 +#define ASPEED_CLK_GATE_LHCCLK 8 +#define ASPEED_CLK_GATE_REFCLK 9 +#define ASPEED_CLK_GATE_ESPICLK 10 +#define ASPEED_CLK_GATE_UART1CLK 11 +#define ASPEED_CLK_GATE_UART2CLK 12 +#define ASPEED_CLK_GATE_UART3CLK 13 +#define ASPEED_CLK_GATE_UART4CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_UART6CLK 16 +#define ASPEED_CLK_GATE_UART7CLK 17 +#define ASPEED_CLK_GATE_UART8CLK 18 +#define ASPEED_CLK_GATE_UART9CLK 19 +#define ASPEED_CLK_GATE_UART10CLK 20 +#define ASPEED_CLK_GATE_UART11CLK 21 +#define ASPEED_CLK_GATE_UART12CLK 22 +#define ASPEED_CLK_GATE_UART13CLK 23 +#define ASPEED_CLK_GATE_MAC1CLK 24 +#define ASPEED_CLK_GATE_MAC2CLK 25 +#define ASPEED_CLK_GATE_MAC3CLK 26 +#define ASPEED_CLK_GATE_MAC4CLK 27 +#define ASPEED_CLK_GATE_RSACLK 28 +#define ASPEED_CLK_GATE_SDCLK 29 +#define ASPEED_CLK_GATE_SDEXTCLK 30 +#define ASPEED_CLK_GATE_EMMCCLK 31 +#define ASPEED_CLK_GATE_EMMCEXTCLK 32 +#define ASPEED_CLK_GATE_USBUHCICLK 33 +#define ASPEED_CLK_GATE_USBPORT1CLK 34 +#define ASPEED_CLK_GATE_USBPORT2CLK 35 +#define ASPEED_CLK_GATE_FSICLK 36 + +#define ASPEED_CLK_APLL 37 +#define ASPEED_CLK_EPLL 38 +#define ASPEED_CLK_DPLL 39 +#define ASPEED_CLK_HPLL 40 +#define ASPEED_CLK_AHB 41 +#define ASPEED_CLK_APB1 42 +#define ASPEED_CLK_APB2 43 +#define ASPEED_CLK_UART 44 +#define ASPEED_CLK_SDIO 45 +#define ASPEED_CLK_ECLK 46 +#define ASPEED_CLK_ECLK_MUX 47 +#define ASPEED_CLK_LHCLK 48 +#define ASPEED_CLK_MAC 49 +#define ASPEED_CLK_BCLK 50 +#define ASPEED_CLK_MPLL 51 +#define ASPEED_CLK_24M 52 +#define ASPEED_CLK_EMMC 53 +#define ASPEED_CLK_UARTX 54 +#define ASPEED_CLK_HUARTX 55

From: Dylan Hung dylan_hung@aspeedtech.com

AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600. The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb), 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported.

Signed-off-by: Dylan Hung dylan_hung@aspeedtech.com Signed-off-by: Chia-Wei, Wang chiawei_wang@aspeedtech.com --- .../include/asm/arch-aspeed/sdram_ast2600.h | 163 +++ drivers/ram/aspeed/Kconfig | 61 +- drivers/ram/aspeed/Makefile | 3 +- drivers/ram/aspeed/sdram_ast2600.c | 1061 +++++++++++++++++ 4 files changed, 1286 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/arch-aspeed/sdram_ast2600.h create mode 100644 drivers/ram/aspeed/sdram_ast2600.c

diff --git a/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h new file mode 100644 index 0000000000..d2408c0020 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/sdram_ast2600.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef _ASM_ARCH_SDRAM_AST2600_H +#define _ASM_ARCH_SDRAM_AST2600_H + +/* keys for unlocking HW */ +#define SDRAM_UNLOCK_KEY 0xFC600309 +#define SDRAM_VIDEO_UNLOCK_KEY 0x00440003 + +/* Fixed priority DRAM Requests mask */ +#define REQ_PRI_VGA_HW_CURSOR_R 0 +#define REQ_PRI_VGA_CRT_R 1 +#define REQ_PRI_SOC_DISPLAY_CTRL_R 2 +#define REQ_PRI_PCIE_BUS1_RW 3 +#define REQ_PRI_VIDEO_HIGH_PRI_W 4 +#define REQ_PRI_CPU_RW 5 +#define REQ_PRI_SLI_RW 6 +#define REQ_PRI_PCIE_BUS2_RW 7 +#define REQ_PRI_USB2_0_HUB_EHCI1_DMA_RW 8 +#define REQ_PRI_USB2_0_DEV_EHCI2_DMA_RW 9 +#define REQ_PRI_USB1_1_UHCI_HOST_RW 10 +#define REQ_PRI_AHB_BUS_RW 11 +#define REQ_PRI_CM3_DATA_RW 12 +#define REQ_PRI_CM3_INST_R 13 +#define REQ_PRI_MAC0_DMA_RW 14 +#define REQ_PRI_MAC1_DMA_RW 15 +#define REQ_PRI_SDIO_DMA_RW 16 +#define REQ_PRI_PILOT_ENGINE_RW 17 +#define REQ_PRI_XDMA1_RW 18 +#define REQ_PRI_MCTP1_RW 19 +#define REQ_PRI_VIDEO_FLAG_RW 20 +#define REQ_PRI_VIDEO_LOW_PRI_W 21 +#define REQ_PRI_2D_ENGINE_DATA_RW 22 +#define REQ_PRI_ENC_ENGINE_RW 23 +#define REQ_PRI_MCTP2_RW 24 +#define REQ_PRI_XDMA2_RW 25 +#define REQ_PRI_ECC_RSA_RW 26 + +#define MCR30_RESET_DLL_DELAY_EN BIT(4) +#define MCR30_MODE_REG_SEL_SHIFT 1 +#define MCR30_MODE_REG_SEL_MASK GENMASK(3, 1) +#define MCR30_SET_MODE_REG BIT(0) + +#define MCR30_SET_MR(mr) ((mr << MCR30_MODE_REG_SEL_SHIFT) | MCR30_SET_MODE_REG) + +#define MCR34_SELF_REFRESH_STATUS_MASK GENMASK(30, 28) + +#define MCR34_ODT_DELAY_SHIFT 12 +#define MCR34_ODT_DELAY_MASK GENMASK(15, 12) +#define MCR34_ODT_EXT_SHIFT 10 +#define MCR34_ODT_EXT_MASK GENMASK(11, 10) +#define MCR34_ODT_AUTO_ON BIT(9) +#define MCR34_ODT_EN BIT(8) +#define MCR34_RESETN_DIS BIT(7) +#define MCR34_MREQI_DIS BIT(6) +#define MCR34_MREQ_BYPASS_DIS BIT(5) +#define MCR34_RGAP_CTRL_EN BIT(4) +#define MCR34_CKE_OUT_IN_SELF_REF_DIS BIT(3) +#define MCR34_FOURCE_SELF_REF_EN BIT(2) +#define MCR34_AUTOPWRDN_EN BIT(1) +#define MCR34_CKE_EN BIT(0) + +#define MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT 16 +#define MCR38_RW_MAX_GRANT_CNT_RQ_MASK GENMASK(20, 16) + +/* default request queued limitation mask (0xFFBBFFF4) */ +#define MCR3C_DEFAULT_MASK \ + ~(REQ_PRI_VGA_HW_CURSOR_R | REQ_PRI_VGA_CRT_R | REQ_PRI_PCIE_BUS1_RW | \ + REQ_PRI_XDMA1_RW | REQ_PRI_2D_ENGINE_DATA_RW) + +#define MCR50_RESET_ALL_INTR BIT(31) +#define SDRAM_CONF_ECC_AUTO_SCRUBBING BIT(9) +#define SDRAM_CONF_SCRAMBLE BIT(8) +#define SDRAM_CONF_ECC_EN BIT(7) +#define SDRAM_CONF_DUALX8 BIT(5) +#define SDRAM_CONF_DDR4 BIT(4) +#define SDRAM_CONF_VGA_SIZE_SHIFT 2 +#define SDRAM_CONF_VGA_SIZE_MASK GENMASK(3, 2) +#define SDRAM_CONF_CAP_SHIFT 0 +#define SDRAM_CONF_CAP_MASK GENMASK(1, 0) + +#define SDRAM_CONF_CAP_256M 0 +#define SDRAM_CONF_CAP_512M 1 +#define SDRAM_CONF_CAP_1024M 2 +#define SDRAM_CONF_CAP_2048M 3 +#define SDRAM_CONF_ECC_SETUP (SDRAM_CONF_ECC_AUTO_SCRUBBING | SDRAM_CONF_ECC_EN) + +#define SDRAM_MISC_DDR4_TREFRESH (1 << 3) + +#define SDRAM_PHYCTRL0_PLL_LOCKED BIT(4) +#define SDRAM_PHYCTRL0_NRST BIT(2) +#define SDRAM_PHYCTRL0_INIT BIT(0) + +/* MCR0C */ +#define SDRAM_REFRESH_PERIOD_ZQCS_SHIFT 16 +#define SDRAM_REFRESH_PERIOD_ZQCS_MASK GENMASK(31, 16) +#define SDRAM_REFRESH_PERIOD_SHIFT 8 +#define SDRAM_REFRESH_PERIOD_MASK GENMASK(15, 8) +#define SDRAM_REFRESH_ZQCS_EN BIT(7) +#define SDRAM_RESET_DLL_ZQCL_EN BIT(6) +#define SDRAM_LOW_PRI_REFRESH_EN BIT(5) +#define SDRAM_FORCE_PRECHARGE_EN BIT(4) +#define SDRAM_REFRESH_EN BIT(0) + +#define SDRAM_TEST_LEN_SHIFT 4 +#define SDRAM_TEST_LEN_MASK 0xfffff +#define SDRAM_TEST_START_ADDR_SHIFT 24 +#define SDRAM_TEST_START_ADDR_MASK 0x3f + +#define SDRAM_TEST_EN (1 << 0) +#define SDRAM_TEST_MODE_SHIFT 1 +#define SDRAM_TEST_MODE_MASK (0x3 << SDRAM_TEST_MODE_SHIFT) +#define SDRAM_TEST_MODE_WO (0x0 << SDRAM_TEST_MODE_SHIFT) +#define SDRAM_TEST_MODE_RB (0x1 << SDRAM_TEST_MODE_SHIFT) +#define SDRAM_TEST_MODE_RW (0x2 << SDRAM_TEST_MODE_SHIFT) + +#define SDRAM_TEST_GEN_MODE_SHIFT 3 +#define SDRAM_TEST_GEN_MODE_MASK (7 << SDRAM_TEST_GEN_MODE_SHIFT) +#define SDRAM_TEST_TWO_MODES (1 << 6) +#define SDRAM_TEST_ERRSTOP (1 << 7) +#define SDRAM_TEST_DONE (1 << 12) +#define SDRAM_TEST_FAIL (1 << 13) + +#define SDRAM_AC_TRFC_SHIFT 0 +#define SDRAM_AC_TRFC_MASK 0xff + +#define SDRAM_ECC_RANGE_ADDR_MASK GENMASK(30, 20) +#define SDRAM_ECC_RANGE_ADDR_SHIFT 20 + +#ifndef __ASSEMBLY__ +struct ast2600_sdrammc_regs { + u32 protection_key; /* offset 0x00 */ + u32 config; /* offset 0x04 */ + u32 gm_protection_key; /* offset 0x08 */ + u32 refresh_timing; /* offset 0x0C */ + u32 ac_timing[4]; /* offset 0x10 ~ 0x1C */ + u32 mr01_mode_setting; /* offset 0x20 */ + u32 mr23_mode_setting; /* offset 0x24 */ + u32 mr45_mode_setting; /* offset 0x28 */ + u32 mr6_mode_setting; /* offset 0x2C */ + u32 mode_setting_control; /* offset 0x30 */ + u32 power_ctrl; /* offset 0x34 */ + u32 arbitration_ctrl; /* offset 0x38 */ + u32 req_limit_mask; /* offset 0x3C */ + u32 max_grant_len[4]; /* offset 0x40 ~ 0x4C */ + u32 intr_ctrl; /* offset 0x50 */ + u32 ecc_range_ctrl; /* offset 0x54 */ + u32 first_ecc_err_addr; /* offset 0x58 */ + u32 last_ecc_err_addr; /* offset 0x5C */ + u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */ + u32 ecc_test_ctrl; /* offset 0x70 */ + u32 test_addr; /* offset 0x74 */ + u32 test_fail_dq_bit; /* offset 0x78 */ + u32 test_init_val; /* offset 0x7C */ + u32 req_input_ctrl; /* offset 0x80 */ + u32 req_high_pri_ctrl; /* offset 0x84 */ + u32 reserved0[6]; /* offset 0x88 ~ 0x9C */ +}; +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARCH_SDRAM_AST2600_H */ diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index 020c913188..049b9dc249 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -1,4 +1,5 @@ if RAM || SPL_RAM + config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" depends on DM && OF_CONTROL && ARCH_ASPEED @@ -7,4 +8,62 @@ config ASPEED_DDR4_DUALX8 Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram controller needs to know if the memory chip mounted on the board is dual x8 die or not. Or it may get the wrong size of the memory space. -endif + +if ASPEED_AST2600 + +choice + prompt "DDR4 target date rate" + default ASPEED_DDR4_1600 + +config ASPEED_DDR4_400 + bool "DDR4 targets at 400Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 400M + +config ASPEED_DDR4_800 + bool "DDR4 targets at 800Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 800M + +config ASPEED_DDR4_1333 + bool "DDR4 targets at 1333Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 1333M + +config ASPEED_DDR4_1600 + bool "DDR4 targets at 1600Mbps" + depends on DM && OF_CONTROL && ARCH_ASPEED + help + select DDR4 target data rate at 1600M +endchoice + +config ASPEED_BYPASS_SELFTEST + bool "bypass self test during DRAM initialization" + default n + help + Say Y here to bypass DRAM self test to speed up the boot time + +config ASPEED_ECC + bool "aspeed SDRAM error correcting code" + depends on DM && OF_CONTROL && ARCH_ASPEED + default n + help + enable SDRAM ECC function + +if ASPEED_ECC +config ASPEED_ECC_SIZE + int "ECC size: 0=driver auto-caluated" + depends on ASPEED_ECC + default 0 + help + SDRAM size with the error correcting code enabled. The unit is + in Megabytes. Noted that only the 8/9 of the configured size + can be used by the system. The remaining 1/9 will be used by + the ECC engine. If the size is set to 0, the sdram driver will + calculate the SDRAM size and set the whole range be ECC enabled. +endif # end of ASPEED_ECC +endif # end of ASPEED_AST2600 +endif # end of RAM || SPL_RAM diff --git a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile index af604f8a4b..7ac10af1c2 100644 --- a/drivers/ram/aspeed/Makefile +++ b/drivers/ram/aspeed/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o \ No newline at end of file +obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o +obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c new file mode 100644 index 0000000000..34ef394f44 --- /dev/null +++ b/drivers/ram/aspeed/sdram_ast2600.c @@ -0,0 +1,1061 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <errno.h> +#include <ram.h> +#include <regmap.h> +#include <reset.h> +#include <asm/io.h> +#include <asm/arch/scu_ast2600.h> +#include <asm/arch/sdram_ast2600.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <dt-bindings/clock/ast2600-clock.h> + +#define DDR_PHY_TBL_CHG_ADDR 0xaeeddeea +#define DDR_PHY_TBL_END 0xaeededed + +#if defined(CONFIG_ASPEED_DDR4_800) +u32 ast2600_sdramphy_config[165] = { + 0x1e6e0100, // start address + 0x00000000, // phyr000 + 0x0c002062, // phyr004 + 0x1a7a0063, // phyr008 + 0x5a7a0063, // phyr00c + 0x1a7a0063, // phyr010 + 0x1a7a0063, // phyr014 + 0x20000000, // phyr018 + 0x20000000, // phyr01c + 0x20000000, // phyr020 + 0x20000000, // phyr024 + 0x00000008, // phyr028 + 0x00000000, // phyr02c + 0x00077600, // phyr030 + 0x00000000, // phyr034 + 0x00000000, // phyr038 + 0x20000000, // phyr03c + 0x50506000, // phyr040 + 0x50505050, // phyr044 + 0x00002f07, // phyr048 + 0x00003080, // phyr04c + 0x04000000, // phyr050 + 0x00000200, // phyr054 + 0x03140201, // phyr058 + 0x04800000, // phyr05c + 0x0800044e, // phyr060 + 0x00000000, // phyr064 + 0x00180008, // phyr068 + 0x00e00400, // phyr06c + 0x00140206, // phyr070 + 0x1d4c0000, // phyr074 + 0x493e0107, // phyr078 + 0x08060404, // phyr07c + 0x90000a00, // phyr080 + 0x06420618, // phyr084 + 0x00001002, // phyr088 + 0x05701016, // phyr08c + 0x10000000, // phyr090 + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x00002020, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e01cc, // new address + 0x01010101, // phyr0cc + 0x01010101, // phyr0d0 + 0x80808080, // phyr0d4 + 0x80808080, // phyr0d8 + 0xaeeddeea, // change address + 0x1e6e0288, // new address + 0x80808080, // phyr188 + 0x80808080, // phyr18c + 0x80808080, // phyr190 + 0x80808080, // phyr194 + 0xaeeddeea, // change address + 0x1e6e02f8, // new address + 0x90909090, // phyr1f8 + 0x88888888, // phyr1fc + 0xaeeddeea, // change address + 0x1e6e0300, // new address + 0x00000000, // phyr200 + 0xaeeddeea, // change address + 0x1e6e0194, // new address + 0x80118260, // phyr094 + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x80000000, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e0318, // new address + 0x09222719, // phyr218 + 0x00aa4403, // phyr21c + 0xaeeddeea, // change address + 0x1e6e0198, // new address + 0x08060000, // phyr098 + 0xaeeddeea, // change address + 0x1e6e01b0, // new address + 0x00000000, // phyr0b0 + 0x00000000, // phyr0b4 + 0x00000000, // phyr0b8 + 0x00000000, // phyr0bc + 0x00000000, // phyr0c0 + 0x00000000, // phyr0c4 + 0x000aff2c, // phyr0c8 + 0xaeeddeea, // change address + 0x1e6e01dc, // new address + 0x00080000, // phyr0dc + 0x00000000, // phyr0e0 + 0xaa55aa55, // phyr0e4 + 0x55aa55aa, // phyr0e8 + 0xaaaa5555, // phyr0ec + 0x5555aaaa, // phyr0f0 + 0xaa55aa55, // phyr0f4 + 0x55aa55aa, // phyr0f8 + 0xaaaa5555, // phyr0fc + 0x5555aaaa, // phyr100 + 0xaa55aa55, // phyr104 + 0x55aa55aa, // phyr108 + 0xaaaa5555, // phyr10c + 0x5555aaaa, // phyr110 + 0xaa55aa55, // phyr114 + 0x55aa55aa, // phyr118 + 0xaaaa5555, // phyr11c + 0x5555aaaa, // phyr120 + 0x20202020, // phyr124 + 0x20202020, // phyr128 + 0x20202020, // phyr12c + 0x20202020, // phyr130 + 0x20202020, // phyr134 + 0x20202020, // phyr138 + 0x20202020, // phyr13c + 0x20202020, // phyr140 + 0x20202020, // phyr144 + 0x20202020, // phyr148 + 0x20202020, // phyr14c + 0x20202020, // phyr150 + 0x20202020, // phyr154 + 0x20202020, // phyr158 + 0x20202020, // phyr15c + 0x20202020, // phyr160 + 0x20202020, // phyr164 + 0x20202020, // phyr168 + 0x20202020, // phyr16c + 0x20202020, // phyr170 + 0xaeeddeea, // change address + 0x1e6e0298, // new address + 0x20200800, // phyr198 + 0x20202020, // phyr19c + 0x20202020, // phyr1a0 + 0x20202020, // phyr1a4 + 0x20202020, // phyr1a8 + 0x20202020, // phyr1ac + 0x20202020, // phyr1b0 + 0x20202020, // phyr1b4 + 0x20202020, // phyr1b8 + 0x20202020, // phyr1bc + 0x20202020, // phyr1c0 + 0x20202020, // phyr1c4 + 0x20202020, // phyr1c8 + 0x20202020, // phyr1cc + 0x20202020, // phyr1d0 + 0x20202020, // phyr1d4 + 0x20202020, // phyr1d8 + 0x20202020, // phyr1dc + 0x20202020, // phyr1e0 + 0x20202020, // phyr1e4 + 0x00002020, // phyr1e8 + 0xaeeddeea, // change address + 0x1e6e0304, // new address + 0x00000800, // phyr204 + 0xaeeddeea, // change address + 0x1e6e027c, // new address + 0x4e400000, // phyr17c + 0x59595959, // phyr180 + 0x40404040, // phyr184 + 0xaeeddeea, // change address + 0x1e6e02f4, // new address + 0x00000059, // phyr1f4 + 0xaeededed, // end +}; +#else +u32 ast2600_sdramphy_config[165] = { + 0x1e6e0100, // start address + 0x00000000, // phyr000 + 0x0c002062, // phyr004 + 0x1a7a0063, // phyr008 + 0x5a7a0063, // phyr00c + 0x1a7a0063, // phyr010 + 0x1a7a0063, // phyr014 + 0x20000000, // phyr018 + 0x20000000, // phyr01c + 0x20000000, // phyr020 + 0x20000000, // phyr024 + 0x00000008, // phyr028 + 0x00000000, // phyr02c + 0x00077600, // phyr030 + 0x00000000, // phyr034 + 0x00000000, // phyr038 + 0x20000000, // phyr03c + 0x50506000, // phyr040 + 0x50505050, // phyr044 + 0x00002f07, // phyr048 + 0x00003080, // phyr04c + 0x04000000, // phyr050 + 0x00000200, // phyr054 + 0x03140501, // phyr058-rtt:40 + 0x04800000, // phyr05c + 0x0800044e, // phyr060 + 0x00000000, // phyr064 + 0x00180008, // phyr068 + 0x00e00400, // phyr06c + 0x00140206, // phyr070 + 0x1d4c0000, // phyr074 + 0x493e0107, // phyr078 + 0x08060404, // phyr07c + 0x90000a00, // phyr080 + 0x06420c30, // phyr084 + 0x00001002, // phyr088 + 0x05701016, // phyr08c + 0x10000000, // phyr090 + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x00002020, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e01cc, // new address + 0x01010101, // phyr0cc + 0x01010101, // phyr0d0 + 0x80808080, // phyr0d4 + 0x80808080, // phyr0d8 + 0xaeeddeea, // change address + 0x1e6e0288, // new address + 0x80808080, // phyr188 + 0x80808080, // phyr18c + 0x80808080, // phyr190 + 0x80808080, // phyr194 + 0xaeeddeea, // change address + 0x1e6e02f8, // new address + 0x90909090, // phyr1f8 + 0x88888888, // phyr1fc + 0xaeeddeea, // change address + 0x1e6e0300, // new address + 0x00000000, // phyr200 + 0xaeeddeea, // change address + 0x1e6e0194, // new address + 0x801112e0, // phyr094 - bit12=1,15=0,- write window is ok + 0xaeeddeea, // change address + 0x1e6e019c, // new address + 0x20202020, // phyr09c + 0x20202020, // phyr0a0 + 0x00002020, // phyr0a4 + 0x80000000, // phyr0a8 + 0x00000001, // phyr0ac + 0xaeeddeea, // change address + 0x1e6e0318, // new address + 0x09222719, // phyr218 + 0x00aa4403, // phyr21c + 0xaeeddeea, // change address + 0x1e6e0198, // new address + 0x08060000, // phyr098 + 0xaeeddeea, // change address + 0x1e6e01b0, // new address + 0x00000000, // phyr0b0 + 0x00000000, // phyr0b4 + 0x00000000, // phyr0b8 + 0x00000000, // phyr0bc + 0x00000000, // phyr0c0 - ori + 0x00000000, // phyr0c4 + 0x000aff2c, // phyr0c8 + 0xaeeddeea, // change address + 0x1e6e01dc, // new address + 0x00080000, // phyr0dc + 0x00000000, // phyr0e0 + 0xaa55aa55, // phyr0e4 + 0x55aa55aa, // phyr0e8 + 0xaaaa5555, // phyr0ec + 0x5555aaaa, // phyr0f0 + 0xaa55aa55, // phyr0f4 + 0x55aa55aa, // phyr0f8 + 0xaaaa5555, // phyr0fc + 0x5555aaaa, // phyr100 + 0xaa55aa55, // phyr104 + 0x55aa55aa, // phyr108 + 0xaaaa5555, // phyr10c + 0x5555aaaa, // phyr110 + 0xaa55aa55, // phyr114 + 0x55aa55aa, // phyr118 + 0xaaaa5555, // phyr11c + 0x5555aaaa, // phyr120 + 0x20202020, // phyr124 + 0x20202020, // phyr128 + 0x20202020, // phyr12c + 0x20202020, // phyr130 + 0x20202020, // phyr134 + 0x20202020, // phyr138 + 0x20202020, // phyr13c + 0x20202020, // phyr140 + 0x20202020, // phyr144 + 0x20202020, // phyr148 + 0x20202020, // phyr14c + 0x20202020, // phyr150 + 0x20202020, // phyr154 + 0x20202020, // phyr158 + 0x20202020, // phyr15c + 0x20202020, // phyr160 + 0x20202020, // phyr164 + 0x20202020, // phyr168 + 0x20202020, // phyr16c + 0x20202020, // phyr170 + 0xaeeddeea, // change address + 0x1e6e0298, // new address + 0x20200800, // phyr198 + 0x20202020, // phyr19c + 0x20202020, // phyr1a0 + 0x20202020, // phyr1a4 + 0x20202020, // phyr1a8 + 0x20202020, // phyr1ac + 0x20202020, // phyr1b0 + 0x20202020, // phyr1b4 + 0x20202020, // phyr1b8 + 0x20202020, // phyr1bc + 0x20202020, // phyr1c0 + 0x20202020, // phyr1c4 + 0x20202020, // phyr1c8 + 0x20202020, // phyr1cc + 0x20202020, // phyr1d0 + 0x20202020, // phyr1d4 + 0x20202020, // phyr1d8 + 0x20202020, // phyr1dc + 0x20202020, // phyr1e0 + 0x20202020, // phyr1e4 + 0x00002020, // phyr1e8 + 0xaeeddeea, // change address + 0x1e6e0304, // new address + 0x00000800, // phyr204 + 0xaeeddeea, // change address + 0x1e6e027c, // new address + 0x4e400000, // phyr17c + 0x59595959, // phyr180 + 0x40404040, // phyr184 + 0xaeeddeea, // change address + 0x1e6e02f4, // new address + 0x00000059, // phyr1f4 + 0xaeededed, // end +}; +#endif + +/* MPLL configuration */ +#define SCU_MPLL_FREQ_400M 0x0008405F +#define SCU_MPLL_EXT_400M 0x0000002F +#define SCU_MPLL_FREQ_333M 0x00488299 +#define SCU_MPLL_EXT_333M 0x0000014C +#define SCU_MPLL_FREQ_200M 0x0078007F +#define SCU_MPLL_EXT_200M 0x0000003F +#define SCU_MPLL_FREQ_100M 0x0078003F +#define SCU_MPLL_EXT_100M 0x0000001F + +#if defined(CONFIG_ASPEED_DDR4_1600) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_400M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_400M +#elif defined(CONFIG_ASPEED_DDR4_1333) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_333M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_333M +#elif defined(CONFIG_ASPEED_DDR4_800) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_200M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_200M +#elif defined(CONFIG_ASPEED_DDR4_400) +#define SCU_MPLL_FREQ_CFG SCU_MPLL_FREQ_100M +#define SCU_MPLL_EXT_CFG SCU_MPLL_EXT_100M +#else +#error "undefined DDR4 target rate\n" +#endif + +/* + * AC timing and SDRAM mode register setting + * for real chip are derived from the model GDDR4-1600 + */ +#define DDR4_MR01_MODE 0x03010510 +#define DDR4_MR23_MODE 0x00000000 +#define DDR4_MR45_MODE 0x04000000 +#define DDR4_MR6_MODE 0x00000400 +#define DDR4_TRFC_1600 0x467299f1 +#define DDR4_TRFC_1333 0x3a5f80c9 +#define DDR4_TRFC_800 0x23394c78 +#define DDR4_TRFC_400 0x111c263c + +#if defined(CONFIG_ASPEED_DDR4_1600) +#define DDR4_TRFC DDR4_TRFC_1600 +#define DDR4_PHY_TRAIN_TRFC 0xc30 +#elif defined(CONFIG_ASPEED_DDR4_1333) +#define DDR4_TRFC DDR4_TRFC_1333 +#define DDR4_PHY_TRAIN_TRFC 0xa25 +#elif defined(CONFIG_ASPEED_DDR4_800) +#define DDR4_TRFC DDR4_TRFC_800 +#define DDR4_PHY_TRAIN_TRFC 0x618 +#elif defined(CONFIG_ASPEED_DDR4_400) +#define DDR4_TRFC DDR4_TRFC_400 +#define DDR4_PHY_TRAIN_TRFC 0x30c +#else +#error "undefined tRFC setting" +#endif + +/* supported SDRAM size */ +#define SDRAM_SIZE_1KB (1024U) +#define SDRAM_SIZE_1MB (SDRAM_SIZE_1KB * SDRAM_SIZE_1KB) +#define SDRAM_MIN_SIZE (256 * SDRAM_SIZE_1MB) +#define SDRAM_MAX_SIZE (2048 * SDRAM_SIZE_1MB) + +DECLARE_GLOBAL_DATA_PTR; + +static const u32 ddr4_ac_timing[4] = { + 0x040e0307, 0x0f4711f1, 0x0e060304, 0x00001240 }; +static const u32 ddr_max_grant_params[4] = { + 0x44444444, 0x44444444, 0x44444444, 0x44444444 }; + +struct dram_info { + struct ram_info info; + struct clk ddr_clk; + struct ast2600_sdrammc_regs *regs; + struct ast2600_scu *scu; + struct ast2600_ddr_phy *phy; + void __iomem *phy_setting; + void __iomem *phy_status; + ulong clock_rate; +}; + +static void ast2600_sdramphy_kick_training(struct dram_info *info) +{ + u32 data; + struct ast2600_sdrammc_regs *regs = info->regs; + + writel(SDRAM_PHYCTRL0_NRST, &regs->phy_ctrl[0]); + udelay(5); + writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, &regs->phy_ctrl[0]); + udelay(1000); + + while (1) { + data = readl(&regs->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; + if (~data) + break; + } +} + +/** + * @brief load DDR-PHY configurations table to the PHY registers + * @param[in] p_tbl - pointer to the configuration table + * @param[in] info - pointer to the DRAM info struct + * + * There are two sets of MRS (Mode Registers) configuration in ast2600 memory + * system: one is in the SDRAM MC (memory controller) which is used in run + * time, and the other is in the DDR-PHY IP which is used during DDR-PHY + * training. + */ +static void ast2600_sdramphy_init(u32 *p_tbl, struct dram_info *info) +{ + u32 reg_base = (u32)info->phy_setting; + u32 addr = p_tbl[0]; + u32 data; + int i = 1; + + writel(0, &info->regs->phy_ctrl[0]); + udelay(10); + + while (1) { + if (addr < reg_base) { + debug("invalid DDR-PHY addr: 0x%08x\n", addr); + break; + } + data = p_tbl[i++]; + + if (data == DDR_PHY_TBL_END) { + break; + } else if (data == DDR_PHY_TBL_CHG_ADDR) { + addr = p_tbl[i++]; + } else { + writel(data, addr); + addr += 4; + } + } + + data = readl(info->phy_setting + 0x84) & ~GENMASK(16, 0); + data |= DDR4_PHY_TRAIN_TRFC; + writel(data, info->phy_setting + 0x84); +} + +static int ast2600_sdramphy_check_status(struct dram_info *info) +{ + u32 value, tmp; + u32 reg_base = (u32)info->phy_status; + int need_retrain = 0; + + debug("\nSDRAM PHY training report:\n"); + + /* training status */ + value = readl(reg_base + 0x00); + debug("rO_DDRPHY_reg offset 0x00 = 0x%08x\n", value); + + if (value & BIT(3)) + debug("\tinitial PVT calibration fail\n"); + + if (value & BIT(5)) + debug("\truntime calibration fail\n"); + + /* PU & PD */ + value = readl(reg_base + 0x30); + debug("rO_DDRPHY_reg offset 0x30 = 0x%08x\n", value); + debug(" PU = 0x%02x\n", value & 0xff); + debug(" PD = 0x%02x\n", (value >> 16) & 0xff); + + /* read eye window */ + value = readl(reg_base + 0x68); + if (0 == (value & GENMASK(7, 0))) + need_retrain = 1; + + debug("rO_DDRPHY_reg offset 0x68 = 0x%08x\n", value); + debug(" rising edge of read data eye training pass window\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; + debug(" B1:%d%%\n", tmp); + + value = readl(reg_base + 0xC8); + debug("rO_DDRPHY_reg offset 0xC8 = 0x%08x\n", value); + debug(" falling edge of read data eye training pass window\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; + debug(" B1:%d%%\n", tmp); + + /* write eye window */ + value = readl(reg_base + 0x7c); + if (0 == (value & GENMASK(7, 0))) + need_retrain = 1; + + debug("rO_DDRPHY_reg offset 0x7C = 0x%08x\n", value); + debug(" rising edge of write data eye training pass window\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 255; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 255; + debug(" B1:%d%%\n", tmp); + + /* read Vref training result */ + value = readl(reg_base + 0x88); + debug("rO_DDRPHY_reg offset 0x88 = 0x%08x\n", value); + debug(" read Vref training result\n"); + tmp = (((value & GENMASK(7, 0)) >> 0) * 100) / 127; + debug(" B0:%d%%\n", tmp); + tmp = (((value & GENMASK(15, 8)) >> 8) * 100) / 127; + debug(" B1:%d%%\n", tmp); + + /* write Vref training result */ + value = readl(reg_base + 0x90); + debug("rO_DDRPHY_reg offset 0x90 = 0x%08x\n", value); + + /* gate train */ + value = readl(reg_base + 0x50); + if ((0 == (value & GENMASK(15, 0))) || + (0 == (value & GENMASK(31, 16)))) { + need_retrain = 1; + } + + debug("rO_DDRPHY_reg offset 0x50 = 0x%08x\n", value); + + return need_retrain; +} + +#ifndef CONFIG_ASPEED_BYPASS_SELFTEST +#define MC_TEST_PATTERN_N 8 +static u32 as2600_sdrammc_test_pattern[MC_TEST_PATTERN_N] = { + 0xcc33cc33, 0xff00ff00, 0xaa55aa55, 0x88778877, + 0x92cc4d6e, 0x543d3cde, 0xf1e843c7, 0x7c61d253 }; + +#define TIMEOUT_DRAM 5000000 +int ast2600_sdrammc_dg_test(struct dram_info *info, unsigned int datagen, u32 mode) +{ + unsigned int data; + unsigned int timeout = 0; + struct ast2600_sdrammc_regs *regs = info->regs; + + writel(0, &regs->ecc_test_ctrl); + + if (mode == 0) + writel(0x00000085 | (datagen << 3), &regs->ecc_test_ctrl); + else + writel(0x000000C1 | (datagen << 3), &regs->ecc_test_ctrl); + + do { + data = readl(&regs->ecc_test_ctrl) & GENMASK(13, 12); + + if (data & BIT(13)) + return 0; + + if (++timeout > TIMEOUT_DRAM) { + debug("Timeout!!\n"); + writel(0, &regs->ecc_test_ctrl); + return -1; + } + } while (!data); + + writel(0, &regs->ecc_test_ctrl); + + return 0; +} + +int ast2600_sdrammc_cbr_test(struct dram_info *info) +{ + u32 i; + struct ast2600_sdrammc_regs *regs = info->regs; + + clrsetbits_le32(&regs->test_addr, GENMASK(30, 4), 0x7ffff0); + + /* single */ + for (i = 0; i < 8; i++) + if (ast2600_sdrammc_dg_test(info, i, 0)) + return -1; + + /* burst */ + for (i = 0; i < 8; i++) + if (ast2600_sdrammc_dg_test(info, i, i)) + return -1; + + return 0; +} + +static int ast2600_sdrammc_test(struct dram_info *info) +{ + struct ast2600_sdrammc_regs *regs = info->regs; + + u32 pass_cnt = 0; + u32 fail_cnt = 0; + u32 target_cnt = 2; + u32 test_cnt = 0; + u32 pattern; + u32 i = 0; + bool finish = false; + + debug("sdram mc test:\n"); + while (!finish) { + pattern = as2600_sdrammc_test_pattern[i++]; + i = i % MC_TEST_PATTERN_N; + debug(" pattern = %08X : ", pattern); + writel(pattern, &regs->test_init_val); + + if (ast2600_sdrammc_cbr_test(info)) { + debug("fail\n"); + fail_cnt++; + } else { + debug("pass\n"); + pass_cnt++; + } + + if (++test_cnt == target_cnt) + finish = true; + } + debug("statistics: pass/fail/total:%d/%d/%d\n", pass_cnt, fail_cnt, + target_cnt); + + return fail_cnt; +} +#endif + +/* + * scu500[14:13] + * 2b'00: VGA memory size = 16MB + * 2b'01: VGA memory size = 16MB + * 2b'10: VGA memory size = 32MB + * 2b'11: VGA memory size = 64MB + * + * mcr04[3:2] + * 2b'00: VGA memory size = 8MB + * 2b'01: VGA memory size = 16MB + * 2b'10: VGA memory size = 32MB + * 2b'11: VGA memory size = 64MB + */ +static size_t ast2600_sdrammc_get_vga_mem_size(struct dram_info *info) +{ + u32 vga_hwconf; + size_t vga_mem_size_base = 8 * 1024 * 1024; + + vga_hwconf = + (readl(&info->scu->hwstrap1) & SCU_HWSTRAP1_VGA_MEM_MASK) >> + SCU_HWSTRAP1_VGA_MEM_SHIFT; + + if (vga_hwconf == 0) { + vga_hwconf = 1; + writel(vga_hwconf << SCU_HWSTRAP1_VGA_MEM_SHIFT, + &info->scu->hwstrap1); + } + + clrsetbits_le32(&info->regs->config, SDRAM_CONF_VGA_SIZE_MASK, + ((vga_hwconf << SDRAM_CONF_VGA_SIZE_SHIFT) & + SDRAM_CONF_VGA_SIZE_MASK)); + + /* no need to reserve VGA memory if efuse[VGA disable] is set */ + if (readl(&info->scu->efuse) & SCU_EFUSE_DIS_VGA) + return 0; + + return vga_mem_size_base << vga_hwconf; +} + +/* + * Find out RAM size and save it in dram_info + * + * The procedure is taken from Aspeed SDK + */ +static void ast2600_sdrammc_calc_size(struct dram_info *info) +{ + /* The controller supports 256/512/1024/2048 MB ram */ + size_t ram_size = SDRAM_MIN_SIZE; + const int write_test_offset = 0x100000; + u32 test_pattern = 0xdeadbeef; + u32 cap_param = SDRAM_CONF_CAP_2048M; + u32 refresh_timing_param = DDR4_TRFC; + const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset; + + for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; + ram_size >>= 1) { + writel(test_pattern, write_addr_base + (ram_size >> 1)); + test_pattern = (test_pattern >> 4) | (test_pattern << 28); + } + + /* One last write to overwrite all wrapped values */ + writel(test_pattern, write_addr_base); + + /* Reset the pattern and see which value was really written */ + test_pattern = 0xdeadbeef; + for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE; + ram_size >>= 1) { + if (readl(write_addr_base + (ram_size >> 1)) == test_pattern) + break; + + --cap_param; + refresh_timing_param >>= 8; + test_pattern = (test_pattern >> 4) | (test_pattern << 28); + } + + clrsetbits_le32(&info->regs->ac_timing[1], + (SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT), + ((refresh_timing_param & SDRAM_AC_TRFC_MASK) + << SDRAM_AC_TRFC_SHIFT)); + + info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); + + clrsetbits_le32(&info->regs->config, SDRAM_CONF_CAP_MASK, + ((cap_param << SDRAM_CONF_CAP_SHIFT) & SDRAM_CONF_CAP_MASK)); +} + +static int ast2600_sdrammc_init_ddr4(struct dram_info *info) +{ + const u32 power_ctrl = MCR34_CKE_EN | MCR34_AUTOPWRDN_EN | + MCR34_MREQ_BYPASS_DIS | MCR34_RESETN_DIS | + MCR34_ODT_EN | MCR34_ODT_AUTO_ON | + (0x1 << MCR34_ODT_EXT_SHIFT); + + /* init SDRAM-PHY only on real chip */ + ast2600_sdramphy_init(ast2600_sdramphy_config, info); + writel((MCR34_CKE_EN | MCR34_MREQI_DIS | MCR34_RESETN_DIS), + &info->regs->power_ctrl); + udelay(5); + ast2600_sdramphy_kick_training(info); + udelay(500); + writel(SDRAM_RESET_DLL_ZQCL_EN, &info->regs->refresh_timing); + + writel(MCR30_SET_MR(3), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(6), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(5), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(4), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(2), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(1), &info->regs->mode_setting_control); + writel(MCR30_SET_MR(0) | MCR30_RESET_DLL_DELAY_EN, + &info->regs->mode_setting_control); + + writel(SDRAM_REFRESH_EN | SDRAM_RESET_DLL_ZQCL_EN | + (0x5f << SDRAM_REFRESH_PERIOD_SHIFT), + &info->regs->refresh_timing); + + /* wait self-refresh idle */ + while (readl(&info->regs->power_ctrl) & + MCR34_SELF_REFRESH_STATUS_MASK) + ; + + writel(SDRAM_REFRESH_EN | SDRAM_LOW_PRI_REFRESH_EN | + SDRAM_REFRESH_ZQCS_EN | + (0x5f << SDRAM_REFRESH_PERIOD_SHIFT) | + (0x42aa << SDRAM_REFRESH_PERIOD_ZQCS_SHIFT), + &info->regs->refresh_timing); + + writel(power_ctrl, &info->regs->power_ctrl); + udelay(500); + + return 0; +} + +static void ast2600_sdrammc_unlock(struct dram_info *info) +{ + writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key); + while (!readl(&info->regs->protection_key)) + ; +} + +static void ast2600_sdrammc_lock(struct dram_info *info) +{ + writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key); + while (readl(&info->regs->protection_key)) + ; +} + +static void ast2600_sdrammc_common_init(struct ast2600_sdrammc_regs *regs) +{ + int i; + + writel(MCR34_MREQI_DIS | MCR34_RESETN_DIS, &regs->power_ctrl); + writel(SDRAM_VIDEO_UNLOCK_KEY, &regs->gm_protection_key); + writel(0x10 << MCR38_RW_MAX_GRANT_CNT_RQ_SHIFT, + &regs->arbitration_ctrl); + writel(0xFFBBFFF4, &regs->req_limit_mask); + + for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i) + writel(ddr_max_grant_params[i], &regs->max_grant_len[i]); + + writel(MCR50_RESET_ALL_INTR, &regs->intr_ctrl); + + writel(0x07FFFFFF, &regs->ecc_range_ctrl); + + writel(0, &regs->ecc_test_ctrl); + writel(0x80000001, &regs->test_addr); + writel(0, &regs->test_fail_dq_bit); + writel(0, &regs->test_init_val); + + writel(0xFFFFFFFF, &regs->req_input_ctrl); + writel(0, &regs->req_high_pri_ctrl); + + udelay(600); + +#ifdef CONFIG_ASPEED_DDR4_DUALX8 + writel(0x37, &regs->config); +#else + writel(0x17, &regs->config); +#endif + + /* load controller setting */ + for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i) + writel(ddr4_ac_timing[i], &regs->ac_timing[i]); + + writel(DDR4_MR01_MODE, &regs->mr01_mode_setting); + writel(DDR4_MR23_MODE, &regs->mr23_mode_setting); + writel(DDR4_MR45_MODE, &regs->mr45_mode_setting); + writel(DDR4_MR6_MODE, &regs->mr6_mode_setting); +} + +/* + * Update size info according to the ECC HW setting + * + * Assume SDRAM has been initialized by SPL or the host. To get the RAM size, we + * don't need to calculate the ECC size again but read from MCR04 and derive the + * size from its value. + */ +static void ast2600_sdrammc_update_size(struct dram_info *info) +{ + struct ast2600_sdrammc_regs *regs = info->regs; + u32 conf = readl(&regs->config); + u32 cap_param; + size_t ram_size = SDRAM_MAX_SIZE; + size_t hw_size; + + cap_param = (conf & SDRAM_CONF_CAP_MASK) >> SDRAM_CONF_CAP_SHIFT; + switch (cap_param) { + case SDRAM_CONF_CAP_2048M: + ram_size = 2048 * SDRAM_SIZE_1MB; + break; + case SDRAM_CONF_CAP_1024M: + ram_size = 1024 * SDRAM_SIZE_1MB; + break; + case SDRAM_CONF_CAP_512M: + ram_size = 512 * SDRAM_SIZE_1MB; + break; + case SDRAM_CONF_CAP_256M: + ram_size = 256 * SDRAM_SIZE_1MB; + break; + } + + info->info.base = CONFIG_SYS_SDRAM_BASE; + info->info.size = ram_size - ast2600_sdrammc_get_vga_mem_size(info); + + if (0 == (conf & SDRAM_CONF_ECC_SETUP)) + return; + + hw_size = readl(&regs->ecc_range_ctrl) & SDRAM_ECC_RANGE_ADDR_MASK; + hw_size += (1 << SDRAM_ECC_RANGE_ADDR_SHIFT); + + info->info.size = hw_size; +} + +#ifdef CONFIG_ASPEED_ECC +static void ast2600_sdrammc_ecc_enable(struct dram_info *info) +{ + struct ast2600_sdrammc_regs *regs = info->regs; + size_t conf_size; + u32 reg; + + conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB; + if (conf_size > info->info.size) { + printf("warning: ECC configured %dMB but actual size is %dMB\n", + CONFIG_ASPEED_ECC_SIZE, + info->info.size / SDRAM_SIZE_1MB); + conf_size = info->info.size; + } else if (conf_size == 0) { + conf_size = info->info.size; + } + + info->info.size = (((conf_size / 9) * 8) >> 20) << 20; + writel(((info->info.size >> 20) - 1) << 20, &regs->ecc_range_ctrl); + reg = readl(&regs->config) | SDRAM_CONF_ECC_SETUP; + writel(reg, &regs->config); + + writel(0, &regs->test_init_val); + writel(0x80000001, &regs->test_addr); + writel(0x221, &regs->ecc_test_ctrl); + while (0 == (readl(&regs->ecc_test_ctrl) & BIT(12))) + ; + writel(0, &regs->ecc_test_ctrl); + writel(BIT(31), &regs->intr_ctrl); + writel(0, &regs->intr_ctrl); +} +#endif + +static int ast2600_sdrammc_probe(struct udevice *dev) +{ + int ret; + u32 reg; + struct dram_info *priv = (struct dram_info *)dev_get_priv(dev); + struct ast2600_sdrammc_regs *regs = priv->regs; + struct udevice *clk_dev; + + /* find SCU base address from clock device */ + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(aspeed_ast2600_scu), &clk_dev); + if (ret) { + debug("clock device not defined\n"); + return ret; + } + + priv->scu = devfdt_get_addr_ptr(clk_dev); + if (IS_ERR(priv->scu)) { + debug("%s(): can't get SCU\n", __func__); + return PTR_ERR(priv->scu); + } + + if (readl(&priv->scu->dram_hdshk) & SCU_DRAM_HDSHK_RDY) { + printf("already initialized, "); + ast2600_sdrammc_update_size(priv); + return 0; + } + + reg = readl(&priv->scu->mpll); + reg &= ~(SCU_PLL_BYPASS | SCU_PLL_DIV_MASK | + SCU_PLL_DENUM_MASK | SCU_PLL_NUM_MASK); + reg |= (SCU_PLL_RST | SCU_PLL_OFF | SCU_MPLL_FREQ_CFG); + writel(reg, &priv->scu->mpll); + writel(SCU_MPLL_EXT_CFG, &priv->scu->mpll_ext); + udelay(100); + reg &= ~(SCU_PLL_RST | SCU_PLL_OFF); + writel(reg, &priv->scu->mpll); + + while ((readl(&priv->scu->mpll_ext) & BIT(31)) == 0) + ; + + ast2600_sdrammc_unlock(priv); + ast2600_sdrammc_common_init(regs); +L_ast2600_sdramphy_train: + ast2600_sdrammc_init_ddr4(priv); + + /* make sure DDR-PHY is ready before access */ + do { + reg = readl(priv->phy_status) & BIT(1); + } while (reg == 0); + + if (ast2600_sdramphy_check_status(priv) != 0) { + printf("DDR4 PHY training fail, retrain\n"); + goto L_ast2600_sdramphy_train; + } + + ast2600_sdrammc_calc_size(priv); + +#ifndef CONFIG_ASPEED_BYPASS_SELFTEST + if (ast2600_sdrammc_test(priv) != 0) { + printf("%s: DDR4 init fail\n", __func__); + return -EINVAL; + } +#endif + +#ifdef CONFIG_ASPEED_ECC + ast2600_sdrammc_ecc_enable(priv); +#endif + + writel(readl(&priv->scu->dram_hdshk) | SCU_DRAM_HDSHK_RDY, + &priv->scu->dram_hdshk); + + clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR); + ast2600_sdrammc_lock(priv); + return 0; +} + +static int ast2600_sdrammc_ofdata_to_platdata(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + + priv->regs = (void *)(uintptr_t)devfdt_get_addr_index(dev, 0); + priv->phy_setting = (void *)(uintptr_t)devfdt_get_addr_index(dev, 1); + priv->phy_status = (void *)(uintptr_t)devfdt_get_addr_index(dev, 2); + + priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), + "clock-frequency", 0); + if (!priv->clock_rate) { + debug("DDR Clock Rate not defined\n"); + return -EINVAL; + } + + return 0; +} + +static int ast2600_sdrammc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops ast2600_sdrammc_ops = { + .get_info = ast2600_sdrammc_get_info, +}; + +static const struct udevice_id ast2600_sdrammc_ids[] = { + { .compatible = "aspeed,ast2600-sdrammc" }, + { } +}; + +U_BOOT_DRIVER(sdrammc_ast2600) = { + .name = "aspeed_ast2600_sdrammc", + .id = UCLASS_RAM, + .of_match = ast2600_sdrammc_ids, + .ops = &ast2600_sdrammc_ops, + .ofdata_to_platdata = ast2600_sdrammc_ofdata_to_platdata, + .probe = ast2600_sdrammc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), +};

Add controller reset support through the System Control Unit (SCU) of AST2600 SoC.

Signed-off-by: Chia-Wei, Wang chiawei_wang@aspeedtech.com --- drivers/reset/Kconfig | 9 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-ast2600.c | 108 ++++++++++++++++++++++ include/dt-bindings/reset/ast2600-reset.h | 70 ++++++++++++++ 4 files changed, 188 insertions(+) create mode 100644 drivers/reset/reset-ast2600.c create mode 100644 include/dt-bindings/reset/ast2600-reset.h

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 33c2736554..f5b3f8826f 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -81,6 +81,15 @@ config RESET_AST2500 Say Y if you want to control reset signals of different peripherals through System Control Unit (SCU).

+config RESET_AST2600 + bool "Reset controller driver for AST2600 SoCs" + depends on DM_RESET + default y if ASPEED_AST2600 + help + Support for reset controller on AST2600 SoC. + Say Y if you want to control reset signals of different peripherals + through System Control Unit (SCU). + config RESET_ROCKCHIP bool "Reset controller driver for Rockchip SoCs" depends on DM_RESET && ARCH_ROCKCHIP && CLK diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index fa52aa3329..8a0f528076 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o +obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git a/drivers/reset/reset-ast2600.c b/drivers/reset/reset-ast2600.c new file mode 100644 index 0000000000..c402968fa8 --- /dev/null +++ b/drivers/reset/reset-ast2600.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 ASPEED Technology Inc. + */ + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <misc.h> +#include <reset.h> +#include <reset-uclass.h> +#include <linux/err.h> +#include <asm/io.h> +#include <asm/arch/scu_ast2600.h> + +struct ast2600_reset_priv { + struct ast2600_scu *scu; +}; + +static int ast2600_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int ast2600_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int ast2600_reset_assert(struct reset_ctl *reset_ctl) +{ + struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct ast2600_scu *scu = priv->scu; + + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id); + + if (reset_ctl->id < 32) + writel(BIT(reset_ctl->id), scu->modrst_ctrl1); + else + writel(BIT(reset_ctl->id - 32), scu->modrst_ctrl2); + + return 0; +} + +static int ast2600_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct ast2600_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct ast2600_scu *scu = priv->scu; + + debug("%s: reset_ctl->id: %lu\n", __func__, reset_ctl->id); + + if (reset_ctl->id < 32) + writel(BIT(reset_ctl->id), scu->modrst_clr1); + else + writel(BIT(reset_ctl->id - 32), scu->modrst_clr2); + + return 0; +} + +static int ast2600_reset_probe(struct udevice *dev) +{ + int rc; + struct ast2600_reset_priv *priv = dev_get_priv(dev); + struct udevice *scu_dev; + + /* get SCU base from clock device */ + rc = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(aspeed_ast2600_scu), &scu_dev); + if (rc) { + debug("%s: clock device not found, rc=%d\n", __func__, rc); + return rc; + } + + priv->scu = devfdt_get_addr_ptr(scu_dev); + if (IS_ERR_OR_NULL(priv->scu)) { + debug("%s: invalid SCU base pointer\n", __func__); + return PTR_ERR(priv->scu); + } + + return 0; +} + +static const struct udevice_id ast2600_reset_ids[] = { + { .compatible = "aspeed,ast2600-reset" }, + { } +}; + +struct reset_ops ast2600_reset_ops = { + .request = ast2600_reset_request, + .rfree = ast2600_reset_free, + .rst_assert = ast2600_reset_assert, + .rst_deassert = ast2600_reset_deassert, +}; + +U_BOOT_DRIVER(ast2600_reset) = { + .name = "ast2600_reset", + .id = UCLASS_RESET, + .of_match = ast2600_reset_ids, + .probe = ast2600_reset_probe, + .ops = &ast2600_reset_ops, + .priv_auto_alloc_size = sizeof(struct ast2600_reset_priv), +}; diff --git a/include/dt-bindings/reset/ast2600-reset.h b/include/dt-bindings/reset/ast2600-reset.h new file mode 100644 index 0000000000..b6d0f79917 --- /dev/null +++ b/include/dt-bindings/reset/ast2600-reset.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef _ABI_MACH_ASPEED_AST2600_RESET_H_ +#define _ABI_MACH_ASPEED_AST2600_RESET_H_ + +#define ASPEED_RESET_FSI (59) +#define ASPEED_RESET_RESERVED58 (58) +#define ASPEED_RESET_RESERVED57 (57) +#define ASPEED_RESET_SD (56) +#define ASPEED_RESET_ADC (55) +#define ASPEED_RESET_JTAG_MASTER2 (54) +#define ASPEED_RESET_MAC4 (53) +#define ASPEED_RESET_MAC3 (52) +#define ASPEED_RESET_RESERVE51 (51) +#define ASPEED_RESET_RESERVE50 (50) +#define ASPEED_RESET_RESERVE49 (49) +#define ASPEED_RESET_RESERVE48 (48) +#define ASPEED_RESET_RESERVE47 (47) +#define ASPEED_RESET_RESERVE46 (46) +#define ASPEED_RESET_I3C5 (45) +#define ASPEED_RESET_I3C4 (44) +#define ASPEED_RESET_I3C3 (43) +#define ASPEED_RESET_I3C2 (42) +#define ASPEED_RESET_I3C1 (41) +#define ASPEED_RESET_I3C0 (40) +#define ASPEED_RESET_I3C_DMA (39) +#define ASPEED_RESET_RESERVED38 (38) +#define ASPEED_RESET_PWM (37) +#define ASPEED_RESET_PECI (36) +#define ASPEED_RESET_MII (35) +#define ASPEED_RESET_I2C (34) +#define ASPEED_RESET_RESERVED33 (33) +#define ASPEED_RESET_LPC_ESPI (32) +#define ASPEED_RESET_H2X (31) +#define ASPEED_RESET_GP_MCU (30) +#define ASPEED_RESET_DP_MCU (29) +#define ASPEED_RESET_DP (28) +#define ASPEED_RESET_RC_XDMA (27) +#define ASPEED_RESET_GRAPHICS (26) +#define ASPEED_RESET_DEV_XDMA (25) +#define ASPEED_RESET_DEV_MCTP (24) +#define ASPEED_RESET_RC_MCTP (23) +#define ASPEED_RESET_JTAG_MASTER (22) +#define ASPEED_RESET_PCIE_DEV_OE (21) +#define ASPEED_RESET_PCIE_DEV_O (20) +#define ASPEED_RESET_PCIE_RC_OE (19) +#define ASPEED_RESET_PCIE_RC_O (18) +#define ASPEED_RESET_RESERVED17 (17) +#define ASPEED_RESET_EMMC (16) +#define ASPEED_RESET_UHCI (15) +#define ASPEED_RESET_EHCI_P1 (14) +#define ASPEED_RESET_CRT (13) +#define ASPEED_RESET_MAC2 (12) +#define ASPEED_RESET_MAC1 (11) +#define ASPEED_RESET_RESERVED10 (10) +#define ASPEED_RESET_RVAS (9) +#define ASPEED_RESET_PCI_VGA (8) +#define ASPEED_RESET_2D (7) +#define ASPEED_RESET_VIDEO (6) +#define ASPEED_RESET_PCI_DP (5) +#define ASPEED_RESET_HACE (4) +#define ASPEED_RESET_EHCI_P2 (3) +#define ASPEED_RESET_RESERVED2 (2) +#define ASPEED_RESET_AHB (1) +#define ASPEED_RESET_SDRAM (0) + +#endif /* _ABI_MACH_ASPEED_AST2600_RESET_H_ */

Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode.

However, currently the patch supports only the booting from memory-mapped SPI flash.

Signed-off-by: Chia-Wei, Wang chiawei_wang@aspeedtech.com --- arch/arm/include/asm/arch-aspeed/boot0.h | 23 ++ arch/arm/include/asm/arch-aspeed/platform.h | 5 + arch/arm/mach-aspeed/Kconfig | 20 ++ arch/arm/mach-aspeed/Makefile | 1 + arch/arm/mach-aspeed/ast2600/Kconfig | 17 ++ arch/arm/mach-aspeed/ast2600/Makefile | 2 + arch/arm/mach-aspeed/ast2600/board_common.c | 105 +++++++++ arch/arm/mach-aspeed/ast2600/lowlevel_init.S | 233 +++++++++++++++++++ arch/arm/mach-aspeed/ast2600/spl.c | 55 +++++ board/aspeed/evb_ast2600/Kconfig | 12 + board/aspeed/evb_ast2600/Makefile | 1 + board/aspeed/evb_ast2600/evb_ast2600.c | 5 + drivers/sysreset/sysreset_ast.c | 5 + include/configs/evb_ast2600.h | 16 ++ 14 files changed, 500 insertions(+) create mode 100644 arch/arm/include/asm/arch-aspeed/boot0.h create mode 100644 arch/arm/mach-aspeed/ast2600/Kconfig create mode 100644 arch/arm/mach-aspeed/ast2600/Makefile create mode 100644 arch/arm/mach-aspeed/ast2600/board_common.c create mode 100644 arch/arm/mach-aspeed/ast2600/lowlevel_init.S create mode 100644 arch/arm/mach-aspeed/ast2600/spl.c create mode 100644 board/aspeed/evb_ast2600/Kconfig create mode 100644 board/aspeed/evb_ast2600/Makefile create mode 100644 board/aspeed/evb_ast2600/evb_ast2600.c create mode 100644 include/configs/evb_ast2600.h

diff --git a/arch/arm/include/asm/arch-aspeed/boot0.h b/arch/arm/include/asm/arch-aspeed/boot0.h new file mode 100644 index 0000000000..368becc87a --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/boot0.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ + +#ifndef _ASM_ARCH_BOOT0_H +#define _ASM_ARCH_BOOT0_H + +_start: + ARM_VECTORS + + .word 0x0 /* key location */ + .word 0x0 /* start address of image */ + .word 0xfc00 /* maximum image size: 63KB */ + .word 0x0 /* signature address */ + .word 0x0 /* header revision ID low */ + .word 0x0 /* header revision ID high */ + .word 0x0 /* reserved */ + .word 0x0 /* checksum */ + .word 0x0 /* BL2 secure header */ + .word 0x0 /* public key or digest offset for BL2 */ + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h index 6cee036f54..d50ec5f8a9 100644 --- a/arch/arm/include/asm/arch-aspeed/platform.h +++ b/arch/arm/include/asm/arch-aspeed/platform.h @@ -13,6 +13,11 @@ #define ASPEED_DRAM_BASE 0x80000000 #define ASPEED_SRAM_BASE 0x1e720000 #define ASPEED_SRAM_SIZE 0x9000 +#elif defined(CONFIG_ASPEED_AST2600) +#define ASPEED_MAC_COUNT 4 +#define ASPEED_DRAM_BASE 0x80000000 +#define ASPEED_SRAM_BASE 0x10000000 +#define ASPEED_SRAM_SIZE 0x10000 #else #err "Unrecognized Aspeed platform." #endif diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index 4f021baa06..9a725f195a 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -9,6 +9,11 @@ config SYS_SOC config SYS_TEXT_BASE default 0x00000000

+choice + prompt "Aspeed SoC select" + depends on ARCH_ASPEED + default ASPEED_AST2500 + config ASPEED_AST2500 bool "Support Aspeed AST2500 SoC" depends on DM_RESET @@ -18,6 +23,21 @@ config ASPEED_AST2500 It is used as Board Management Controller on many server boards, which is enabled by support of LPC and eSPI peripherals.

+config ASPEED_AST2600 + bool "Support Aspeed AST2600 SoC" + select CPU_V7A + select CPU_V7_HAS_NONSEC + select SYS_ARCH_TIMER + select SUPPORT_SPL + select ENABLE_ARM_SOC_BOOT0_HOOK + help + The Aspeed AST2600 is a ARM-based SoC with Cortex-A7 CPU. + It is used as Board Management Controller on many server boards, + which is enabled by support of LPC and eSPI peripherals. + +endchoice + source "arch/arm/mach-aspeed/ast2500/Kconfig" +source "arch/arm/mach-aspeed/ast2600/Kconfig"

endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile index 33f65b50b2..42599c125b 100644 --- a/arch/arm/mach-aspeed/Makefile +++ b/arch/arm/mach-aspeed/Makefile @@ -4,3 +4,4 @@

obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o obj-$(CONFIG_ASPEED_AST2500) += ast2500/ +obj-$(CONFIG_ASPEED_AST2600) += ast2600/ diff --git a/arch/arm/mach-aspeed/ast2600/Kconfig b/arch/arm/mach-aspeed/ast2600/Kconfig new file mode 100644 index 0000000000..f3a53387a1 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2600/Kconfig @@ -0,0 +1,17 @@ +if ASPEED_AST2600 + +config SYS_CPU + default "armv7" + +config TARGET_EVB_AST2600 + bool "EVB-AST2600" + depends on ASPEED_AST2600 + help + EVB-AST2600 is Aspeed evaluation board for AST2600A0 chip. + It has 512M of RAM, 32M of SPI flash, two Ethernet ports, + 4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot, + 20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs. + +source "board/aspeed/evb_ast2600/Kconfig" + +endif diff --git a/arch/arm/mach-aspeed/ast2600/Makefile b/arch/arm/mach-aspeed/ast2600/Makefile new file mode 100644 index 0000000000..448d3201af --- /dev/null +++ b/arch/arm/mach-aspeed/ast2600/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel_init.o board_common.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c new file mode 100644 index 0000000000..642ea48d8e --- /dev/null +++ b/arch/arm/mach-aspeed/ast2600/board_common.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#include <common.h> +#include <dm.h> +#include <ram.h> +#include <timer.h> +#include <asm/io.h> +#include <asm/arch/timer.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <dm/uclass.h> +#include <asm/arch/scu_ast2600.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Memory Control registers */ +#define MCR_BASE 0x1e6e0000 +#define MCR_CONF (MCR_BASE + 0x004) + +/* bit fields of MCR_CONF */ +#define MCR_CONF_ECC_EN BIT(7) +#define MCR_CONF_VGA_MEMSZ_MASK GENMASK(3, 2) +#define MCR_CONF_VGA_MEMSZ_SHIFT 2 +#define MCR_CONF_MEMSZ_MASK GENMASK(1, 0) +#define MCR_CONF_MEMSZ_SHIFT 0 + +int dram_init(void) +{ + int ret; + struct udevice *dev; + struct ram_info ram; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("cannot get DRAM driver\n"); + return ret; + } + + ret = ram_get_info(dev, &ram); + if (ret) { + debug("cannot get DRAM information\n"); + return ret; + } + + gd->ram_size = ram.size; + return 0; +} + +int board_init(void) +{ + int i = 0, rc; + struct udevice *dev; + + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + while (1) { + rc = uclass_get_device(UCLASS_MISC, i++, &dev); + if (rc) + break; + } + + return 0; +} + +void board_add_ram_info(int use_default) +{ + int rc; + uint32_t conf; + uint32_t ecc, act_size, vga_rsvd; + struct udevice *scu_dev; + struct ast2600_scu *scu; + + rc = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(aspeed_ast2600_scu), &scu_dev); + if (rc) { + debug("%s: cannot find SCU device, rc=%d\n", __func__, rc); + return; + } + + scu = devfdt_get_addr_ptr(scu_dev); + if (IS_ERR_OR_NULL(scu)) { + debug("%s: cannot get SCU address pointer\n", __func__); + return; + } + + conf = readl(MCR_CONF); + + ecc = conf & MCR_CONF_ECC_EN; + act_size = 0x100 << ((conf & MCR_CONF_MEMSZ_MASK) >> MCR_CONF_MEMSZ_SHIFT); + vga_rsvd = 0x8 << ((conf & MCR_CONF_VGA_MEMSZ_MASK) >> MCR_CONF_VGA_MEMSZ_SHIFT); + + /* no VGA reservation if efuse VGA disable bit is set */ + if (readl(scu->efuse) & SCU_EFUSE_DIS_VGA) + vga_rsvd = 0; + + printf(" (capacity:%d MiB, VGA:%d MiB), ECC %s", act_size, + vga_rsvd, (ecc) ? "on" : "off"); +} + +void enable_caches(void) +{ + /* get rid of the warning message */ +} diff --git a/arch/arm/mach-aspeed/ast2600/lowlevel_init.S b/arch/arm/mach-aspeed/ast2600/lowlevel_init.S new file mode 100644 index 0000000000..594963d039 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2600/lowlevel_init.S @@ -0,0 +1,233 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) ASPEED Technology Inc. + */ +#include <config.h> +#include <asm/armv7.h> +#include <linux/linkage.h> +#include <asm/arch/scu_ast2600.h> + +/* SCU register offsets */ +#define SCU_BASE 0x1e6e2000 +#define SCU_PROT_KEY1 (SCU_BASE + 0x000) +#define SCU_PROT_KEY2 (SCU_BASE + 0x010) +#define SCU_SMP_BOOT (SCU_BASE + 0x180) +#define SCU_HWSTRAP1 (SCU_BASE + 0x510) +#define SCU_CA7_PARITY_CHK (SCU_BASE + 0x820) +#define SCU_CA7_PARITY_CLR (SCU_BASE + 0x824) +#define SCU_MMIO_DEC (SCU_BASE + 0xc24) + +/* FMC SPI register offsets */ +#define FMC_BASE 0x1e620000 +#define FMC_CE0_CTRL (FMC_BASE + 0x010) +#define FMC_SW_RST_CTRL (FMC_BASE + 0x050) +#define FMC_WDT1_CTRL_MODE (FMC_BASE + 0x060) +#define FMC_WDT2_CTRL_MODE (FMC_BASE + 0x064) + +/* + * The SMP mailbox provides a space with few instructions in it + * for secondary cores to execute on and wait for the signal of + * SMP core bring up. + * + * SMP mailbox + * +----------------------+ + * | | + * | mailbox insn. for | + * | cpuN polling SMP go | + * | | + * +----------------------+ 0xC + * | mailbox ready signal | + * +----------------------+ 0x8 + * | cpuN GO signal | + * +----------------------+ 0x4 + * | cpuN entrypoint | + * +----------------------+ SMP_MAILBOX_BASE + */ +#define SMP_MBOX_BASE (SCU_SMP_BOOT) +#define SMP_MBOX_FIELD_ENTRY (SMP_MBOX_BASE + 0x0) +#define SMP_MBOX_FIELD_GOSIGN (SMP_MBOX_BASE + 0x4) +#define SMP_MBOX_FIELD_READY (SMP_MBOX_BASE + 0x8) +#define SMP_MBOX_FIELD_POLLINSN (SMP_MBOX_BASE + 0xc) + +.macro scu_unlock + movw r0, #(SCU_UNLOCK_KEY & 0xffff) + movt r0, #(SCU_UNLOCK_KEY >> 16) + + ldr r1, =SCU_PROT_KEY1 + str r0, [r1] + ldr r1, =SCU_PROT_KEY2 + str r0, [r1] +.endm + +.macro timer_init + ldr r1, =SCU_HWSTRAP1 + ldr r1, [r1] + and r1, #0x700 + lsr r1, #0x8 + + /* 1.2GHz */ + cmp r1, #0x0 + movweq r0, #0x8c00 + movteq r0, #0x4786 + + /* 1.6GHz */ + cmp r1, #0x1 + movweq r0, #0x1000 + movteq r0, #0x5f5e + + /* 1.2GHz */ + cmp r1, #0x2 + movweq r0, #0x8c00 + movteq r0, #0x4786 + + /* 1.6GHz */ + cmp r1, #0x3 + movweq r0, #0x1000 + movteq r0, #0x5f5e + + /* 800MHz */ + cmp r1, #0x4 + movwge r0, #0x0800 + movtge r0, #0x2faf + + mcr p15, 0, r0, c14, c0, 0 @; update CNTFRQ +.endm + + +.globl lowlevel_init + +lowlevel_init: +#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) + mov pc, lr +#else + /* setup ARM arch timer frequency */ + timer_init + + /* reset SMP mailbox as early as possible */ + mov r0, #0x0 + ldr r1, =SMP_MBOX_FIELD_READY + str r0, [r1] + + /* set ACTLR.SMP to enable cache use */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, #0x40 + mcr p15, 0, r0, c1, c0, 1 + + /* + * we treat cpu0 as the primary core and + * put secondary core (cpuN) to sleep + */ + mrc p15, 0, r0, c0, c0, 5 @; Read CPU ID register + ands r0, #0xff @; Mask off, leaving the CPU ID field + movw r2, #0xab00 + movt r2, #0xabba + orr r2, r0 + + beq do_primary_core_setup + + /* hold cpuN until mailbox is ready */ +poll_mailbox_ready: + wfe + ldr r0, =SMP_MBOX_FIELD_READY + ldr r0, [r0] + movw r1, #0xcafe + movt r1, #0xbabe + cmp r1, r0 + bne poll_mailbox_ready + + /* parameters for relocated SMP go polling insn. */ + ldr r0, =SMP_MBOX_FIELD_GOSIGN + ldr r1, =SMP_MBOX_FIELD_ENTRY + + /* no return */ + ldr pc, =SMP_MBOX_FIELD_POLLINSN + +do_primary_core_setup: + scu_unlock + + /* MMIO decode setting */ + ldr r0, =SCU_MMIO_DEC + mov r1, #0x2000 + str r1, [r0] + + /* enable CA7 cache parity check */ + mov r0, #0 + ldr r1, =SCU_CA7_PARITY_CLR + str r0, [r1] + + mov r0, #0x1 + ldr r1, =SCU_CA7_PARITY_CHK + str r0, [r1] + + /* do not fill FMC50[1] if boot from eMMC */ + ldr r0, =SCU_HWSTRAP1 + ldr r1, [r0] + ands r1, #0x04 + bne skip_fill_wip_bit + + /* fill FMC50[1] for waiting WIP idle */ + mov r0, #0x02 + ldr r1, =FMC_SW_RST_CTRL + str r0, [r1] + +skip_fill_wip_bit: + /* disable FMC WDT for SPI address mode detection */ + mov r0, #0 + ldr r1, =FMC_WDT1_CTRL_MODE + str r0, [r1] + + /* relocate mailbox insn. for cpuN polling SMP go signal */ + adrl r0, mailbox_insn + adrl r1, mailbox_insn_end + + ldr r2, =#SMP_MBOX_FIELD_POLLINSN + +relocate_mailbox_insn: + ldr r3, [r0], #0x4 + str r3, [r2], #0x4 + cmp r0, r1 + bne relocate_mailbox_insn + + /* reset SMP go sign */ + mov r0, #0 + ldr r1, =SMP_MBOX_FIELD_GOSIGN + str r0, [r1] + + /* notify cpuN mailbox is ready */ + movw r0, #0xCAFE + movt r0, #0xBABE + ldr r1, =SMP_MBOX_FIELD_READY + str r0, [r1] + sev + + /* back to arch calling code */ + mov pc, lr + +/* + * insn. inside mailbox to poll SMP go signal. + * + * Note that as this code will be relocated, any + * pc-relative assembly should NOT be used. + */ +mailbox_insn: + /* + * r0 ~ r3 are parameters: + * r0 = SMP_MBOX_FIELD_GOSIGN + * r1 = SMP_MBOX_FIELD_ENTRY + * r2 = per-cpu go sign value + * r3 = no used now + */ +poll_mailbox_smp_go: + wfe + ldr r4, [r0] + cmp r2, r4 + bne poll_mailbox_smp_go + + /* SMP GO signal confirmed, release cpuN */ + ldr pc, [r1] + +mailbox_insn_end: + /* should never reach */ + b . + +#endif diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c new file mode 100644 index 0000000000..9201d4a4d4 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <spl.h> +#include <init.h> +#include <asm/io.h> +#include <asm/arch/scu_ast2600.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong dummy) +{ + spl_early_init(); + preloader_console_init(); + timer_init(); + dram_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_RAM; +} + +struct image_header *spl_get_load_buffer(ssize_t offset, size_t size) +{ + /* + * When boot from SPI, AST2600 already remap 0x00000000 ~ 0x0fffffff + * to BMC SPI memory space 0x20000000 ~ 0x2fffffff. The next stage BL + * has been located in SPI for XIP. In this case, the load buffer for + * SPL image loading will be set to the remapped address of the next + * BL instead of the DRAM space CONFIG_SYS_LOAD_ADDR + */ + return (struct image_header *)(CONFIG_SYS_TEXT_BASE); +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* boot linux */ + return 0; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + return 0; +} +#endif diff --git a/board/aspeed/evb_ast2600/Kconfig b/board/aspeed/evb_ast2600/Kconfig new file mode 100644 index 0000000000..42008cd033 --- /dev/null +++ b/board/aspeed/evb_ast2600/Kconfig @@ -0,0 +1,12 @@ +if TARGET_EVB_AST2600 + +config SYS_BOARD + default "evb_ast2600" + +config SYS_VENDOR + default "aspeed" + +config SYS_CONFIG_NAME + default "evb_ast2600" + +endif diff --git a/board/aspeed/evb_ast2600/Makefile b/board/aspeed/evb_ast2600/Makefile new file mode 100644 index 0000000000..9291db6ee1 --- /dev/null +++ b/board/aspeed/evb_ast2600/Makefile @@ -0,0 +1 @@ +obj-y += evb_ast2600.o diff --git a/board/aspeed/evb_ast2600/evb_ast2600.c b/board/aspeed/evb_ast2600/evb_ast2600.c new file mode 100644 index 0000000000..e6dc8c7952 --- /dev/null +++ b/board/aspeed/evb_ast2600/evb_ast2600.c @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#include <common.h> diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c index ee941c7770..d747ed00a7 100644 --- a/drivers/sysreset/sysreset_ast.c +++ b/drivers/sysreset/sysreset_ast.c @@ -12,6 +12,7 @@ #include <asm/io.h> #include <asm/arch/wdt.h> #include <linux/err.h> +#include <hang.h>

static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type) { @@ -33,11 +34,15 @@ static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type) return -EPROTONOSUPPORT; }

+#if !defined(CONFIG_SPL_BUILD) ret = wdt_expire_now(wdt, reset_mode); if (ret) { debug("Sysreset failed: %d", ret); return ret; } +#else + hang(); +#endif

return -EINPROGRESS; } diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h new file mode 100644 index 0000000000..e7975bf66d --- /dev/null +++ b/include/configs/evb_ast2600.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/aspeed-common.h> + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE + +/* Memory Info */ +#define CONFIG_SYS_LOAD_ADDR 0x83000000 + +#endif /* __CONFIG_H */