Re: [U-Boot] dwc2: usb: Unable to clear channel error
On 10/23/2017 09:03 AM, Minas Harutyunyan wrote:
On 10/19/2017 5:35 PM, Dinh Nguyen wrote:
On 10/19/2017 06:55 AM, Grigor Tovmasyan wrote:
On 10/18/2017 6:07 PM, Marek Vasut wrote:
On 10/18/2017 04:05 PM, Dinh Nguyen wrote:
Hi,
I'm trying to bringup the DWC2 USB IP version 330A on a new Stratix10 SoC and have encountered this error in both Linux and U-Boot:
U-Boot(version v2017.09)
# usb start starting USB... USB0: Core Release: 3.30a dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout!
Linux(kernel v4.13)
[ 1.299891] dwc2 ffb00000.usb: DWC OTG Controller [ 1.304628] dwc2 ffb00000.usb: new USB bus registered, assigned bus number 1 [ 1.311698] dwc2 ffb00000.usb: irq 13, io mem 0xffb00000 [ 1.318309] dwc2 ffb00000.usb: Unable to clear enable on channel 0 [ 1.325749] dwc2 ffb00000.usb: Unable to clear enable on channel 1 [ 1.333187] dwc2 ffb00000.usb: Unable to clear enable on channel 2 [ 1.340626] dwc2 ffb00000.usb: Unable to clear enable on channel 3 [ 1.348064] dwc2 ffb00000.usb: Unable to clear enable on channel 4 [ 1.355503] dwc2 ffb00000.usb: Unable to clear enable on channel 5 [ 1.362941] dwc2 ffb00000.usb: Unable to clear enable on channel 6 [ 1.370379] dwc2 ffb00000.usb: Unable to clear enable on channel 7 [ 1.377818] dwc2 ffb00000.usb: Unable to clear enable on channel 8 [ 1.385256] dwc2 ffb00000.usb: Unable to clear enable on channel 9 [ 1.392694] dwc2 ffb00000.usb: Unable to clear enable on channel 10 [ 1.400218] dwc2 ffb00000.usb: Unable to clear enable on channel 11 [ 1.407743] dwc2 ffb00000.usb: Unable to clear enable on channel 12 [ 1.415269] dwc2 ffb00000.usb: Unable to clear enable on channel 13 [ 1.422794] dwc2 ffb00000.usb: Unable to clear enable on channel 14
Just wondering if anyone might have an idea on what could be causing this error?
Maybe some clock are not enabled ?
Hi ,
Are you following board/hisilicon/hikey/README file instructions when using U-Boot? Specially paragraph FLASHING point 4, where discussed "dwc_otg_core_host_init: Timeout!" message.
I saw that, but I don't know how that applies to a Stratix10 platform?
Dinh
Hi,
Did you able to resolve this issue? If not, please provide verbose debug log and register dump.
I double-checked the clocks and it looks like all of the necessary clocks are enabled. Here are the log and register dump for U-Boot, I'll follow-up with the Linux log shortly.
For U-Boot:
SOCFPGA_STRATIX10 # usb start starting USB... USB0: Core Release: 3.30a dwc_otg_core_host_init: Timeout (reg=00000000ffb00500 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00520 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00540 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00560 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00580 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb005a0 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb005c0 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb005e0 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00600 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00620 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00640 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00660 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00680 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb006a0 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb006c0 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! scanning bus 0 for devices... dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa4f440, udev->dev='usb_hub', portnr=1 chunk_msg: msg: pipe 80000083 pid 3 in 0 len 8 transfer_chunk: chunk: pid 3 xfer_len 8 pkts 1 wait_for_chhltd: Timeout (reg=00000000ffb00508 mask=00000002 wait_set=1) unable to get device descriptor (error=-110) dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found SOCFPGA_STRATIX10
Before "usb start", the registers are:
ffb00000: 00200000 00000000 00000000 00001410 .. ............. ffb00010: 80000000 04000021 00000000 00000000 ....!........... ffb00020: 00000000 00002000 20002000 00082000 ..... ... . . .. ffb00030: 00000000 00000000 00000000 12345678 ............xV4. ffb00040: 4f54330a 00000000 238ffc90 1f8002e8 .3TO.......#.... ffb00050: fe0f0020 00000000 00000000 1f802000 ............ .. ffb00060: 00000000 00000000 00000000 00000000 ................ ffb00070: 00000000 00000000 00000000 00000000 ................ ffb00080: 00000000 00000000 00000000 00000000 ................ ffb00090: 00000000 00000000 00000000 00000000 ................ ffb000a0: 00000000 00000000 00000000 00000000 ................ ffb000b0: 00000000 00000000 00000000 00000000 ................ ffb000c0: 00000000 00000000 00000000 00000000 ................ ffb000d0: 00000000 00000000 00000000 00000000 ................ ffb000e0: 00000000 00000000 00000000 00000000 ................ ffb000f0: 00000000 00000000 00000000 00000000 ................ ffb00100: 20004000 00000000 00000000 00000000 .@. ............ ffb00110: 00000000 00000000 00000000 00000000 ................ ffb00120: 00000000 00000000 00000000 00000000 ................ ffb00130: 00000000 00000000 00000000 00000000 ................ ffb00140: 00000000 00000000 00000000 00000000 ................ ffb00150: 00000000 00000000 00000000 00000000 ................ ffb00160: 00000000 00000000 00000000 00000000 ................ ffb00170: 00000000 00000000 00000000 00000000 ................ ffb00180: 00000000 00000000 00000000 00000000 ................
ffb00500: 00000000 00000000 00000000 00000000 ................ ffb00510: 00000000 ffffff7f 00000000 ffffff7f ................ ffb00520: 00000000 00000000 00000000 00000000 ................ ffb00530: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00540: 00000000 00000000 00000000 00000000 ................ ffb00550: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00560: 00000000 00000000 00000000 00000000 ................ ffb00570: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00580: 00000000 00000000 00000000 00000000 ................ ffb00590: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb005a0: 00000000 00000000 00000000 00000000 ................ ffb005b0: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb005c0: 00000000 00000000 00000000 00000000 ................ ffb005d0: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb005e0: 00000000 00000000 00000000 00000000 ................ ffb005f0: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00600: 00000000 00000000 00000000 00000000 ................ ffb00610: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00620: 00000000 00000000 00000000 00000000 ................ ffb00630: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00640: 00000000 00000000 00000000 00000000 ................ ffb00650: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00660: 00000000 00000000 00000000 00000000 ................ ffb00670: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00680: 00000000 00000000 00000000 00000000 ................
After "usb start":
# md.l 0xffb00000 64 ffb00000: 002e0000 00080000 00000026 01301710 ........&.....0. ffb00010: 80000000 3500002d 00000000 ffffff7f ....-..5........ ffb00020: ffffff7f 00000214 01000214 47080100 ...............G ffb00030: 00000000 00000000 00000000 12345678 ............xV4. ffb00040: 4f54330a 00000000 238ffc90 1f8002e8 .3TO.......#.... ffb00050: fe0f0020 00000000 00000000 1f802000 ............ .. ffb00060: 00000000 00000000 00000000 00000000 ................ ffb00070: 00000000 00000000 00000000 00000000 ................ ffb00080: 00000000 00000000 00000000 00000000 ................ ffb00090: 00000000 00000000 00000000 00000000 ................ ffb000a0: 00000000 00000000 00000000 00000000 ................ ffb000b0: 00000000 00000000 00000000 00000000 ................ ffb000c0: 00000000 00000000 00000000 00000000 ................ ffb000d0: 00000000 00000000 00000000 00000000 ................ ffb000e0: 00000000 00000000 00000000 00000000 ................ ffb000f0: 00000000 00000000 00000000 00000000 ................ ffb00100: 02000314 00000000 00000000 00000000 ................ ffb00110: 00000000 00000000 00000000 00000000 ................ ffb00120: 00000000 00000000 00000000 00000000 ................ ffb00130: 00000000 00000000 00000000 00000000 ................ ffb00140: 00000000 00000000 00000000 00000000 ................ ffb00150: 00000000 00000000 00000000 00000000 ................ ffb00160: 00000000 00000000 00000000 00000000 ................ ffb00170: 00000000 00000000 00000000 00000000 ................ ffb00180: 00000000 00000000 00000000 00000000 ................
# md.l 0xffb00500 64 ffb00500: c0100040 00000000 00000000 00000000 @............... ffb00510: 60080008 ffffff7f 00000000 ffffff7f ...`............ ffb00520: c0000000 00000000 00000000 00000000 ................ ffb00530: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00540: c0000000 00000000 00000000 00000000 ................ ffb00550: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00560: c0000000 00000000 00000000 00000000 ................ ffb00570: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00580: c0000000 00000000 00000000 00000000 ................ ffb00590: 00000000 ffffff7f 00000100 ffffff7f ................ ffb005a0: c0000000 00000000 00000000 00000000 ................ ffb005b0: 00000000 ffffff7f 00000100 ffffff7f ................ ffb005c0: c0000000 00000000 00000000 00000000 ................ ffb005d0: 00000000 ffffff7f 00000100 ffffff7f ................ ffb005e0: c0000000 00000000 00000000 00000000 ................ ffb005f0: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00600: c0000000 00000000 00000000 00000000 ................ ffb00610: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00620: c0000000 00000000 00000000 00000000 ................ ffb00630: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00640: c0000000 00000000 00000000 00000000 ................ ffb00650: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00660: c0000000 00000000 00000000 00000000 ................ ffb00670: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00680: c0000000 00000000 00000000 00000000 ................
I'll follow up the the Linux debug output shortly.
Dinh
On 10/24/2017 3:23 AM, Dinh Nguyen wrote:
On 10/23/2017 09:03 AM, Minas Harutyunyan wrote:
On 10/19/2017 5:35 PM, Dinh Nguyen wrote:
On 10/19/2017 06:55 AM, Grigor Tovmasyan wrote:
On 10/18/2017 6:07 PM, Marek Vasut wrote:
On 10/18/2017 04:05 PM, Dinh Nguyen wrote:
Hi,
I'm trying to bringup the DWC2 USB IP version 330A on a new Stratix10 SoC and have encountered this error in both Linux and U-Boot:
U-Boot(version v2017.09)
# usb start starting USB... USB0: Core Release: 3.30a dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout!
Linux(kernel v4.13)
[ 1.299891] dwc2 ffb00000.usb: DWC OTG Controller [ 1.304628] dwc2 ffb00000.usb: new USB bus registered, assigned bus number 1 [ 1.311698] dwc2 ffb00000.usb: irq 13, io mem 0xffb00000 [ 1.318309] dwc2 ffb00000.usb: Unable to clear enable on channel 0 [ 1.325749] dwc2 ffb00000.usb: Unable to clear enable on channel 1 [ 1.333187] dwc2 ffb00000.usb: Unable to clear enable on channel 2 [ 1.340626] dwc2 ffb00000.usb: Unable to clear enable on channel 3 [ 1.348064] dwc2 ffb00000.usb: Unable to clear enable on channel 4 [ 1.355503] dwc2 ffb00000.usb: Unable to clear enable on channel 5 [ 1.362941] dwc2 ffb00000.usb: Unable to clear enable on channel 6 [ 1.370379] dwc2 ffb00000.usb: Unable to clear enable on channel 7 [ 1.377818] dwc2 ffb00000.usb: Unable to clear enable on channel 8 [ 1.385256] dwc2 ffb00000.usb: Unable to clear enable on channel 9 [ 1.392694] dwc2 ffb00000.usb: Unable to clear enable on channel 10 [ 1.400218] dwc2 ffb00000.usb: Unable to clear enable on channel 11 [ 1.407743] dwc2 ffb00000.usb: Unable to clear enable on channel 12 [ 1.415269] dwc2 ffb00000.usb: Unable to clear enable on channel 13 [ 1.422794] dwc2 ffb00000.usb: Unable to clear enable on channel 14
Just wondering if anyone might have an idea on what could be causing this error?
Maybe some clock are not enabled ?
Hi ,
Are you following board/hisilicon/hikey/README file instructions when using U-Boot? Specially paragraph FLASHING point 4, where discussed "dwc_otg_core_host_init: Timeout!" message.
I saw that, but I don't know how that applies to a Stratix10 platform?
Dinh
Hi,
Did you able to resolve this issue? If not, please provide verbose debug log and register dump.
I double-checked the clocks and it looks like all of the necessary clocks are enabled. Here are the log and register dump for U-Boot, I'll follow-up with the Linux log shortly.
For U-Boot:
SOCFPGA_STRATIX10 # usb start starting USB... USB0: Core Release: 3.30a dwc_otg_core_host_init: Timeout (reg=00000000ffb00500 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00520 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00540 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00560 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00580 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb005a0 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb005c0 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb005e0 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00600 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00620 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00640 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00660 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb00680 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb006a0 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! dwc_otg_core_host_init: Timeout (reg=00000000ffb006c0 mask=80000000 wait_set=0) dwc_otg_core_host_init: Timeout! scanning bus 0 for devices... dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa50380, udev->dev='usb@ffb00000', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa4f440, udev->dev='usb_hub', portnr=1 chunk_msg: msg: pipe 80000083 pid 3 in 0 len 8 transfer_chunk: chunk: pid 3 xfer_len 8 pkts 1 wait_for_chhltd: Timeout (reg=00000000ffb00508 mask=00000002 wait_set=1) unable to get device descriptor (error=-110) dwc2_submit_control_msg: dev='usb@ffb00000', udev=000000003fa55080, udev->dev='usb_hub', portnr=0 1 USB Device(s) found scanning usb for storage devices... 0 Storage Device(s) found SOCFPGA_STRATIX10
Before "usb start", the registers are:
ffb00000: 00200000 00000000 00000000 00001410 .. ............. ffb00010: 80000000 04000021 00000000 00000000 ....!........... ffb00020: 00000000 00002000 20002000 00082000 ..... ... . . .. ffb00030: 00000000 00000000 00000000 12345678 ............xV4. ffb00040: 4f54330a 00000000 238ffc90 1f8002e8 .3TO.......#.... ffb00050: fe0f0020 00000000 00000000 1f802000 ............ .. ffb00060: 00000000 00000000 00000000 00000000 ................ ffb00070: 00000000 00000000 00000000 00000000 ................ ffb00080: 00000000 00000000 00000000 00000000 ................ ffb00090: 00000000 00000000 00000000 00000000 ................ ffb000a0: 00000000 00000000 00000000 00000000 ................ ffb000b0: 00000000 00000000 00000000 00000000 ................ ffb000c0: 00000000 00000000 00000000 00000000 ................ ffb000d0: 00000000 00000000 00000000 00000000 ................ ffb000e0: 00000000 00000000 00000000 00000000 ................ ffb000f0: 00000000 00000000 00000000 00000000 ................ ffb00100: 20004000 00000000 00000000 00000000 .@. ............ ffb00110: 00000000 00000000 00000000 00000000 ................ ffb00120: 00000000 00000000 00000000 00000000 ................ ffb00130: 00000000 00000000 00000000 00000000 ................ ffb00140: 00000000 00000000 00000000 00000000 ................ ffb00150: 00000000 00000000 00000000 00000000 ................ ffb00160: 00000000 00000000 00000000 00000000 ................ ffb00170: 00000000 00000000 00000000 00000000 ................ ffb00180: 00000000 00000000 00000000 00000000 ................
ffb00500: 00000000 00000000 00000000 00000000 ................ ffb00510: 00000000 ffffff7f 00000000 ffffff7f ................ ffb00520: 00000000 00000000 00000000 00000000 ................ ffb00530: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00540: 00000000 00000000 00000000 00000000 ................ ffb00550: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00560: 00000000 00000000 00000000 00000000 ................ ffb00570: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00580: 00000000 00000000 00000000 00000000 ................ ffb00590: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb005a0: 00000000 00000000 00000000 00000000 ................ ffb005b0: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb005c0: 00000000 00000000 00000000 00000000 ................ ffb005d0: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb005e0: 00000000 00000000 00000000 00000000 ................ ffb005f0: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00600: 00000000 00000000 00000000 00000000 ................ ffb00610: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00620: 00000000 00000000 00000000 00000000 ................ ffb00630: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00640: 00000000 00000000 00000000 00000000 ................ ffb00650: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00660: 00000000 00000000 00000000 00000000 ................ ffb00670: 00000000 ffffff7f 00002000 ffffff7f ......... ...... ffb00680: 00000000 00000000 00000000 00000000 ................
After "usb start":
# md.l 0xffb00000 64 ffb00000: 002e0000 00080000 00000026 01301710 ........&.....0. ffb00010: 80000000 3500002d 00000000 ffffff7f ....-..5........ ffb00020: ffffff7f 00000214 01000214 47080100 ...............G ffb00030: 00000000 00000000 00000000 12345678 ............xV4. ffb00040: 4f54330a 00000000 238ffc90 1f8002e8 .3TO.......#.... ffb00050: fe0f0020 00000000 00000000 1f802000 ............ .. ffb00060: 00000000 00000000 00000000 00000000 ................ ffb00070: 00000000 00000000 00000000 00000000 ................ ffb00080: 00000000 00000000 00000000 00000000 ................ ffb00090: 00000000 00000000 00000000 00000000 ................ ffb000a0: 00000000 00000000 00000000 00000000 ................ ffb000b0: 00000000 00000000 00000000 00000000 ................ ffb000c0: 00000000 00000000 00000000 00000000 ................ ffb000d0: 00000000 00000000 00000000 00000000 ................ ffb000e0: 00000000 00000000 00000000 00000000 ................ ffb000f0: 00000000 00000000 00000000 00000000 ................ ffb00100: 02000314 00000000 00000000 00000000 ................ ffb00110: 00000000 00000000 00000000 00000000 ................ ffb00120: 00000000 00000000 00000000 00000000 ................ ffb00130: 00000000 00000000 00000000 00000000 ................ ffb00140: 00000000 00000000 00000000 00000000 ................ ffb00150: 00000000 00000000 00000000 00000000 ................ ffb00160: 00000000 00000000 00000000 00000000 ................ ffb00170: 00000000 00000000 00000000 00000000 ................ ffb00180: 00000000 00000000 00000000 00000000 ................
# md.l 0xffb00500 64 ffb00500: c0100040 00000000 00000000 00000000 @............... ffb00510: 60080008 ffffff7f 00000000 ffffff7f ...`............ ffb00520: c0000000 00000000 00000000 00000000 ................ ffb00530: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00540: c0000000 00000000 00000000 00000000 ................ ffb00550: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00560: c0000000 00000000 00000000 00000000 ................ ffb00570: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00580: c0000000 00000000 00000000 00000000 ................ ffb00590: 00000000 ffffff7f 00000100 ffffff7f ................ ffb005a0: c0000000 00000000 00000000 00000000 ................ ffb005b0: 00000000 ffffff7f 00000100 ffffff7f ................ ffb005c0: c0000000 00000000 00000000 00000000 ................ ffb005d0: 00000000 ffffff7f 00000100 ffffff7f ................ ffb005e0: c0000000 00000000 00000000 00000000 ................ ffb005f0: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00600: c0000000 00000000 00000000 00000000 ................ ffb00610: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00620: c0000000 00000000 00000000 00000000 ................ ffb00630: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00640: c0000000 00000000 00000000 00000000 ................ ffb00650: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00660: c0000000 00000000 00000000 00000000 ................ ffb00670: 00000000 ffffff7f 00000100 ffffff7f ................ ffb00680: c0000000 00000000 00000000 00000000 ................
I'll follow up the the Linux debug output shortly.
Dinh
Hi, Can you please apply this patch to Linux kernel driver and check if it help you overcome issue.
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index f4ef159b538e..e8e7db216b64 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -2384,10 +2384,12 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) num_channels = hsotg->params.host_channels; for (i = 0; i < num_channels; i++) { hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); - hcchar &= ~HCCHAR_CHENA; - hcchar |= HCCHAR_CHDIS; - hcchar &= ~HCCHAR_EPDIR; - dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + if (hcchar & HCCHAR_CHENA) { + hcchar &= ~HCCHAR_CHENA; + hcchar |= HCCHAR_CHDIS; + hcchar &= ~HCCHAR_EPDIR; + dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } }
/* Halt all channels to put them into a known state */ @@ -2395,21 +2397,24 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) int count = 0;
hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); - hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; - hcchar &= ~HCCHAR_EPDIR; - dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); - dev_dbg(hsotg->dev, "%s: Halt channel %d\n", - __func__, i); - do { - hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); - if (++count > 1000) { - dev_err(hsotg->dev, - "Unable to clear enable on channel %d\n", - i); - break; - } - udelay(1); - } while (hcchar & HCCHAR_CHENA); + if (hcchar & HCCHAR_CHENA) { + hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; + hcchar &= ~HCCHAR_EPDIR; + dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + dev_dbg(hsotg->dev, "%s: Halt channel %d\n", + __func__, i); + do { + hcchar = dwc2_readl(hsotg->regs + + HCCHAR(i)); + if (++count > 1000) { + dev_err(hsotg->dev, + "Unable to clear enable on channel %d\n", + i); + break; + } + udelay(1); + } while (hcchar & HCCHAR_CHENA); + } } }
Thanks, Minas
participants (2)
-
Dinh Nguyen -
Minas Harutyunyan