[PATCH v2] mtd: spi-nor: Disable chip erase for S28HS02GT flash
From: Tejas Bhumkar tejas.arvind.bhumkar@amd.com
Since the opcode SPINOR_OP_CHIP_ERASE (0xc7) is not supported for the S28HS02GT flash, the NO_CHIP_ERASE flag has been added to enable sector erase functionality instead.
Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com Signed-off-by: Prasad Kummari prasad.kummari@amd.com --- Changes in v2: - corrected commit subject.
drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 0908fb954e..1b737a3507 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -383,7 +383,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) }, { INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, { INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) }, - { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ | SPI_NOR_MULTI_DIE) }, + { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ | SPI_NOR_MULTI_DIE | NO_CHIP_ERASE) }, #endif #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */
Hello,
On 7/30/2024 9:05 PM, Prasad Kummari wrote:
From: Tejas Bhumkar tejas.arvind.bhumkar@amd.com
Since the opcode SPINOR_OP_CHIP_ERASE (0xc7) is not supported for the S28HS02GT flash, the NO_CHIP_ERASE flag has been added to enable sector erase functionality instead.
Signed-off-by: Tejas Bhumkar tejas.arvind.bhumkar@amd.com Signed-off-by: Prasad Kummari prasad.kummari@amd.com
Changes in v2:
- corrected commit subject.
drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 0908fb954e..1b737a3507 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -383,7 +383,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s28hl01gt", 0x345a1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) }, { INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, { INFO("s28hs01gt", 0x345b1b, 0, 256 * 1024, 512, SPI_NOR_OCTAL_DTR_READ) },
- { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ | SPI_NOR_MULTI_DIE) },
- { INFO("s28hs02gt", 0x345b1c, 0, 256 * 1024, 1024, SPI_NOR_OCTAL_DTR_READ | SPI_NOR_MULTI_DIE | NO_CHIP_ERASE) },
The 'SPI_NOR_MULTI_DIE' is not defined in mainline u-boot. I have submitted another patch: https://patchwork.ozlabs.org/project/uboot/patch/20240830000537.18862-1-Taka...
Thanks, Takahiro Kuwano
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Prasad Kummari -
Takahiro Kuwano