[PATCH v4 0/7] Add SE HMBSC board support
SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major difference from db410c is serial port where HMIBSC board uses UART1 as the debug console with an RS232 port, patch #2 - #5 adds corresponding driver support.
Patch #6 adds main HMIBSC board specific bits, features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 2GiB RAM - 64GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI
Features enabled in U-Boot: - RAUC updates (refer [2] for more details) - Environment protection - USB based ethernet adaptors
Feedback is very much welcome.
Changes in v4: - Rebased on top of qcom-main [4]. - Split out board DTS patch as #6. - Convert to text based environment as hmibsc.env. - MMC regression has been reported for qcom-main branch here [5]. - Collected further review tag.
Changes in v3: - Rebased on top of qcom-next [1]. - Collected some review tags. - Incorporated misc. comments from Caleb and Stephen. - Split patch#4 as requested. - Linux HMIBSC board DTS has already been reviewed here [3], I have incorporated that for U-Boot too.
Changes in v2: - Rebased on top on qcom-next [1]. - Added patch#1 as a fix for generic qcom board support. - Added patch#4 to enable driving GPIO pins based on pinctrl configuration. This replaces the custom GPIO configuration. - Added proper DTS file for HMIBSC board based on Linux DT pattern. - Merged board support patches into a single patch#5.
[1] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-ne... [2] https://rauc.readthedocs.io/en/latest/ [3] https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.garg@lin... [4] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-ma... [5] https://lore.kernel.org/all/CAFA6WYO+3VroUdFUVH390taViQX8pMQrOQDTSn0yU6BD5YY...
Sumit Garg (7): qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default apq8016: Add support for UART1 clocks and pinmux serial_msm: Enable RS232 flow control pinctrl: qcom: Add support for driving GPIO pins output pinctrl: qcom: apq8016: Add GPIO pinctrl function arm: dts: qcom: Add Schneider HMIBSC board dts board: add support for Schneider HMIBSC board
arch/arm/Kconfig | 2 +- arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++++++++++++++++++++++ board/schneider/hmibsc/MAINTAINERS | 6 + board/schneider/hmibsc/hmibsc.env | 40 ++ configs/hmibsc_defconfig | 87 ++++ doc/board/index.rst | 1 + doc/board/schneider/hmibsc.rst | 45 ++ doc/board/schneider/index.rst | 9 + drivers/clk/qcom/clock-apq8016.c | 38 +- drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 + drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +- drivers/serial/serial_msm.c | 24 +- include/configs/hmibsc.h | 16 + 13 files changed, 760 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 board/schneider/hmibsc/hmibsc.env create mode 100644 configs/hmibsc_defconfig create mode 100644 doc/board/schneider/hmibsc.rst create mode 100644 doc/board/schneider/index.rst create mode 100644 include/configs/hmibsc.h
Enabling LINUX_KERNEL_IMAGE_HEADER by default doesn't allow ENABLE_ARM_SOC_BOOT0_HOOK to work properly on db410c when U-Boot is loaded as a first stage bootloader. It leads to secondary CPUs bringup failure and later causing the Linux kernel to freeze.
So fix it via selectively enabling LINUX_KERNEL_IMAGE_HEADER where it's actually required.
Fixes: 059d526af312 ("mach-snapdragon: generalise board support") Reviewed-by: Caleb Connolly caleb.connolly@linaro.org Signed-off-by: Sumit Garg sumit.garg@linaro.org --- arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 23ee25269a2..1d451c46d32 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1088,7 +1088,7 @@ config ARCH_SNAPDRAGON select BOARD_LATE_INIT select OF_BOARD select SAVE_PREV_BL_FDT_ADDR - select LINUX_KERNEL_IMAGE_HEADER + select LINUX_KERNEL_IMAGE_HEADER if !ENABLE_ARM_SOC_BOOT0_HOOK imply CMD_DM
config ARCH_SOCFPGA
SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks and pinmux support. Along with that update instructions to enable clocks for debug UART support.
Reviewed-by: Caleb Connolly caleb.connolly@linaro.org Signed-off-by: Sumit Garg sumit.garg@linaro.org --- drivers/clk/qcom/clock-apq8016.c | 38 ++++++++++++++++++-------- drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 + drivers/serial/serial_msm.c | 11 ++++++-- 3 files changed, 35 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index 5a5868169c8..9556b94774a 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -31,7 +31,8 @@ #define BLSP1_AHB_CBCR 0x1008
/* Uart clock control registers */ -#define BLSP1_UART2_BCR (0x3028) +#define BLSP1_UART1_APPS_CBCR (0x203C) +#define BLSP1_UART1_APPS_CMD_RCGR (0x2044) #define BLSP1_UART2_APPS_CBCR (0x302C) #define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
@@ -52,7 +53,7 @@ static struct vote_clk gcc_blsp1_ahb_clk = { };
/* SDHCI */ -static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) +static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) { int div = 15; /* 100MHz default */
@@ -70,20 +71,35 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) }
/* UART: 115200 */ -int apq8016_clk_init_uart(phys_addr_t base) +int apq8016_clk_init_uart(phys_addr_t base, unsigned long id) { + u32 cmd_rcgr, apps_cbcr; + + switch (id) { + case GCC_BLSP1_UART1_APPS_CLK: + cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR; + apps_cbcr = BLSP1_UART1_APPS_CBCR; + break; + case GCC_BLSP1_UART2_APPS_CLK: + cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR; + apps_cbcr = BLSP1_UART2_APPS_CBCR; + break; + default: + return 0; + } + /* Enable AHB clock */ clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk);
/* 7372800 uart block clock @ GPLL0 */ - clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625, - CFG_CLK_SRC_GPLL0, 16); + clk_rcg_set_rate_mnd(base, cmd_rcgr, 1, 144, 15625, CFG_CLK_SRC_GPLL0, + 16);
/* Vote for gpll0 clock */ clk_enable_gpll0(base, &gpll0_vote_clk);
/* Enable core clk */ - clk_enable_cbc(base + BLSP1_UART2_APPS_CBCR); + clk_enable_cbc(base + apps_cbcr);
return 0; } @@ -94,14 +110,12 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)
switch (clk->id) { case GCC_SDCC1_APPS_CLK: /* SDC1 */ - return clk_init_sdc(priv, 0, rate); - break; + return apq8016_clk_init_sdc(priv, 0, rate); case GCC_SDCC2_APPS_CLK: /* SDC2 */ - return clk_init_sdc(priv, 1, rate); - break; + return apq8016_clk_init_sdc(priv, 1, rate); + case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */ case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ - return apq8016_clk_init_uart(priv->base); - break; + return apq8016_clk_init_uart(priv->base, clk->id); default: return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index a9a00f4b081..1ee8b7db1a2 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = { };
static const struct pinctrl_function msm_pinctrl_functions[] = { + {"blsp_uart1", 2}, {"blsp_uart2", 2}, };
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index ac4280c6c4c..4de10e75191 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -248,12 +248,17 @@ static struct msm_serial_data init_serial_data = { #include <debug_uart.h>
/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ -//int apq8016_clk_init_uart(phys_addr_t gcc_base); +//int apq8016_clk_init_uart(phys_addr_t gcc_base, unsigned long id);
static inline void _debug_uart_init(void) { - /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ - //apq8016_clk_init_uart(0x1800000); + /* + * Uncomment to turn on UART clocks when debugging U-Boot as aboot + * on MSM8916. Supported debug UART clock IDs: + * - db410c: GCC_BLSP1_UART2_APPS_CLK + * - HMIBSC: GCC_BLSP1_UART1_APPS_CLK + */ + //apq8016_clk_init_uart(0x1800000, <uart_clk_id>); uart_dm_init(&init_serial_data); }
SE HMIBSC board debug console requires RS232 flow control, so enable corresponding support if RS232 gpios are present.
Reviewed-by: Caleb Connolly caleb.connolly@linaro.org Signed-off-by: Sumit Garg sumit.garg@linaro.org --- drivers/serial/serial_msm.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 4de10e75191..3142ecf7362 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -53,10 +53,11 @@ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */
-#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC -#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 -#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 -#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC +#define MSM_BOOT_UART_DM_8_N_1_MODE 0x34 +#define MSM_BOOT_UART_DM_CMD_RESET_RX 0x10 +#define MSM_BOOT_UART_DM_CMD_RESET_TX 0x20 +#define MSM_UART_MR1_RX_RDY_CTL BIT(7)
DECLARE_GLOBAL_DATA_PTR;
@@ -182,7 +183,9 @@ static void uart_dm_init(struct msm_serial_data *priv) mdelay(5);
writel(priv->clk_bit_rate, priv->base + UARTDM_CSR); - writel(0x0, priv->base + UARTDM_MR1); + + /* Enable RS232 flow control to support RS232 db9 connector */ + writel(MSM_UART_MR1_RX_RDY_CTL, priv->base + UARTDM_MR1); writel(MSM_BOOT_UART_DM_8_N_1_MODE, priv->base + UARTDM_MR2); writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR);
Add support for driving the GPIO pins as output low or high.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- drivers/pinctrl/qcom/pinctrl-qcom.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 909e566acf5..e68971b37ff 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -29,15 +29,24 @@ struct msm_pinctrl_priv { #define GPIO_CONFIG_REG(priv, x) \ (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
-#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_DISABLE BIT(9) +#define GPIO_IN_OUT_REG(priv, x) \ + (GPIO_CONFIG_REG(priv, x) + 0x4) + +#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_OUTPUT_MASK BIT(1) +#define TLMM_GPIO_OE_MASK BIT(9) + +/* GPIO register shifts. */ +#define GPIO_OUT_SHIFT 1
static const struct pinconf_param msm_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 }, + { "output-high", PIN_CONFIG_OUTPUT, 1, }, + { "output-low", PIN_CONFIG_OUTPUT, 0, }, };
static int msm_get_functions_count(struct udevice *dev) @@ -90,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, return 0;
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), - TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2); + TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, func << 2); return 0; }
@@ -117,6 +126,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_GPIO_PULL_MASK, argument); break; + case PIN_CONFIG_OUTPUT: + writel(argument << GPIO_OUT_SHIFT, + priv->base + GPIO_IN_OUT_REG(priv, pin_selector)); + setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), + TLMM_GPIO_OE_MASK); + break; default: return 0; }
On 12/04/2024 11:54, Sumit Garg wrote:
Add support for driving the GPIO pins as output low or high.
Signed-off-by: Sumit Garg sumit.garg@linaro.org
drivers/pinctrl/qcom/pinctrl-qcom.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index 909e566acf5..e68971b37ff 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -29,15 +29,24 @@ struct msm_pinctrl_priv { #define GPIO_CONFIG_REG(priv, x) \ (qcom_pin_offset((priv)->data->pin_data.pin_offsets, x))
-#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) -#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) -#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) -#define TLMM_GPIO_DISABLE BIT(9) +#define GPIO_IN_OUT_REG(priv, x) \
- (GPIO_CONFIG_REG(priv, x) + 0x4)
+#define TLMM_GPIO_PULL_MASK GENMASK(1, 0) +#define TLMM_FUNC_SEL_MASK GENMASK(5, 2) +#define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6) +#define TLMM_GPIO_OUTPUT_MASK BIT(1) +#define TLMM_GPIO_OE_MASK BIT(9)
+/* GPIO register shifts. */ +#define GPIO_OUT_SHIFT 1
static const struct pinconf_param msm_conf_params[] = { { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 }, { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
{ "output-high", PIN_CONFIG_OUTPUT, 1, },
{ "output-low", PIN_CONFIG_OUTPUT, 0, }, };
static int msm_get_functions_count(struct udevice *dev)
@@ -90,7 +99,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, return 0;
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, func << 2);
TLMM_FUNC_SEL_MASK | TLMM_GPIO_OE_MASK, func << 2);@@ -117,6 +126,12 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_GPIO_PULL_MASK, argument); break;
- case PIN_CONFIG_OUTPUT:
writel(argument << GPIO_OUT_SHIFT,priv->base + GPIO_IN_OUT_REG(priv, pin_selector));setbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),TLMM_GPIO_OE_MASK);break;
Reviewed-by: Neil Armstrong neil.armstrong@linaro.org
Add GPIO pinctrl function to enable driving GPIO pins as output low or high.
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index 1ee8b7db1a2..b14a8921af4 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -29,6 +29,7 @@ static const char * const msm_pinctrl_pins[] = { };
static const struct pinctrl_function msm_pinctrl_functions[] = { + {"gpio", 0}, {"blsp_uart1", 2}, {"blsp_uart2", 2}, };
Schneider HMIBSC board dts has already been reviewed upstream on the linux-arm-msm mailing list. So once it comes through the Linux kernel release cycle into the U-Boot dts/upstream subtree, a switch to OF_UPSTREAM can be made. For the time being maintain the U-Boot copy.
Link: https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.garg@lin... Signed-off-by: Sumit Garg sumit.garg@linaro.org --- arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++++++++++++++++++++++ 1 file changed, 491 insertions(+) create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts
diff --git a/arch/arm/dts/apq8016-schneider-hmibsc.dts b/arch/arm/dts/apq8016-schneider-hmibsc.dts new file mode 100644 index 00000000000..75c6137e5a1 --- /dev/null +++ b/arch/arm/dts/apq8016-schneider-hmibsc.dts @@ -0,0 +1,491 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Linaro Ltd. + */ + +/dts-v1/; + +#include "msm8916-pm8916.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> +#include <dt-bindings/pinctrl/qcom,pmic-mpp.h> +#include <dt-bindings/sound/apq8016-lpass.h> + +/ { + model = "Schneider Electric HMIBSC Board"; + compatible = "schneider,apq8016-hmibsc", "qcom,apq8016"; + + aliases { + i2c1 = &blsp_i2c6; + i2c3 = &blsp_i2c4; + i2c4 = &blsp_i2c3; + mmc0 = &sdhc_1; /* eMMC */ + mmc1 = &sdhc_2; /* SD card */ + serial0 = &blsp_uart1; + serial1 = &blsp_uart2; + spi0 = &blsp_spi5; + usid0 = &pm8916_0; + }; + + chosen { + stdout-path = "serial0"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-0 = <&msm_key_volp_n_default>; + pinctrl-names = "default"; + + button { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pm8916_mpps_leds>; + pinctrl-names = "default"; + + led-1 { + function = LED_FUNCTION_WLAN; + color = <LED_COLOR_ID_YELLOW>; + gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + led-2 { + function = LED_FUNCTION_BLUETOOTH; + color = <LED_COLOR_ID_BLUE>; + gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "bluetooth-power"; + default-state = "off"; + }; + }; + + memory@80000000 { + reg = <0 0x80000000 0 0x40000000>; + }; + + reserved-memory { + ramoops@bff00000 { + compatible = "ramoops"; + reg = <0x0 0xbff00000 0x0 0x100000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x20000>; + ecc-size = <16>; + }; + }; + + usb-hub { + compatible = "smsc,usb3503"; + reset-gpios = <&pm8916_gpios 1 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + }; + + usb_id: usb-id { + compatible = "linux,extcon-usb-gpio"; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&usb_id_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; +}; + +&blsp_i2c4 { + status = "okay"; + + adv_bridge: bridge@39 { + compatible = "adi,adv7533"; + reg = <0x39>; + interrupts-extended = <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + + adi,dsi-lanes = <4>; + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + pd-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>; + + avdd-supply = <&pm8916_l6>; + a2vdd-supply = <&pm8916_l6>; + dvdd-supply = <&pm8916_l6>; + pvdd-supply = <&pm8916_l6>; + v1p2-supply = <&pm8916_l6>; + v3p3-supply = <&pm8916_l17>; + + pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>; + pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>; + pinctrl-names = "default","sleep"; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7533_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp_i2c6 { + status = "okay"; + + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&blsp_spi5 { + cs-gpios = <&tlmm 18 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <500000>; + }; +}; + +&blsp_uart1 { + label = "UART0"; + status = "okay"; +}; + +&blsp_uart2 { + label = "UART1"; + status = "okay"; +}; + +&lpass { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&adv7533_in>; +}; + +&pm8916_codec { + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + status = "okay"; +}; + +&pm8916_gpios { + gpio-line-names = + "USB_HUB_RESET_N_PM", + "USB_SW_SEL_PM", + "NC", + "NC"; + + usb_hub_reset_pm: usb-hub-reset-pm-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-high; + }; + + usb_hub_reset_pm_device: usb-hub-reset-pm-device-state { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + input-disable; + output-low; + }; + + usb_sw_sel_pm: usb-sw-sel-pm-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <PM8916_GPIO_VPH>; + input-disable; + output-high; + }; + + usb_sw_sel_pm_device: usb-sw-sel-pm-device-state { + pins = "gpio2"; + function = PMIC_GPIO_FUNC_NORMAL; + power-source = <PM8916_GPIO_VPH>; + input-disable; + output-low; + }; +}; + +&pm8916_mpps { + gpio-line-names = + "NC", + "WLAN_LED_CTRL", + "BT_LED_CTRL", + "NC"; + + pm8916_mpps_leds: pm8916-mpps-state { + pins = "mpp2", "mpp3"; + function = "digital"; + output-low; + }; +}; + +&pm8916_resin { + linux,code = <KEY_POWER>; + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sound { + pinctrl-0 = <&cdc_pdm_default &sec_mi2s_default>; + pinctrl-1 = <&cdc_pdm_sleep &sec_mi2s_sleep>; + pinctrl-names = "default", "sleep"; + model = "HMIBSC"; + audio-routing = + "AMIC2", "MIC BIAS Internal2", + "AMIC3", "MIC BIAS External1"; + status = "okay"; + + quaternary-dai-link { + link-name = "ADV7533"; + cpu { + sound-dai = <&lpass MI2S_QUATERNARY>; + }; + codec { + sound-dai = <&adv_bridge 0>; + }; + }; + + primary-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&pm8916_codec 0>; + }; + }; + + tertiary-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&pm8916_codec 1>; + }; + }; +}; + +&tlmm { + pinctrl-0 = <&uart1_mux0_rs232_high &uart1_mux1_rs232_low>; + pinctrl-names = "default"; + + adv7533_int_active: adv533-int-active-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + adv7533_int_suspend: adv7533-int-suspend-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + adv7533_switch_active: adv7533-switch-active-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + adv7533_switch_suspend: adv7533-switch-suspend-state { + pins = "gpio32"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + msm_key_volp_n_default: msm-key-volp-n-default-state { + pins = "gpio107"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + /* + * UART1 being the debug console supports various modes of + * operation (RS-232/485/422) controlled via GPIOs configured + * mux as follows: + * + * gpio100 gpio99 UART mode + * 0 0 loopback + * 0 1 RS-232 + * 1 0 RS-485 + * 1 1 RS-422 + * + * The default mode configured here is RS-232 mode. + */ + uart1_mux0_rs232_high: uart1-mux0-rs232-state { + bootph-all; + pins = "gpio99"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + + uart1_mux1_rs232_low: uart1-mux1-rs232-state { + bootph-all; + pins = "gpio100"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-low; + }; + + usb_id_default: usb-id-default-state { + pins = "gpio110"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&usb_id>, <&usb_id>; + pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>; + pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>; + pinctrl-names = "default", "device"; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&usb_id>; +}; + +&wcnss { + firmware-name = "qcom/apq8016/wcnss.mbn"; + status = "okay"; +}; + +&wcnss_ctrl { + firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3620"; +}; + +&wcnss_mem { + status = "okay"; +}; + +/* PINCTRL - additions to nodes defined in msm8916.dtsi */ + +/* + * 2mA drive strength is not enough when connecting multiple + * I2C devices with different pull up resistors. + */ +&blsp_i2c4_default { + drive-strength = <16>; +}; + +&blsp_i2c6_default { + drive-strength = <16>; +}; + +&blsp_uart1_default { + bootph-all; +}; + +/* Enable CoreSight */ +&cti0 { status = "okay"; }; +&cti1 { status = "okay"; }; +&cti12 { status = "okay"; }; +&cti13 { status = "okay"; }; +&cti14 { status = "okay"; }; +&cti15 { status = "okay"; }; +&debug0 { status = "okay"; }; +&debug1 { status = "okay"; }; +&debug2 { status = "okay"; }; +&debug3 { status = "okay"; }; +&etf { status = "okay"; }; +&etm0 { status = "okay"; }; +&etm1 { status = "okay"; }; +&etm2 { status = "okay"; }; +&etm3 { status = "okay"; }; +&etr { status = "okay"; }; +&funnel0 { status = "okay"; }; +&funnel1 { status = "okay"; }; +&replicator { status = "okay"; }; +&stm { status = "okay"; }; +&tpiu { status = "okay"; };
Support for Schneider Electric HMIBSC. Features: - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306) - 2GiB RAM - 64GiB eMMC, SD slot - WiFi and Bluetooth - 2x Host, 1x Device USB port - HDMI - Discrete TPM2 chip over SPI
Features enabled in U-Boot: - RAUC updates - Environment protection - USB based ethernet adaptors
Signed-off-by: Sumit Garg sumit.garg@linaro.org --- board/schneider/hmibsc/MAINTAINERS | 6 +++ board/schneider/hmibsc/hmibsc.env | 40 ++++++++++++++ configs/hmibsc_defconfig | 87 ++++++++++++++++++++++++++++++ doc/board/index.rst | 1 + doc/board/schneider/hmibsc.rst | 45 ++++++++++++++++ doc/board/schneider/index.rst | 9 ++++ include/configs/hmibsc.h | 16 ++++++ 7 files changed, 204 insertions(+) create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 board/schneider/hmibsc/hmibsc.env create mode 100644 configs/hmibsc_defconfig create mode 100644 doc/board/schneider/hmibsc.rst create mode 100644 doc/board/schneider/index.rst create mode 100644 include/configs/hmibsc.h
diff --git a/board/schneider/hmibsc/MAINTAINERS b/board/schneider/hmibsc/MAINTAINERS new file mode 100644 index 00000000000..0f31bbda966 --- /dev/null +++ b/board/schneider/hmibsc/MAINTAINERS @@ -0,0 +1,6 @@ +HMIBSC BOARD +M: Sumit Garg sumit.garg@linaro.org +S: Maintained +F: board/schneider/hmibsc/ +F: include/configs/hmibsc.h +F: configs/hmibsc_defconfig diff --git a/board/schneider/hmibsc/hmibsc.env b/board/schneider/hmibsc/hmibsc.env new file mode 100644 index 00000000000..da3d892f91d --- /dev/null +++ b/board/schneider/hmibsc/hmibsc.env @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +loadaddr=0x90000000 +bootcmd= + echo "Booting RAUC A/B system"; + setenv devtype mmc; setenv devnum 0; + test -n "${BOOT_ORDER}" || setenv BOOT_ORDER "A B"; + test -n "${BOOT_A_LEFT}" || setenv BOOT_A_LEFT 3; + test -n "${BOOT_B_LEFT}" || setenv BOOT_B_LEFT 3; + setenv raucslot; + for BOOT_SLOT in "${BOOT_ORDER}"; do + if test "x${raucslot}" != "x"; then + echo "skip remaining slots..."; + elif test "x${BOOT_SLOT}" = "xA"; then + if test ${BOOT_A_LEFT} -gt 0; then + setexpr BOOT_A_LEFT ${BOOT_A_LEFT} - 1; + echo "Found valid RAUC slot A"; + setenv raucslot "rauc.slot=A"; + setenv raucpart A; setenv distro_bootpart 6; + fi; + elif test "x${BOOT_SLOT}" = "xB"; then + if test ${BOOT_B_LEFT} -gt 0; then + setexpr BOOT_B_LEFT ${BOOT_B_LEFT} - 1; + echo "Found valid RAUC slot B"; + setenv raucslot "rauc.slot=B"; + setenv raucpart B; setenv distro_bootpart 7; + fi; + fi; + done; + if test -n "${raucslot}"; then + setenv bootargs console=ttyMSM1 root=PARTLABEL=rootfs_${raucpart} rw rootwait ${raucslot}; + saveenv; + else + echo "No valid RAUC slot found. Resetting tries to 3"; + setenv BOOT_A_LEFT 3; + setenv BOOT_B_LEFT 3; + saveenv; + reset; + fi; + load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} /boot/fitImage && bootm; diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig new file mode 100644 index 00000000000..a07689894ef --- /dev/null +++ b/configs/hmibsc_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_SYS_VENDOR="schneider" +CONFIG_SYS_BOARD="hmibsc" +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y +CONFIG_ARCH_SNAPDRAGON=y +CONFIG_TEXT_BASE=0x8f600000 +CONFIG_SYS_MALLOC_LEN=0x802000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_DEFAULT_DEVICE_TREE="apq8016-schneider-hmibsc" +# CONFIG_OF_UPSTREAM is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_IDENT_STRING="\nSchneider Electric-HMIBSC" +CONFIG_SYS_LOAD_ADDR=0x80080000 +CONFIG_REMAKE_ELF=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_CBSIZE=2048 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="hmibsc => " +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_CMD_IMI is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +CONFIG_BOOTP_BOOTFILESIZE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_ENV_EXISTS=y +CONFIG_CMD_NVEDIT_INFO=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON_QCOM_PMIC=y +CONFIG_CLK=y +CONFIG_CLK_QCOM_APQ8016=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x91000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_MSM_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_QCOM_APQ8016=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_QCOM=y +CONFIG_MSM_SERIAL=y +CONFIG_SPMI_MSM=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_PHYLIB=y +CONFIG_USB_ETHER_LAN75XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x18d1 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd00d +CONFIG_CI_UDC=y diff --git a/doc/board/index.rst b/doc/board/index.rst index f0a11f84ccc..428faa810be 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -42,6 +42,7 @@ Board-specific doc renesas/index rockchip/index samsung/index + schneider/index sielaff/index siemens/index sifive/index diff --git a/doc/board/schneider/hmibsc.rst b/doc/board/schneider/hmibsc.rst new file mode 100644 index 00000000000..f09fb5af1b3 --- /dev/null +++ b/doc/board/schneider/hmibsc.rst @@ -0,0 +1,45 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Sumit Garg sumit.garg@linaro.org + +HMIBSC +====== + +The HMIBSC is an IIoT Edge Box Core board based on the Qualcomm APQ8016E SoC. +More information can be found on the `SE product page`_. + +U-Boot can be used as a replacement for Qualcomm's original Android bootloader +(a fork of Little Kernel/LK). Like LK, it is installed directly into the ``aboot`` +partition. Note that the U-Boot port used to be loaded as an Android boot image +through LK. This is no longer the case, now U-Boot can replace LK entirely. + +.. _SE product page: https://www.se.com/us/en/product/HMIBSCEA53D1L0T/iiot-edge-box-core-harmony-... + +Build steps +----------- + +First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``hmibsc``:: + + $ export CROSS_COMPILE=<aarch64 toolchain prefix> + $ make hmibsc_defconfig + $ make + +This will build ``u-boot.elf`` in the configured output directory. + +Installation +------------ + +Although the HMIBSC does not have secure boot set up by default, the firmware +still expects firmware ELF images to be "signed". The signature does not provide +any security in this case, but it provides the firmware with some required +metadata. + +To "sign" ``u-boot.elf`` you can use e.g. `qtestsign`_:: + + $ ./qtestsign.py aboot u-boot.elf + +Then install the resulting ``u-boot-test-signed.mbn`` to the ``aboot`` partition +on your device, e.g. with ``fastboot flash aboot u-boot-test-signed.mbn``. + +U-Boot should be running after a reboot (``fastboot reboot``). + +.. _qtestsign: https://github.com/msm8916-mainline/qtestsign diff --git a/doc/board/schneider/index.rst b/doc/board/schneider/index.rst new file mode 100644 index 00000000000..55792ed3100 --- /dev/null +++ b/doc/board/schneider/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Schneider Electric +================== + +.. toctree:: + :maxdepth: 2 + + hmibsc diff --git a/include/configs/hmibsc.h b/include/configs/hmibsc.h new file mode 100644 index 00000000000..27404c80fdf --- /dev/null +++ b/include/configs/hmibsc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for HMIBSC + * + * (C) Copyright 2024 Sumit Garg sumit.garg@linaro.org + */ + +#ifndef __CONFIGS_HMIBSC_H +#define __CONFIGS_HMIBSC_H + +/* PHY needs a longer aneg time */ +#define PHY_ANEG_TIMEOUT 8000 + +#define CFG_ENV_FLAGS_LIST_STATIC "BOOT_A_LEFT:dw,BOOT_B_LEFT:dw,BOOT_ORDER:sw" + +#endif
Hi Caleb,
On Fri, 12 Apr 2024 at 02:54, Sumit Garg sumit.garg@linaro.org wrote:
SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major difference from db410c is serial port where HMIBSC board uses UART1 as the debug console with an RS232 port, patch #2 - #5 adds corresponding driver support.
Patch #6 adds main HMIBSC board specific bits, features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 2GiB RAM
- 64GiB eMMC, SD slot
- WiFi and Bluetooth
- 2x Host, 1x Device USB port
- HDMI
- Discrete TPM2 chip over SPI
Features enabled in U-Boot:
- RAUC updates (refer [2] for more details)
- Environment protection
- USB based ethernet adaptors
Feedback is very much welcome.
Changes in v4:
- Rebased on top of qcom-main [4].
- Split out board DTS patch as #6.
- Convert to text based environment as hmibsc.env.
- MMC regression has been reported for qcom-main branch here [5].
- Collected further review tag.
I haven't seen any further comments on this series. Can you help pick it up?
-Sumit
Changes in v3:
- Rebased on top of qcom-next [1].
- Collected some review tags.
- Incorporated misc. comments from Caleb and Stephen.
- Split patch#4 as requested.
- Linux HMIBSC board DTS has already been reviewed here [3], I have incorporated that for U-Boot too.
Changes in v2:
- Rebased on top on qcom-next [1].
- Added patch#1 as a fix for generic qcom board support.
- Added patch#4 to enable driving GPIO pins based on pinctrl configuration. This replaces the custom GPIO configuration.
- Added proper DTS file for HMIBSC board based on Linux DT pattern.
- Merged board support patches into a single patch#5.
[1] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-ne... [2] https://rauc.readthedocs.io/en/latest/ [3] https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.garg@lin... [4] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-ma... [5] https://lore.kernel.org/all/CAFA6WYO+3VroUdFUVH390taViQX8pMQrOQDTSn0yU6BD5YY...
Sumit Garg (7): qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default apq8016: Add support for UART1 clocks and pinmux serial_msm: Enable RS232 flow control pinctrl: qcom: Add support for driving GPIO pins output pinctrl: qcom: apq8016: Add GPIO pinctrl function arm: dts: qcom: Add Schneider HMIBSC board dts board: add support for Schneider HMIBSC board
arch/arm/Kconfig | 2 +- arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++++++++++++++++++++++ board/schneider/hmibsc/MAINTAINERS | 6 + board/schneider/hmibsc/hmibsc.env | 40 ++ configs/hmibsc_defconfig | 87 ++++ doc/board/index.rst | 1 + doc/board/schneider/hmibsc.rst | 45 ++ doc/board/schneider/index.rst | 9 + drivers/clk/qcom/clock-apq8016.c | 38 +- drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 + drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +- drivers/serial/serial_msm.c | 24 +- include/configs/hmibsc.h | 16 + 13 files changed, 760 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 board/schneider/hmibsc/hmibsc.env create mode 100644 configs/hmibsc_defconfig create mode 100644 doc/board/schneider/hmibsc.rst create mode 100644 doc/board/schneider/index.rst create mode 100644 include/configs/hmibsc.h
-- 2.34.1
Applied, thanks.
(b4 didn't seem to detect this series properly, hence the manual mail).
On 12/04/2024 11:54, Sumit Garg wrote:
SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major difference from db410c is serial port where HMIBSC board uses UART1 as the debug console with an RS232 port, patch #2 - #5 adds corresponding driver support.
Patch #6 adds main HMIBSC board specific bits, features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 2GiB RAM
- 64GiB eMMC, SD slot
- WiFi and Bluetooth
- 2x Host, 1x Device USB port
- HDMI
- Discrete TPM2 chip over SPI
Features enabled in U-Boot:
- RAUC updates (refer [2] for more details)
- Environment protection
- USB based ethernet adaptors
Feedback is very much welcome.
Changes in v4:
- Rebased on top of qcom-main [4].
- Split out board DTS patch as #6.
- Convert to text based environment as hmibsc.env.
- MMC regression has been reported for qcom-main branch here [5].
- Collected further review tag.
Changes in v3:
- Rebased on top of qcom-next [1].
- Collected some review tags.
- Incorporated misc. comments from Caleb and Stephen.
- Split patch#4 as requested.
- Linux HMIBSC board DTS has already been reviewed here [3], I have incorporated that for U-Boot too.
Changes in v2:
- Rebased on top on qcom-next [1].
- Added patch#1 as a fix for generic qcom board support.
- Added patch#4 to enable driving GPIO pins based on pinctrl configuration. This replaces the custom GPIO configuration.
- Added proper DTS file for HMIBSC board based on Linux DT pattern.
- Merged board support patches into a single patch#5.
[1] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-ne... [2] https://rauc.readthedocs.io/en/latest/ [3] https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.garg@lin... [4] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-ma... [5] https://lore.kernel.org/all/CAFA6WYO+3VroUdFUVH390taViQX8pMQrOQDTSn0yU6BD5YY...
Sumit Garg (7): qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default apq8016: Add support for UART1 clocks and pinmux serial_msm: Enable RS232 flow control pinctrl: qcom: Add support for driving GPIO pins output pinctrl: qcom: apq8016: Add GPIO pinctrl function arm: dts: qcom: Add Schneider HMIBSC board dts board: add support for Schneider HMIBSC board
arch/arm/Kconfig | 2 +- arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++++++++++++++++++++++ board/schneider/hmibsc/MAINTAINERS | 6 + board/schneider/hmibsc/hmibsc.env | 40 ++ configs/hmibsc_defconfig | 87 ++++ doc/board/index.rst | 1 + doc/board/schneider/hmibsc.rst | 45 ++ doc/board/schneider/index.rst | 9 + drivers/clk/qcom/clock-apq8016.c | 38 +- drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 + drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +- drivers/serial/serial_msm.c | 24 +- include/configs/hmibsc.h | 16 + 13 files changed, 760 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 board/schneider/hmibsc/hmibsc.env create mode 100644 configs/hmibsc_defconfig create mode 100644 doc/board/schneider/hmibsc.rst create mode 100644 doc/board/schneider/index.rst create mode 100644 include/configs/hmibsc.h
On Tue, 23 Apr 2024 at 17:29, Caleb Connolly caleb.connolly@linaro.org wrote:
Applied, thanks.
Thanks.
(b4 didn't seem to detect this series properly, hence the manual mail).
Switching my workflow to b4 is on my ToDo list. I hope to do it sooner rather than later.
-Sumit
On 12/04/2024 11:54, Sumit Garg wrote:
SE HMIBSC board is based on Qcom APQ8016 SoC. One of the major difference from db410c is serial port where HMIBSC board uses UART1 as the debug console with an RS232 port, patch #2 - #5 adds corresponding driver support.
Patch #6 adds main HMIBSC board specific bits, features:
- Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
- 2GiB RAM
- 64GiB eMMC, SD slot
- WiFi and Bluetooth
- 2x Host, 1x Device USB port
- HDMI
- Discrete TPM2 chip over SPI
Features enabled in U-Boot:
- RAUC updates (refer [2] for more details)
- Environment protection
- USB based ethernet adaptors
Feedback is very much welcome.
Changes in v4:
- Rebased on top of qcom-main [4].
- Split out board DTS patch as #6.
- Convert to text based environment as hmibsc.env.
- MMC regression has been reported for qcom-main branch here [5].
- Collected further review tag.
Changes in v3:
- Rebased on top of qcom-next [1].
- Collected some review tags.
- Incorporated misc. comments from Caleb and Stephen.
- Split patch#4 as requested.
- Linux HMIBSC board DTS has already been reviewed here [3], I have incorporated that for U-Boot too.
Changes in v2:
- Rebased on top on qcom-next [1].
- Added patch#1 as a fix for generic qcom board support.
- Added patch#4 to enable driving GPIO pins based on pinctrl configuration. This replaces the custom GPIO configuration.
- Added proper DTS file for HMIBSC board based on Linux DT pattern.
- Merged board support patches into a single patch#5.
[1] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-ne... [2] https://rauc.readthedocs.io/en/latest/ [3] https://lore.kernel.org/linux-kernel/20240403043416.3800259-4-sumit.garg@lin... [4] https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/commits/qcom-ma... [5] https://lore.kernel.org/all/CAFA6WYO+3VroUdFUVH390taViQX8pMQrOQDTSn0yU6BD5YY...
Sumit Garg (7): qcom: Don't enable LINUX_KERNEL_IMAGE_HEADER by default apq8016: Add support for UART1 clocks and pinmux serial_msm: Enable RS232 flow control pinctrl: qcom: Add support for driving GPIO pins output pinctrl: qcom: apq8016: Add GPIO pinctrl function arm: dts: qcom: Add Schneider HMIBSC board dts board: add support for Schneider HMIBSC board
arch/arm/Kconfig | 2 +- arch/arm/dts/apq8016-schneider-hmibsc.dts | 491 ++++++++++++++++++++++ board/schneider/hmibsc/MAINTAINERS | 6 + board/schneider/hmibsc/hmibsc.env | 40 ++ configs/hmibsc_defconfig | 87 ++++ doc/board/index.rst | 1 + doc/board/schneider/hmibsc.rst | 45 ++ doc/board/schneider/index.rst | 9 + drivers/clk/qcom/clock-apq8016.c | 38 +- drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 + drivers/pinctrl/qcom/pinctrl-qcom.c | 25 +- drivers/serial/serial_msm.c | 24 +- include/configs/hmibsc.h | 16 + 13 files changed, 760 insertions(+), 26 deletions(-) create mode 100644 arch/arm/dts/apq8016-schneider-hmibsc.dts create mode 100644 board/schneider/hmibsc/MAINTAINERS create mode 100644 board/schneider/hmibsc/hmibsc.env create mode 100644 configs/hmibsc_defconfig create mode 100644 doc/board/schneider/hmibsc.rst create mode 100644 doc/board/schneider/index.rst create mode 100644 include/configs/hmibsc.h
-- // Caleb (they/them)
participants (3)
-
Caleb Connolly -
neil.armstrong＠linaro.org -
Sumit Garg