[U-Boot] [PATCH] sata: sata_mv: Fix misaligned cache warnings

This patch fixes the warnings about misaligned cache on Armada XP:
CACHE: Misaligned operation at range [7facb400, 7facb460]
Signed-off-by: Stefan Roese sr@denx.de --- drivers/block/sata_mv.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/block/sata_mv.c b/drivers/block/sata_mv.c index 8d36f44..bbc75fe 100644 --- a/drivers/block/sata_mv.c +++ b/drivers/block/sata_mv.c @@ -572,6 +572,7 @@ static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis, struct mv_priv *priv = (struct mv_priv *)sata_dev_desc[port].priv; struct crqb *req; int slot; + u32 start;
if (len >= 64 * 1024) { printf("We only support <64K transfers for now\n"); @@ -628,7 +629,9 @@ static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis, CRQB_SECTCOUNT_COUNT_EXP_MASK;
/* Flush data */ - flush_dcache_range((u32)req, (u32)req + sizeof(*req)); + start = (u32)req & ~(ARCH_DMA_MINALIGN - 1); + flush_dcache_range(start, + start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
/* Trigger operation */ slot = get_next_reqip(port); @@ -643,8 +646,11 @@ static int mv_ata_exec_ata_cmd(int port, struct sata_fis_h2d *cfis, process_responses(port);
/* Invalidate data on read */ - if (buffer && len) - invalidate_dcache_range((u32)buffer, (u32)buffer + len); + if (buffer && len) { + start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1); + invalidate_dcache_range(start, + start + ALIGN(len, ARCH_DMA_MINALIGN)); + }
return len; }

This patch fixes the warning about misaligned cache on Armada XP:
CACHE: Misaligned operation at range [7ffff000, 7fffffac]
Signed-off-by: Stefan Roese sr@denx.de Cc: Valentin Longchamp valentin.longchamp@keymile.com --- drivers/bootcount/bootcount_ram.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/bootcount/bootcount_ram.c b/drivers/bootcount/bootcount_ram.c index e0d2669..ad4cc56 100644 --- a/drivers/bootcount/bootcount_ram.c +++ b/drivers/bootcount/bootcount_ram.c @@ -37,7 +37,8 @@ void bootcount_store(ulong a)
/* Make sure the data is written to RAM */ flush_dcache_range((ulong)&save_addr[0], - (ulong)&save_addr[REPEAT_PATTERN + OFFS_PATTERN]); + (((ulong)&save_addr[REPEAT_PATTERN + OFFS_PATTERN] & + ~(ARCH_DMA_MINALIGN - 1)) + ARCH_DMA_MINALIGN)); }
ulong bootcount_load(void)

On Fri, Nov 18, 2016 at 05:21:52PM +0100, Stefan Roese wrote:
This patch fixes the warning about misaligned cache on Armada XP:
CACHE: Misaligned operation at range [7ffff000, 7fffffac]
Signed-off-by: Stefan Roese sr@denx.de Cc: Valentin Longchamp valentin.longchamp@keymile.com
Reviewed-by: Tom Rini trini@konsulko.com

On Fri, Nov 18, 2016 at 05:21:52PM +0100, Stefan Roese wrote:
This patch fixes the warning about misaligned cache on Armada XP:
CACHE: Misaligned operation at range [7ffff000, 7fffffac]
Signed-off-by: Stefan Roese sr@denx.de Cc: Valentin Longchamp valentin.longchamp@keymile.com Reviewed-by: Tom Rini trini@konsulko.com
Applied to u-boot/master, thanks!

On 18.11.2016 17:21, Stefan Roese wrote:
This patch fixes the warnings about misaligned cache on Armada XP:
CACHE: Misaligned operation at range [7facb400, 7facb460]
Signed-off-by: Stefan Roese sr@denx.de
Applied to u-boot-marvell/master.
Thanks, Stefan
participants (3)
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Stefan Roese
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Stefan Roese
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Tom Rini