[U-Boot] [PATCHv2 0/3] dm: pcie_fsl: Fix some issues
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The current driver is not working on some PowerPC T-series, P-series and MPC85xx platforms due to the difference in PCIe IP revisions and the various integration on different platforms. This patch set fixes these issues.
Hou Zhiqiang (3): dm: pcie_fsl: Fix workaround of P4080 erratum A003 dm: pcie_fsl: Fix the Class Code fixup function dm: pcie_fsl: Fix the calculation of controller index
drivers/pci/pcie_fsl.c | 33 ++++++++++++++++++++++++++------- drivers/pci/pcie_fsl.h | 12 ++++++++++++ 2 files changed, 38 insertions(+), 7 deletions(-)
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
In the workaround of P4080 erratum A003, it uses the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block register address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as following:
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined on both corenet and non-corenet platforms (though it should be defined only on corenet platforms), but the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on corenet platforms, so when enabled this driver on non-corenet platforms, the following build error will come up:
drivers/pci/pcie_fsl.c: In function 'fsl_pcie_init_port': ./arch/powerpc/include/asm/immap_85xx.h:3000:21: error: 'CONFIG_SYS_FSL_CORENET_SERDES_OFFSET' undeclared (first use in this function); did you mean 'CONFIG_SYS_FSL_CORENET_SERDES_ADDR'? (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fix this build error by replacing it with a new added macro for SerDes address of P4080.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - Replaced CONFIG_SYS_FSL_CORENET_SERDES_ADDR with the CCSR base + P4080 SerDes offset. - Reworded the change log slightly.
drivers/pci/pcie_fsl.c | 2 +- drivers/pci/pcie_fsl.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 4d61a46cef..29b50f2376 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -444,7 +444,7 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) !fsl_pcie_link_up(pcie)) { serdes_corenet_t *srds_regs;
- srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + srds_regs = (void *)P4080_SERDES_ADDR; val_32 = in_be32(&srds_regs->srdspccr0);
if ((val_32 >> 28) == 3) { diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 5eefc31fa9..35a740241e 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -40,6 +40,8 @@ #define LTSSM_L0_REV3 0x11 #define LTSSM_L0 0x16
+#define P4080_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA000) + struct fsl_pcie { int idx; struct udevice *bus;
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
In the workaround of P4080 erratum A003, it uses the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block register address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as following:
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined on both corenet and non-corenet platforms (though it should be defined only on corenet platforms), but the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on corenet platforms, so when enabled this driver on non-corenet platforms,
so when enabling
the following build error will come up:
This patch still does not look correct to me.
So far only ARCH_P4080 selects SYS_P4080_ERRATUM_PCIE_A003, so the CONFIG_SYS_FSL_CORENET_SERDES_ADDR needs to be only defined in the P4080 codes. Replacing the macro name to P4080_SERDES_ADDR does not help anything.
drivers/pci/pcie_fsl.c: In function 'fsl_pcie_init_port': ./arch/powerpc/include/asm/immap_85xx.h:3000:21: error: 'CONFIG_SYS_FSL_CORENET_SERDES_OFFSET' undeclared (first use in this function); did you mean 'CONFIG_SYS_FSL_CORENET_SERDES_ADDR'? (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fix this build error by replacing it with a new added macro for SerDes address of P4080.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2:
- Replaced CONFIG_SYS_FSL_CORENET_SERDES_ADDR with the CCSR base + P4080 SerDes offset.
- Reworded the change log slightly.
drivers/pci/pcie_fsl.c | 2 +- drivers/pci/pcie_fsl.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-)
Regards, Bin
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 13:59 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
In the workaround of P4080 erratum A003, it uses the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
register
address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as following:
(CONFIG_SYS_IMMR +CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR is
defined
on both corenet and non-corenet platforms (though it should be defined only on corenet platforms), but the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on corenet platforms, so when enabled this driver on non-corenet platforms,
so when enabling
The following series will enable DM PCIe on some PowerPC platforms including MPC8548CDS, which isn't a CORENET platform. http://patchwork.ozlabs.org/project/uboot/list/?series=120966
the following build error will come up:
This patch still does not look correct to me.
So far only ARCH_P4080 selects SYS_P4080_ERRATUM_PCIE_A003, so the CONFIG_SYS_FSL_CORENET_SERDES_ADDR needs to be only defined in the P4080 codes.
The CONFIG_SYS_FSL_CORENET_SERDES_ADDR is a macro for SerDes registers Address, it is not dedicated for workarounds, and the SerDes registers address macro was defined on both CORENET and non-CORENET platforms.
Replacing the macro name to P4080_SERDES_ADDR does not help anything.
As the macro CONFIG_SYS_IMMR is always defined on CORENET and non-CORENET platforms, so replacing the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET, which is only defined on CORENET platforms, with the P4080 SerDes registers address in constant number can resolve the build error on non-CORENET.
Thanks, Zhiqiang
drivers/pci/pcie_fsl.c: In function 'fsl_pcie_init_port': ./arch/powerpc/include/asm/immap_85xx.h:3000:21: error: 'CONFIG_SYS_FSL_CORENET_SERDES_OFFSET' undeclared (first use in this function); did you mean 'CONFIG_SYS_FSL_CORENET_SERDES_ADDR'? (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Fix this build error by replacing it with a new added macro for SerDes address of P4080.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2:
- Replaced CONFIG_SYS_FSL_CORENET_SERDES_ADDR with the CCSR
base +
P4080 SerDes offset.
- Reworded the change log slightly.
drivers/pci/pcie_fsl.c | 2 +- drivers/pci/pcie_fsl.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-)
Regards, Bin
Hi Zhiqiang,
On Mon, Aug 26, 2019 at 4:34 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 13:59 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
In the workaround of P4080 erratum A003, it uses the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
register
address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as following:
(CONFIG_SYS_IMMR +CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR is
defined
on both corenet and non-corenet platforms (though it should be defined only on corenet platforms), but the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on corenet platforms, so when enabled this driver on non-corenet platforms,
so when enabling
The following series will enable DM PCIe on some PowerPC platforms including MPC8548CDS, which isn't a CORENET platform. http://patchwork.ozlabs.org/project/uboot/list/?series=120966
Is this patch series merged? Or still in the review queue. I would like to have a look.
the following build error will come up:
This patch still does not look correct to me.
So far only ARCH_P4080 selects SYS_P4080_ERRATUM_PCIE_A003, so the CONFIG_SYS_FSL_CORENET_SERDES_ADDR needs to be only defined in the P4080 codes.
The CONFIG_SYS_FSL_CORENET_SERDES_ADDR is a macro for SerDes registers Address, it is not dedicated for workarounds, and the SerDes registers address macro was defined on both CORENET and non-CORENET platforms.
Replacing the macro name to P4080_SERDES_ADDR does not help anything.
As the macro CONFIG_SYS_IMMR is always defined on CORENET and non-CORENET platforms, so replacing the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET, which is only defined on CORENET platforms, with the P4080 SerDes registers address in constant number can resolve the build error on non-CORENET.
I don't understand. Unless SYS_P4080_ERRATUM_PCIE_A003 is turned on by other non-CORENET platforms. Could you please point to me which patch does this?
Regards, Bin
Dear Bin,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Monday, August 26, 2019 2:21 PM To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Mon, Aug 26, 2019 at 4:34 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 13:59 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
In the workaround of P4080 erratum A003, it uses the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
register
address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as following:
(CONFIG_SYS_IMMR +CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR is
defined
on both corenet and non-corenet platforms (though it should be defined only on corenet platforms), but the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on corenet platforms, so when enabled this driver on non-corenet platforms,
so when enabling
The following series will enable DM PCIe on some PowerPC platforms including MPC8548CDS, which isn't a CORENET platform. https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
work.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D120966&dat a
=02%7C01%7Cprabhakar.kushwaha%40nxp.com%7C927d704c60734c63fb7708 d72a02
7cd0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702406248371 8776&a
mp;sdata=HLHA1%2FXmSxPPz%2FOF%2BWu30kQDD0xGsWOhxyHBEuMs8hw% 3D&rese
rved=0
Is this patch series merged? Or still in the review queue. I would like to have a look.
This patch series has not been merged. I am in process of integrating it.
powerpc: Enable PCIe DM drvier for some platforms: http://patchwork.ozlabs.org/project/uboot/list/?series=120966
If you have feedback. Please do share.
I can wait to send in in rc4 or rc5.
--pk
Hi Prabhakar,
On Mon, Aug 26, 2019 at 5:10 PM Prabhakar Kushwaha prabhakar.kushwaha@nxp.com wrote:
Dear Bin,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Monday, August 26, 2019 2:21 PM To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Mon, Aug 26, 2019 at 4:34 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 13:59 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
In the workaround of P4080 erratum A003, it uses the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
register
address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as following:
(CONFIG_SYS_IMMR +CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR is
defined
on both corenet and non-corenet platforms (though it should be defined only on corenet platforms), but the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on corenet platforms, so when enabled this driver on non-corenet platforms,
so when enabling
The following series will enable DM PCIe on some PowerPC platforms including MPC8548CDS, which isn't a CORENET platform. https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
work.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D120966&dat a
=02%7C01%7Cprabhakar.kushwaha%40nxp.com%7C927d704c60734c63fb7708 d72a02
7cd0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702406248371 8776&a
mp;sdata=HLHA1%2FXmSxPPz%2FOF%2BWu30kQDD0xGsWOhxyHBEuMs8hw% 3D&rese
rved=0
Is this patch series merged? Or still in the review queue. I would like to have a look.
This patch series has not been merged. I am in process of integrating it.
powerpc: Enable PCIe DM drvier for some platforms: http://patchwork.ozlabs.org/project/uboot/list/?series=120966
If you have feedback. Please do share.
I can wait to send in in rc4 or rc5.
Thanks for letting me know the patch status. I will take a look soon.
Regards, Bin
Hi Prabhakar,
On Mon, Aug 26, 2019 at 9:00 PM Bin Meng bmeng.cn@gmail.com wrote:
Hi Prabhakar,
On Mon, Aug 26, 2019 at 5:10 PM Prabhakar Kushwaha prabhakar.kushwaha@nxp.com wrote:
Dear Bin,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Monday, August 26, 2019 2:21 PM To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Mon, Aug 26, 2019 at 4:34 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 13:59 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
In the workaround of P4080 erratum A003, it uses the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
register
address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as following:
(CONFIG_SYS_IMMR +CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR is
defined
on both corenet and non-corenet platforms (though it should be defined only on corenet platforms), but the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on corenet platforms, so when enabled this driver on non-corenet platforms,
so when enabling
The following series will enable DM PCIe on some PowerPC platforms including MPC8548CDS, which isn't a CORENET platform. https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
work.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D120966&dat a
=02%7C01%7Cprabhakar.kushwaha%40nxp.com%7C927d704c60734c63fb7708 d72a02
7cd0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702406248371 8776&a
mp;sdata=HLHA1%2FXmSxPPz%2FOF%2BWu30kQDD0xGsWOhxyHBEuMs8hw% 3D&rese
rved=0
Is this patch series merged? Or still in the review queue. I would like to have a look.
This patch series has not been merged. I am in process of integrating it.
powerpc: Enable PCIe DM drvier for some platforms: http://patchwork.ozlabs.org/project/uboot/list/?series=120966
If you have feedback. Please do share.
I can wait to send in in rc4 or rc5.
Thanks for letting me know the patch status. I will take a look soon.
Thanks to Zhiqiang's quick response to my review comments, now I have finished the review for patch series http://patchwork.ozlabs.org/project/uboot/list/?series=120966.
Regards, Bin
Thanks Bin
Let me integrate his patch-set.
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Tuesday, August 27, 2019 10:32 AM To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Cc: Z.q. Hou zhiqiang.hou@nxp.com; u-boot@lists.denx.de Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Prabhakar,
On Mon, Aug 26, 2019 at 9:00 PM Bin Meng bmeng.cn@gmail.com wrote:
Hi Prabhakar,
On Mon, Aug 26, 2019 at 5:10 PM Prabhakar Kushwaha prabhakar.kushwaha@nxp.com wrote:
Dear Bin,
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Monday, August 26, 2019 2:21 PM To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Mon, Aug 26, 2019 at 4:34 PM Z.q. Hou zhiqiang.hou@nxp.com
wrote:
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 13:59 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com
wrote:
> > From: Hou Zhiqiang Zhiqiang.Hou@nxp.com > > In the workaround of P4080 erratum A003, it uses the macro > CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block register > address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined > as > following: > > (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) > > The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR > is defined > on both corenet and non-corenet platforms (though it should > be defined only on corenet platforms), but the macro > CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on > corenet platforms, so when enabled this driver on > non-corenet platforms,
so when enabling
The following series will enable DM PCIe on some PowerPC platforms including MPC8548CDS, which isn't a CORENET platform. http://patch
work.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D120966&
dat a
=02%7C01%7Cprabhakar.kushwaha%40nxp.com%7C927d704c60734c63fb7708
d72a02
7cd0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702406248371
8776&a
mp;sdata=HLHA1%2FXmSxPPz%2FOF%2BWu30kQDD0xGsWOhxyHBEuMs8hw%
3D&rese
rved=0
Is this patch series merged? Or still in the review queue. I would like to have a look.
This patch series has not been merged. I am in process of integrating it.
powerpc: Enable PCIe DM drvier for some platforms: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpat
chwork.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D120966&
data=02%7C01%7Cprabhakar.kushwaha%40nxp.com%7C13a11a268f744379648 508
d72aabb175%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702478 9212
237371&sdata=eC0rQReEX7PtVDTlHXmTl2TyHVh70gRYVy4dsBrl7fk%3D&a mp;
reserved=0
If you have feedback. Please do share.
I can wait to send in in rc4 or rc5.
Thanks for letting me know the patch status. I will take a look soon.
Thanks to Zhiqiang's quick response to my review comments, now I have finished the review for patch series https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatchwor k.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D120966&data=0 2%7C01%7Cprabhakar.kushwaha%40nxp.com%7C13a11a268f744379648508d7 2aabb175%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6370247892 12237371&sdata=eC0rQReEX7PtVDTlHXmTl2TyHVh70gRYVy4dsBrl7fk%3D &reserved=0.
Regards, Bin
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 16:51 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Mon, Aug 26, 2019 at 4:34 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 13:59 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com
wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
In the workaround of P4080 erratum A003, it uses the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
register
address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as following:
(CONFIG_SYS_IMMR +CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR
is
defined
on both corenet and non-corenet platforms (though it should be defined only on corenet platforms), but the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on
corenet
platforms, so when enabled this driver on non-corenet platforms,
so when enabling
The following series will enable DM PCIe on some PowerPC platforms including MPC8548CDS, which isn't a CORENET platform.
https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
work.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D120966& ;data
=02%7C01%7Czhiqiang.hou%40nxp.com%7C927d704c60734c63fb7708d72a 027cd0%7
C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702406248358884 7&sda
ta=6M7wj0KNNxL6TNaP9gQABcFJUb8gvV%2BfOhzY9sOswck%3D&rese rved=0
Is this patch series merged? Or still in the review queue. I would like to have a look.
the following build error will come up:
This patch still does not look correct to me.
So far only ARCH_P4080 selects SYS_P4080_ERRATUM_PCIE_A003, so
the
CONFIG_SYS_FSL_CORENET_SERDES_ADDR needs to be only defined in
the
P4080 codes.
The CONFIG_SYS_FSL_CORENET_SERDES_ADDR is a macro for SerDes
registers
Address, it is not dedicated for workarounds, and the SerDes registers address macro was defined on both CORENET and non-CORENET
platforms.
Replacing the macro name to P4080_SERDES_ADDR does not help
anything.
As the macro CONFIG_SYS_IMMR is always defined on CORENET and non-CORENET platforms, so replacing the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET, which is only defined on CORENET platforms, with the P4080 SerDes registers address in constant number can resolve the build error on
non-CORENET.
I don't understand. Unless SYS_P4080_ERRATUM_PCIE_A003 is turned on by other non-CORENET platforms. Could you please point to me which patch does this?
In function fsl_pcie_init_port() in drivers/pci/pcie_fsl.c, it checks this Errata in run-time by "IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003)", so it always precompile the lines of this workaround no matter whether the SYS_P4080_ERRATUM_PCIE_A003 has been selected or not.
Do you think it is better to use "#ifdef ... #endif"?
Thanks, Zhiqiang
Regards, Bin
Hi Zhiqiang,
On Mon, Aug 26, 2019 at 6:17 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 16:51 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Mon, Aug 26, 2019 at 4:34 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 13:59 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum A003
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com
wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
In the workaround of P4080 erratum A003, it uses the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block
register
address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as following:
(CONFIG_SYS_IMMR +CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR
is
defined
on both corenet and non-corenet platforms (though it should be defined only on corenet platforms), but the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on
corenet
platforms, so when enabled this driver on non-corenet platforms,
so when enabling
The following series will enable DM PCIe on some PowerPC platforms including MPC8548CDS, which isn't a CORENET platform.
https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch
work.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D120966& ;data
=02%7C01%7Czhiqiang.hou%40nxp.com%7C927d704c60734c63fb7708d72a 027cd0%7
C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702406248358884 7&sda
ta=6M7wj0KNNxL6TNaP9gQABcFJUb8gvV%2BfOhzY9sOswck%3D&rese rved=0
Is this patch series merged? Or still in the review queue. I would like to have a look.
the following build error will come up:
This patch still does not look correct to me.
So far only ARCH_P4080 selects SYS_P4080_ERRATUM_PCIE_A003, so
the
CONFIG_SYS_FSL_CORENET_SERDES_ADDR needs to be only defined in
the
P4080 codes.
The CONFIG_SYS_FSL_CORENET_SERDES_ADDR is a macro for SerDes
registers
Address, it is not dedicated for workarounds, and the SerDes registers address macro was defined on both CORENET and non-CORENET
platforms.
Replacing the macro name to P4080_SERDES_ADDR does not help
anything.
As the macro CONFIG_SYS_IMMR is always defined on CORENET and non-CORENET platforms, so replacing the macro CONFIG_SYS_FSL_CORENET_SERDES_OFFSET, which is only defined on CORENET platforms, with the P4080 SerDes registers address in constant number can resolve the build error on
non-CORENET.
I don't understand. Unless SYS_P4080_ERRATUM_PCIE_A003 is turned on by other non-CORENET platforms. Could you please point to me which patch does this?
In function fsl_pcie_init_port() in drivers/pci/pcie_fsl.c, it checks this Errata in run-time by "IS_ENABLED(CONFIG_SYS_P4080_ERRATUM_PCIE_A003)", so it always precompile the lines of this workaround no matter whether the SYS_P4080_ERRATUM_PCIE_A003 has been selected or not.
Ah, I see. Thanks for the info.
Do you think it is better to use "#ifdef ... #endif"?
Looks the IS_ENABLED() really does no better than #ifdef, so let's switch all IS_ENABLED in this routine to #ifdef.
Regards, Bin
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones.
This patch is to add the Class Code fixup for the block revision < 3.0.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - No change.
drivers/pci/pcie_fsl.c | 17 +++++++++++++---- drivers/pci/pcie_fsl.h | 3 +++ 2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 29b50f2376..60d274124b 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -502,12 +502,21 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) ccsr_fsl_pci_t *regs = pcie->regs; u32 val;
- setbits_be32(®s->dbi_ro_wr_en, 0x01); - fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val); + if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { + setbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val); + val &= 0xff; + val |= PCI_CLASS_BRIDGE_PCI << 16; + fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val); + clrbits_be32(®s->dbi_ro_wr_en, 0x01); + + return 0; + } + + fsl_pcie_hose_read_config_dword(pcie, CSR_CLASSCODE, &val); val &= 0xff; val |= PCI_CLASS_BRIDGE_PCI << 16; - fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val); - clrbits_be32(®s->dbi_ro_wr_en, 0x01); + fsl_pcie_hose_write_config_dword(pcie, CSR_CLASSCODE, val);
return 0; } diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 35a740241e..cdf28dbea2 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -9,6 +9,9 @@ #ifndef _PCIE_FSL_H_ #define _PCIE_FSL_H_
+/* GPEX CSR */ +#define CSR_CLASSCODE 0x474 + #ifdef CONFIG_SYS_FSL_PCI_VER_3_X #define FSL_PCIE_CAP_ID 0x70 #else
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones.
This patch is to add the Class Code fixup for the block revision < 3.0.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2:
- No change.
drivers/pci/pcie_fsl.c | 17 +++++++++++++---- drivers/pci/pcie_fsl.h | 3 +++ 2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 29b50f2376..60d274124b 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -502,12 +502,21 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) ccsr_fsl_pci_t *regs = pcie->regs; u32 val;
setbits_be32(®s->dbi_ro_wr_en, 0x01);fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {setbits_be32(®s->dbi_ro_wr_en, 0x01);fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION, &val);val &= 0xff;val |= PCI_CLASS_BRIDGE_PCI << 16;fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);clrbits_be32(®s->dbi_ro_wr_en, 0x01);return 0;}
I think you can use a variable "int class_rev_reg", then
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { class_rev_reg = PCI_CLASS_REVISION; setbits_be32(®s->dbi_ro_wr_en, 0x01); } else { class_rev_reg = CSR_CLASSCODE; }
then do the same for both <= 3.0 IP and > 3.0 IP,
and finally
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) clrbits_be32(®s->dbi_ro_wr_en, 0x01);
fsl_pcie_hose_read_config_dword(pcie, CSR_CLASSCODE, &val); val &= 0xff; val |= PCI_CLASS_BRIDGE_PCI << 16;
fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION, val);clrbits_be32(®s->dbi_ro_wr_en, 0x01);
fsl_pcie_hose_write_config_dword(pcie, CSR_CLASSCODE, val); return 0;} diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 35a740241e..cdf28dbea2 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -9,6 +9,9 @@ #ifndef _PCIE_FSL_H_ #define _PCIE_FSL_H_
+/* GPEX CSR */ +#define CSR_CLASSCODE 0x474
#ifdef CONFIG_SYS_FSL_PCI_VER_3_X #define FSL_PCIE_CAP_ID 0x70
#else
Regards, Bin
Hi Bin,
Thanks a lot for your comments!
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 14:07 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 2/3] dm: pcie_fsl: Fix the Class Code fixup function
Hi Zhiqiang,
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The Class Code fixup method was changed from PCIe block revision 3.0, the current fixup is only valid for the revision 3.0 and the later ones.
This patch is to add the Class Code fixup for the block revision < 3.0.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2:
- No change.
drivers/pci/pcie_fsl.c | 17 +++++++++++++---- drivers/pci/pcie_fsl.h | 3 +++ 2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 29b50f2376..60d274124b 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -502,12 +502,21 @@ static int fsl_pcie_fixup_classcode(struct
fsl_pcie *pcie)
ccsr_fsl_pci_t *regs = pcie->regs; u32 val;
setbits_be32(®s->dbi_ro_wr_en, 0x01);fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION,&val);
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {setbits_be32(®s->dbi_ro_wr_en, 0x01);fsl_pcie_hose_read_config_dword(pcie,PCI_CLASS_REVISION, &val);
val &= 0xff;val |= PCI_CLASS_BRIDGE_PCI << 16;fsl_pcie_hose_write_config_dword(pcie,PCI_CLASS_REVISION, val);
clrbits_be32(®s->dbi_ro_wr_en, 0x01);return 0;}I think you can use a variable "int class_rev_reg", then
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) { class_rev_reg = PCI_CLASS_REVISION; setbits_be32(®s->dbi_ro_wr_en, 0x01); } else { class_rev_reg = CSR_CLASSCODE; }
then do the same for both <= 3.0 IP and > 3.0 IP,
and finally
if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) clrbits_be32(®s->dbi_ro_wr_en, 0x01);
Good idea! Will rewrite this func in v3.
Thanks, Zhiqiang
fsl_pcie_hose_read_config_dword(pcie, CSR_CLASSCODE, &val); val &= 0xff; val |= PCI_CLASS_BRIDGE_PCI << 16;
fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION,val);
clrbits_be32(®s->dbi_ro_wr_en, 0x01);
fsl_pcie_hose_write_config_dword(pcie, CSR_CLASSCODE, val); return 0;} diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index 35a740241e..cdf28dbea2 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -9,6 +9,9 @@ #ifndef _PCIE_FSL_H_ #define _PCIE_FSL_H_
+/* GPEX CSR */ +#define CSR_CLASSCODE 0x474
#ifdef CONFIG_SYS_FSL_PCI_VER_3_X #define FSL_PCIE_CAP_ID 0x70
#else
Regards, Bin
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index.
Fix it by adding the related info to the driver data structure.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com --- V2: - No change.
drivers/pci/pcie_fsl.c | 14 ++++++++++++-- drivers/pci/pcie_fsl.h | 7 +++++++ 2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 60d274124b..ff9b07506a 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -579,6 +579,7 @@ static int fsl_pcie_probe(struct udevice *dev) static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) { struct fsl_pcie *pcie = dev_get_priv(dev); + struct fsl_pcie_data *info; int ret;
pcie->regs = dev_remap_addr(dev); @@ -593,7 +594,10 @@ static int fsl_pcie_ofdata_to_platdata(struct udevice *dev) return ret; }
- pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000; + info = (struct fsl_pcie_data *)dev_get_driver_data(dev); + pcie->info = info; + pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) - + info->block_offset) / info->stride;
return 0; } @@ -603,8 +607,14 @@ static const struct dm_pci_ops fsl_pcie_ops = { .write_config = fsl_pcie_write_config, };
+static struct fsl_pcie_data t2080_data = { + .block_offset = 0x240000, + .block_offset_mask = 0x3fffff, + .stride = 0x10000, +}; + static const struct udevice_id fsl_pcie_ids[] = { - { .compatible = "fsl,pcie-t2080" }, + { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { } };
diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index cdf28dbea2..32af54ce49 100644 --- a/drivers/pci/pcie_fsl.h +++ b/drivers/pci/pcie_fsl.h @@ -45,6 +45,12 @@
#define P4080_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA000)
+struct fsl_pcie_data { + u32 block_offset; /* Offset from CCSR of 1st controller */ + u32 block_offset_mask; /* Mask out the CCSR base */ + u32 stride; /* Offset stride between controllers */ +}; + struct fsl_pcie { int idx; struct udevice *bus; @@ -54,6 +60,7 @@ struct fsl_pcie { bool mode; /* RC&EP mode flag */ bool enabled; /* Enable status */ struct list_head list; + struct fsl_pcie_data *info; };
extern struct list_head fsl_pcie_list;
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index.
Fix it by adding the related info to the driver data structure.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2:
- No change.
drivers/pci/pcie_fsl.c | 14 ++++++++++++-- drivers/pci/pcie_fsl.h | 7 +++++++ 2 files changed, 19 insertions(+), 2 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Hi Bin,
Thanks a lot for your review!
Regards, Zhiqiang
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: 2019年8月26日 14:11 To: Z.q. Hou zhiqiang.hou@nxp.com Cc: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCHv2 3/3] dm: pcie_fsl: Fix the calculation of controller index
On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou zhiqiang.hou@nxp.com wrote:
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
The PCIe controller register address in CCSR is different on various platforms, the current code erroneously use the hardcoded address (0xffe240000) and stride (0x10000) to calculate the controller's index.
Fix it by adding the related info to the driver data structure.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com
V2:
- No change.
drivers/pci/pcie_fsl.c | 14 ++++++++++++-- drivers/pci/pcie_fsl.h | 7 +++++++ 2 files changed, 19 insertions(+), 2 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
participants (3)
-
Bin Meng -
Prabhakar Kushwaha -
Z.q. Hou