[U-Boot] [PATCH 1/2] cmd_nand: dump: Align data and OOB buffers
In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.
Signed-off-by: Thierry Reding thierry.reding@avionic-design.de --- common/cmd_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_nand.c b/common/cmd_nand.c index a91ccf4..4367f5a 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
last = off;
- datbuf = malloc(nand->writesize); - oobbuf = malloc(nand->oobsize); + datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize); + oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize); if (!datbuf || !oobbuf) { puts("No memory for page buffer\n"); return 1;
This commit enables NAND support on the Tamonten Evaluation Carrier and adds the corresponding device tree nodes. Furthermore, the U-Boot environment can now be stored in NAND.
Signed-off-by: Thierry Reding thierry.reding@avionic-design.de --- board/avionic-design/dts/tegra20-tec.dts | 11 +++++++++++ include/configs/tec.h | 12 ++++++++++-- 2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/board/avionic-design/dts/tegra20-tec.dts b/board/avionic-design/dts/tegra20-tec.dts index 9faebd8..bb3851b 100644 --- a/board/avionic-design/dts/tegra20-tec.dts +++ b/board/avionic-design/dts/tegra20-tec.dts @@ -55,4 +55,15 @@ usb@c5004000 { status = "disabled"; }; + + nand-controller@70008000 { + nvidia,wp-gpios = <&gpio 23 0>; /* PC7 */ + nvidia,width = <8>; + nvidia,timing = <26 100 20 80 20 10 12 10 70>; + + nand@0 { + reg = <0>; + compatible = "hynix,hy27uf4g2b", "nand-flash"; + }; + }; }; diff --git a/include/configs/tec.h b/include/configs/tec.h index 9b3f88d..54fcd41 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -45,14 +45,22 @@
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_ENV_IS_NOWHERE - /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_TEGRA_MMC #define CONFIG_CMD_MMC
+/* NAND support */ +#define CONFIG_CMD_NAND +#define CONFIG_TEGRA_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE TEGRA20_NAND_BASE + +/* Environment not stored */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */ + /* USB host support */ #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_TEGRA
On 07/31/2012 12:21 AM, Thierry Reding wrote:
This commit enables NAND support on the Tamonten Evaluation Carrier and adds the corresponding device tree nodes. Furthermore, the U-Boot environment can now be stored in NAND.
diff --git a/include/configs/tec.h b/include/configs/tec.h
+/* Environment not stored */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
I guess you also need to update the comment;-)
On Tue, Jul 31, 2012 at 09:40:54AM -0600, Stephen Warren wrote:
On 07/31/2012 12:21 AM, Thierry Reding wrote:
This commit enables NAND support on the Tamonten Evaluation Carrier and adds the corresponding device tree nodes. Furthermore, the U-Boot environment can now be stored in NAND.
diff --git a/include/configs/tec.h b/include/configs/tec.h
+/* Environment not stored */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */
I guess you also need to update the comment;-)
Hehe. Will do. =)
Thierry
+Scott
On Tue, Jul 31, 2012 at 7:21 AM, Thierry Reding thierry.reding@avionic-design.de wrote:
In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.
Signed-off-by: Thierry Reding thierry.reding@avionic-design.de
Acked-by: Simon Glass sjg@chromium.org
common/cmd_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_nand.c b/common/cmd_nand.c index a91ccf4..4367f5a 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
last = off;
datbuf = malloc(nand->writesize);oobbuf = malloc(nand->oobsize);
datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize); if (!datbuf || !oobbuf) { puts("No memory for page buffer\n"); return 1;-- 1.7.11.3
On 07/31/2012 12:21 AM, Thierry Reding wrote:
In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.
Signed-off-by: Thierry Reding thierry.reding@avionic-design.de
You probably want to CC the NAND maintainer, Scott Wood (I have here) so he can ack this or apply it.
common/cmd_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_nand.c b/common/cmd_nand.c index a91ccf4..4367f5a 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
last = off;
- datbuf = malloc(nand->writesize);
- oobbuf = malloc(nand->oobsize);
- datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
- oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize); if (!datbuf || !oobbuf) { puts("No memory for page buffer\n"); return 1;
On 07/31/2012 10:40 AM, Stephen Warren wrote:
On 07/31/2012 12:21 AM, Thierry Reding wrote:
In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.
Signed-off-by: Thierry Reding thierry.reding@avionic-design.de
You probably want to CC the NAND maintainer, Scott Wood (I have here) so he can ack this or apply it.
common/cmd_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_nand.c b/common/cmd_nand.c index a91ccf4..4367f5a 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
last = off;
- datbuf = malloc(nand->writesize);
- oobbuf = malloc(nand->oobsize);
- datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);
- oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize); if (!datbuf || !oobbuf) { puts("No memory for page buffer\n"); return 1;
Acked-by: Scott Wood scottwood@freescale.com
...though I'm still not fond of the idea that every user of an API has to know whether DMA might be used on the buffer.
-Scott
Thierry,
On Mon, Jul 30, 2012 at 11:21 PM, Thierry Reding thierry.reding@avionic-design.de wrote:
In order for cache invalidation and flushing to work properly, the data and OOB buffers must be aligned to full cache lines.
Signed-off-by: Thierry Reding thierry.reding@avionic-design.de
This patch, along with the Tegra: 'Enable NAND on TEC' patch, applied to u-boot-tegra/next. Thanks!
Tom
common/cmd_nand.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/cmd_nand.c b/common/cmd_nand.c index a91ccf4..4367f5a 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -48,8 +48,8 @@ static int nand_dump(nand_info_t *nand, ulong off, int only_oob, int repeat)
last = off;
datbuf = malloc(nand->writesize);oobbuf = malloc(nand->oobsize);
datbuf = memalign(ARCH_DMA_MINALIGN, nand->writesize);oobbuf = memalign(ARCH_DMA_MINALIGN, nand->oobsize); if (!datbuf || !oobbuf) { puts("No memory for page buffer\n"); return 1;-- 1.7.11.3
participants (5)
-
Scott Wood -
Simon Glass -
Stephen Warren -
Thierry Reding -
Tom Warren