In LS2080/LS2085, SFP is LE and Ver is 3.4 The base address is 0x01e80200 SFP will be used in Secure Boot to read fuses. Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes

arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++++ arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 3 +++ include/fsl_sfp.h | 3 ++- 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 49b113d..5a33ff1 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -67,6 +67,10 @@ /* SMMU Defintions */ #define SMMU_BASE 0x05000000 /* GR0 Base */

+/* SFP */ +#define CONFIG_SYS_FSL_SFP_VER_3_4 +#define CONFIG_SYS_FSL_SFP_LE + /* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 #define CCI_MN_RNF_NODEID_LIST 0x180 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 91f3ce8..f1b021f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -73,6 +73,9 @@ #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000) #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)

+/* SFP */ +#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) + /* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index 353a123..2976a2c 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -32,7 +32,8 @@ /* Number of SRKH registers */ #define NUM_SRKH_REGS 8

-#ifdef CONFIG_SYS_FSL_SFP_VER_3_2 +#if defined(CONFIG_SYS_FSL_SFP_VER_3_2) || \ + defined(CONFIG_SYS_FSL_SFP_VER_3_4) struct ccsr_sfp_regs { u32 ospr; /* 0x200 */ u32 ospr1; /* 0x204 */

For Secure Boot, a header is used to identify key table, signature and image address. For LS-CH3, there is a new header structure being used.

The following changes are there in the new header: 1) Currently IE Table (Key extension) feature is not supported 2) Single Key feature is not supported. Keys must be in table format. 3) Hence, SRK (Key table) is by default currently always present. 4) Max Key number has increase from 4 to 8. 8th Key is unrevockable. 5) New Barker Code is being used. Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes

Changes for v3: - No changes

arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +- arch/arm/include/asm/fsl_secure_boot.h | 4 ++ board/freescale/common/fsl_validate.c | 35 +++++++++++-- include/fsl_secboot_err.h | 3 ++ include/fsl_validate.h | 60 ++++++++++++++++++++--- 5 files changed, 91 insertions(+), 14 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 16f60a1..d2ea525 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -79,7 +79,8 @@ /* Security Monitor */ #define CONFIG_SYS_FSL_SEC_MON_LE

- +/* Secure Boot */ +#define CONFIG_ESBC_HDR_LS

/* Cache Coherent Interconnect */ #define CCI_MN_BASE 0x04000000 diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 0da0599..3e46c63 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -40,9 +40,13 @@ * The feature is only applicable in case of NOR boot and is * not applicable in case of RAMBOOT (NAND, SD, SPI). */ +#ifndef CONFIG_ESBC_HDR_LS +/* Current Key EXT feature not available in LS ESBC Header */ #define CONFIG_FSL_ISBC_KEY_EXT #endif

+#endif + #ifdef CONFIG_LS1043A /* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ #define CONFIG_ESBC_ADDR_64BIT diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 8fd6dd6..c12b9c9 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -35,7 +35,13 @@ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, };

static u8 hash_val[SHA256_BYTES]; + +#ifdef CONFIG_ESBC_HDR_LS +/* New Barker Code for LS ESBC Header */ +static const u8 barker_code[ESBC_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 }; +#else static const u8 barker_code[ESBC_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 }; +#endif

void branch_to_self(void) __attribute__ ((noreturn));

@@ -157,10 +163,15 @@ static int get_ie_info_addr(u32 *ie_addr) /* This function checks srk_table_flag in header and set/reset srk_flag.*/ static u32 check_srk(struct fsl_secboot_img_priv *img) { +#ifdef CONFIG_ESBC_HDR_LS + /* In LS, No SRK Flag as SRK is always present*/ + return 1; +#else if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) return 1;

return 0; +#endif }

/* This function returns ospr's key_revoc values.*/ @@ -223,6 +234,7 @@ static u32 read_validate_srk_tbl(struct fsl_secboot_img_priv *img) } #endif

+#ifndef CONFIG_ESBC_HDR_LS static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) { struct fsl_secboot_img_hdr *hdr = &img->hdr; @@ -238,6 +250,7 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img)

return 0; } +#endif /* CONFIG_ESBC_HDR_LS */

#if defined(CONFIG_FSL_ISBC_KEY_EXT) static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) @@ -388,6 +401,7 @@ void fsl_secboot_handle_error(int error) case ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD: case ERROR_ESBC_CLIENT_HEADER_SG_ESBC_EP: case ERROR_ESBC_CLIENT_HEADER_SG_ENTIRES_BAD: + case ERROR_KEY_TABLE_NOT_FOUND: #ifdef CONFIG_KEY_REVOCATION case ERROR_ESBC_CLIENT_HEADER_KEY_REVOKED: case ERROR_ESBC_CLIENT_HEADER_INVALID_SRK_NUM_ENTRY: @@ -536,11 +550,18 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) if (!key_hash && check_ie(img)) key_hash = 1; #endif - if (!key_hash) +#ifndef CONFIG_ESBC_HDR_LS +/* No single key support in LS ESBC header */ + if (!key_hash) { ret = algo->hash_update(algo, ctx, img->img_key, img->hdr.key_len, 0); + key_hash = 1; + } +#endif if (ret) return ret; + if (!key_hash) + return ERROR_KEY_TABLE_NOT_FOUND;

/* Update hash for actual Image */ ret = algo->hash_update(algo, ctx, @@ -626,8 +647,6 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) u8 *k, *s; u32 ret = 0;

-#ifdef CONFIG_KEY_REVOCATION -#endif int key_found = 0;

/* check barker code */ @@ -671,13 +690,17 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) key_found = 1; } #endif - +#ifndef CONFIG_ESBC_HDR_LS +/* Single Key Feature not available in LS ESBC Header */ if (key_found == 0) { ret = read_validate_single_key(img); if (ret != 0) return ret; key_found = 1; } +#endif + if (!key_found) + return ERROR_KEY_TABLE_NOT_FOUND;

/* check signaure */ if (get_key_len(img) == 2 * hdr->sign_len) { @@ -691,10 +714,12 @@ static int read_validate_esbc_client_header(struct fsl_secboot_img_priv *img) }

memcpy(&img->img_sign, esbc + hdr->psign, hdr->sign_len); - +/* No SG support in LS-CH3 */ +#ifndef CONFIG_ESBC_HDR_LS /* No SG support */ if (hdr->sg_flag) return ERROR_ESBC_CLIENT_HEADER_SG; +#endif

/* modulus most significant bit should be set */ k = (u8 *)&img->img_key; diff --git a/include/fsl_secboot_err.h b/include/fsl_secboot_err.h index afc50a8..95d890b 100644 --- a/include/fsl_secboot_err.h +++ b/include/fsl_secboot_err.h @@ -29,6 +29,7 @@ #define ERROR_ESBC_CLIENT_HEADER_INV_IE_ENTRY_KEYLEN 0x18 #define ERROR_IE_TABLE_NOT_FOUND 0x19 #define ERROR_ESBC_CLIENT_HEADER_KEY_LEN_NOT_TWICE_SIG_LEN 0x20 +#define ERROR_KEY_TABLE_NOT_FOUND 0x21 #define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_1 0x40 #define ERROR_ESBC_CLIENT_HEADER_KEY_MOD_2 0x80 #define ERROR_ESBC_CLIENT_HEADER_SIG_KEY_MOD 0x100 @@ -121,6 +122,8 @@ static const struct fsl_secboot_errcode fsl_secboot_errcodes[] = { "Wrong IE public key len in header" }, { ERROR_IE_TABLE_NOT_FOUND, "Information about IE Table missing" }, + { ERROR_KEY_TABLE_NOT_FOUND, + "No Key/ Key Table Found in header"}, { ERROR_ESBC_CLIENT_MAX, "NULL" } };

diff --git a/include/fsl_validate.h b/include/fsl_validate.h index 83efcf4..f812c1a 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -21,14 +21,6 @@

extern struct jobring jr;

-#ifdef CONFIG_KEY_REVOCATION -/* Srk table and key revocation check */ -#define SRK_FLAG 0x01 -#define UNREVOCABLE_KEY 4 -#define ALIGN_REVOC_KEY 3 -#define MAX_KEY_ENTRIES 4 -#endif - /* Barker code size in bytes */ #define ESBC_BARKER_LEN 4 /* barker code length in ESBC uboot client */ /* header */ @@ -39,6 +31,47 @@ extern struct jobring jr; /* Maximum number of SG entries allowed */ #define MAX_SG_ENTRIES 8

+/* Different Header Struct for LS-CH3 */ +#ifdef CONFIG_ESBC_HDR_LS +struct fsl_secboot_img_hdr { + u8 barker[ESBC_BARKER_LEN]; /* barker code */ + u32 srk_tbl_off; + struct { + u8 num_srk; + u8 srk_sel; + u8 reserve; + u8 ie_flag; + } len_kr; + + u32 uid_flag; + + u32 psign; /* signature offset */ + u32 sign_len; /* length of the signature in bytes */ + + u64 pimg64; /* 64 bit pointer to ESBC Image */ + u32 img_size; /* ESBC client image size in bytes */ + u32 ie_key_sel; + + u32 fsl_uid_0; + u32 fsl_uid_1; + u32 oem_uid_0; + u32 oem_uid_1; + u32 oem_uid_2; + u32 oem_uid_3; + u32 oem_uid_4; + u32 reserved1[3]; +}; + +#ifdef CONFIG_KEY_REVOCATION +/* Srk table and key revocation check */ +#define UNREVOCABLE_KEY 8 +#define ALIGN_REVOC_KEY 7 +#define MAX_KEY_ENTRIES 8 +#endif + + +#else /* CONFIG_ESBC_HDR_LS */ + /* * ESBC uboot client header structure. * The struct contain the following fields @@ -109,6 +142,17 @@ struct fsl_secboot_img_hdr { u32 ie_key_sel; };

+#ifdef CONFIG_KEY_REVOCATION +/* Srk table and key revocation check */ +#define SRK_FLAG 0x01 +#define UNREVOCABLE_KEY 4 +#define ALIGN_REVOC_KEY 3 +#define MAX_KEY_ENTRIES 4 +#endif + +#endif /* CONFIG_ESBC_HDR_LS */ + + #if defined(CONFIG_FSL_ISBC_KEY_EXT) struct ie_key_table { u32 key_len;

During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it is executed. This requires a header for bootscript.

When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script.

For ls2080/5, NOR memory map is different from earlier arm SoCs. So a new address on NOR is used for this bootscript header. (0x583920000). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes

arch/arm/include/asm/fsl_secure_boot.h | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index e65caed..7c55ea1 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -63,7 +63,11 @@ "setenv hwconfig 'fsl_ddr:ctlr_intlv=null,bank_intlv=null';"

/* The address needs to be modified according to NOR memory map */ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x583920000 +#else #define CONFIG_BOOTSCRIPT_HDR_ADDR 0x600a0000 +#endif

#include <config_fsl_chain_trust.h> #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */

"fdt_high" env variable has been changed to 0xa0000000 for ls2080a and ls2085a during Secure Boot. This env_varible is used to specify the upper limit to be used for copying flat device tree. This address must be visible to kernel.

The "fdt_high" value has been set during Secure Boot to same value as it's default value during non-secure boot.

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes

arch/arm/include/asm/fsl_secure_boot.h | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 7ab9623..eafdc0b 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -57,10 +57,17 @@ #define CONFIG_ESBC_ADDR_64BIT #endif

+#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +#define CONFIG_EXTRA_ENV \ + "setenv fdt_high 0xa0000000;" \ + "setenv initrd_high 0xcfffffff;" \ + "setenv hwconfig 'fsl_ddr:ctlr_intlv=null,bank_intlv=null';" +#else #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xcfffffff;" \ "setenv initrd_high 0xcfffffff;" \ "setenv hwconfig 'fsl_ddr:ctlr_intlv=null,bank_intlv=null';" +#endif

/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/

During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs to be put in Bypass mode in uboot to enable CAAM transcations to pass through.

During Nonsecure Boot, SP BootROM doesn't enable SMMU and at reset SMMU is in bypass mode. Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes

arch/arm/cpu/armv8/fsl-layerscape/soc.c | 18 +++++++++++++++++- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index d97a445..c52fd69 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -151,7 +151,14 @@ static void erratum_a009203(void) #endif #endif } - +void bypass_smmu(void) +{ + u32 val; + val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_SCR0, val); + val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); + out_le32(SMMU_NSCR0, val); +} void fsl_lsch3_early_init_f(void) { erratum_a008751(); @@ -160,6 +167,15 @@ void fsl_lsch3_early_init_f(void) erratum_a009203(); erratum_a008514(); erratum_a008336(); +#ifdef CONFIG_CHAIN_OF_TRUST + /* In case of Secure Boot, the IBR configures the SMMU + * to allow only Secure transactions. + * SMMU must be reset in bypass mode. + * Set the ClientPD bit and Clear the USFCFG Bit + */ + if (fsl_check_boot_mode_secure() == 1) + bypass_smmu(); +#endif }

#ifdef CONFIG_SCSI_AHCI_PLAT diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 1fc51e0..06d4856 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -83,6 +83,21 @@ /* Security Monitor */ #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)

+/* MMU 500 */ +#define SMMU_SCR0 (SMMU_BASE + 0x0) +#define SMMU_SCR1 (SMMU_BASE + 0x4) +#define SMMU_SCR2 (SMMU_BASE + 0x8) +#define SMMU_SACR (SMMU_BASE + 0x10) +#define SMMU_IDR0 (SMMU_BASE + 0x20) +#define SMMU_IDR1 (SMMU_BASE + 0x24) + +#define SMMU_NSCR0 (SMMU_BASE + 0x400) +#define SMMU_NSCR2 (SMMU_BASE + 0x408) +#define SMMU_NSACR (SMMU_BASE + 0x410) + +#define SCR0_CLIENTPD_MASK 0x00000001 +#define SCR0_USFCFG_MASK 0x00000400 +

/* PCIe */ #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)

To solve CAAM coherency issue on ls2080a and ls2085a. When Caches are enabled and CAAM's DMA's AXI transcations are not made cacheable, Core reads/write data from/to Caches and CAAM does from Main Memory. This forces data flushes to synchronize various data structures But even if any data in proximity of these structures is read by core, these structures again are fetched in caches.

To avoid this problem, either all the data that CAAM accesses can be made cache line aligned or CAAM transcations can be made cacheable.

So, this commit makes CAAM transcations as Write Back with Write and Read Allocate. Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes

drivers/crypto/fsl/jr.c | 13 +++++++++++++ drivers/crypto/fsl/jr.h | 3 +++ 2 files changed, 16 insertions(+)

diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index b8c0c0a..01d9967 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -539,7 +539,20 @@ int sec_init(void) uint32_t liodn_s; #endif

+ /* + * Modifying CAAM Read/Write Attributes + * For LS2080A and LS2085A + * For AXI Write - Cacheable, Write Back, Write allocate + * For AXI Read - Cacheable, Read allocate + * Only For LS2080a and LS2085a, to solve CAAM coherency issues + */ +#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) + mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT); + mcr = (mcr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT); +#else mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); +#endif + #ifdef CONFIG_PHYS_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index 5899696..1f2e324 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -23,6 +23,9 @@ #define MCFGR_PS_SHIFT 16 #define MCFGR_AWCACHE_SHIFT 8 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) +#define MCFGR_ARCACHE_SHIFT 12 +#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) + #define JR_INTMASK 0x00000001 #define JRCR_RESET 0x01 #define JRINT_ERR_HALT_INPROGRESS 0x4

In case of fatal failure during secure boot execution (e.g. header not found) it is needed that the execution stops. Earlier, we were asserting reset request in case in case of failure. But if the RESET_REQ is not tied off to HRESET, this allows the execution to continue.

This can either be taken care in bootscript (Execute esbc_halt command in case of image verification process) or it can be taken care in Uboot Code.

Doing the latter via a esbc_halt. Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: - No changes

board/freescale/common/cmd_esbc_validate.c | 2 +- board/freescale/common/fsl_validate.c | 5 +++++ include/fsl_validate.h | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/board/freescale/common/cmd_esbc_validate.c b/board/freescale/common/cmd_esbc_validate.c index dfa3e21..375bc24 100644 --- a/board/freescale/common/cmd_esbc_validate.c +++ b/board/freescale/common/cmd_esbc_validate.c @@ -8,7 +8,7 @@ #include <command.h> #include <fsl_validate.h>

-static int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, +int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (fsl_check_boot_mode_secure() == 0) { diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index c12b9c9..95059c7 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -325,6 +325,8 @@ static void fsl_secboot_header_verification_failure(void)

printf("Generating reset request\n"); do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); }

/* @@ -355,6 +357,9 @@ static void fsl_secboot_image_verification_failure(void)

printf("Generating reset request\n"); do_reset(NULL, 0, 0, NULL); + /* If reset doesn't coocur, halt execution */ + do_esbc_halt(NULL, 0, 0, NULL); + } else { change_sec_mon_state(HPSR_SSM_ST_TRUST, HPSR_SSM_ST_NON_SECURE); diff --git a/include/fsl_validate.h b/include/fsl_validate.h index f812c1a..ff6f6b7 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -242,6 +242,9 @@ struct fsl_secboot_img_priv { uint32_t img_size; /* ESBC Image Size */ };

+int do_esbc_halt(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]); + int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, uintptr_t img_loc); int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc,

For validating images from uboot (Such as Kernel Image), either keys from SoC fuses can be used or keys from a veriied table of public keys can be used. The latter feature is called IE Key Extension Feature.

For earlier SoCs, BootROM used to verify IE Key Table and then write the address of this table in a secure register (SCRATCHREG). But in LS2088 and LS2085, no such secure registers are available. Hence IE Table is left to be verified by Uboot.

The new procedure is to first verify IE table using Keys stored in fuses, and then use the keys in this table to verify further images. So the steps are:

1) Verify IE Table (If "IE Table Flag" set in any image i.e. Verify IE Table only when any image needs IE Table's Key to be verified) 2) Install IE table. (To be used across verification of multiple images. Stored in a static global structure.) 3) If IE flag enabled in header of any image, Use keys from IE table, otherwise use keys tied up with SoC's fuses (SRK).

The address of IE Table HDR is fixed for NOR. In case of boot from other devices, IE Table and it's Header needs to be copied to an XIP Memory.

Signed-off-by: Aneesh Bansal aneesh.bansal@nxp.com Signed-off-by: Saksham Jain saksham.jain@nxp.com --- Changes for v2: - No changes Changes for v3: -changes to remove compliation warning for various platforms

arch/arm/include/asm/fsl_secure_boot.h | 6 +-- board/freescale/common/fsl_validate.c | 97 ++++++++++++++++++++++++++++------ include/fsl_validate.h | 23 +++++++- 3 files changed, 105 insertions(+), 21 deletions(-)

diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index eafdc0b..061c9f5 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -41,11 +41,11 @@ * in boot ROM of the SoC. * The feature is only applicable in case of NOR boot and is * not applicable in case of RAMBOOT (NAND, SD, SPI). + * For LS, this feature is available for all device if IE Table + * is copied to XIP memory + * Also, for LS, ISBC doesn't verify this table. */ -#ifndef CONFIG_ESBC_HDR_LS -/* Current Key EXT feature not available in LS ESBC Header */ #define CONFIG_FSL_ISBC_KEY_EXT -#endif

#endif

diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 64e4e30..248a759 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -27,6 +27,10 @@ #define CHECK_KEY_LEN(key_len) (((key_len) == 2 * KEY_SIZE_BYTES / 4) || \ ((key_len) == 2 * KEY_SIZE_BYTES / 2) || \ ((key_len) == 2 * KEY_SIZE_BYTES)) +#if defined(CONFIG_FSL_ISBC_KEY_EXT) +/* Global data structure */ +static struct fsl_secboot_glb glb; +#endif

/* This array contains DER value for SHA-256 */ static const u8 hash_identifier[] = { 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, @@ -60,7 +64,7 @@ self: #if defined(CONFIG_FSL_ISBC_KEY_EXT) static u32 check_ie(struct fsl_secboot_img_priv *img) { - if (img->hdr.ie_flag) + if (img->hdr.ie_flag & IE_FLAG_MASK) return 1;

return 0; @@ -119,7 +123,8 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) } #endif

-static int get_ie_info_addr(u32 *ie_addr) +#if !defined(CONFIG_ESBC_HDR_LS) +static int get_ie_info_addr(uintptr_t *ie_addr) { struct fsl_secboot_img_hdr *hdr; struct fsl_secboot_sg_table *sg_tbl; @@ -147,16 +152,17 @@ static int get_ie_info_addr(u32 *ie_addr)

/* IE Key Table is the first entry in the SG Table */ #if defined(CONFIG_MPC85xx) - *ie_addr = (sg_tbl->src_addr & ~(CONFIG_SYS_PBI_FLASH_BASE)) + - flash_base_addr; + *ie_addr = (uintptr_t)((sg_tbl->src_addr & + ~(CONFIG_SYS_PBI_FLASH_BASE)) + + flash_base_addr); #else - *ie_addr = sg_tbl->src_addr; + *ie_addr = (uintptr_t)sg_tbl->src_addr; #endif

- debug("IE Table address is %x\n", *ie_addr); + debug("IE Table address is %lx\n", *ie_addr); return 0; } - +#endif /* CONFIG_ESBC_HDR_LS */ #endif

#ifdef CONFIG_KEY_REVOCATION @@ -164,7 +170,10 @@ static int get_ie_info_addr(u32 *ie_addr) static u32 check_srk(struct fsl_secboot_img_priv *img) { #ifdef CONFIG_ESBC_HDR_LS - /* In LS, No SRK Flag as SRK is always present*/ + /* In LS, No SRK Flag as SRK is always present if IE not present*/ +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + return !check_ie(img); +#endif return 1; #else if (img->hdr.len_kr.srk_table_flag & SRK_FLAG) @@ -253,14 +262,51 @@ static u32 read_validate_single_key(struct fsl_secboot_img_priv *img) #endif /* CONFIG_ESBC_HDR_LS */

#if defined(CONFIG_FSL_ISBC_KEY_EXT) + +#if defined(CONFIG_ESBC_HDR_LS) +static void install_ie_tbl(uintptr_t ie_tbl_addr, + struct fsl_secboot_img_priv *img) +{ + /* Copy IE tbl to Global Data */ + memcpy(&glb.ie_tbl, (u8 *)ie_tbl_addr, sizeof(struct ie_key_info)); + img->ie_addr = (uintptr_t)&glb.ie_tbl; + glb.ie_addr = img->ie_addr; +} +#endif + static u32 read_validate_ie_tbl(struct fsl_secboot_img_priv *img) { struct fsl_secboot_img_hdr *hdr = &img->hdr; u32 ie_key_len, ie_revoc_flag, ie_num; struct ie_key_info *ie_info;

- if (get_ie_info_addr(&img->ie_addr)) - return ERROR_IE_TABLE_NOT_FOUND; +/* For LS, IE Table is installed as a separate image. + * It is not verified by ISBC. + */ + if (!img->ie_addr) +#if defined(CONFIG_ESBC_HDR_LS) + /* Verify and Install IE Table */ + debug("Verifying IE Table\n"); + + int ret; + uintptr_t ie_tbl_addr = 0; + ret = fsl_secboot_validate(IE_TABLE_HDR_ADR, NULL, + &ie_tbl_addr); + if (ret) { + printf("IE Table Verification Failed\n"); + return ret; + } else { + printf("IE Table Verified Successfully\n"); + /* If the image is IE Table, + * then install that IE Table for + * future verification process. + */ + install_ie_tbl(ie_tbl_addr, img); + } +#else + if (get_ie_info_addr(&img->ie_addr)) + return ERROR_IE_TABLE_NOT_FOUND; +#endif ie_info = (struct ie_key_info *)(uintptr_t)img->ie_addr; if (ie_info->num_keys == 0 || ie_info->num_keys > 32) return ERROR_ESBC_CLIENT_HEADER_INVALID_IE_NUM_ENTRY; @@ -810,6 +856,26 @@ static int calculate_cmp_img_sig(struct fsl_secboot_img_priv *img)

return 0; } +/* Function to initialize img priv and global data structure + */ +static int secboot_init(struct fsl_secboot_img_priv **img_ptr) +{ + *img_ptr = malloc(sizeof(struct fsl_secboot_img_priv)); + + struct fsl_secboot_img_priv *img = *img_ptr; + + if (!img) + return -ENOMEM; + memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + if (glb.ie_addr) + img->ie_addr = glb.ie_addr; +#endif + return 0; +} + + /* haddr - Address of the header of image to be validated. * arg_hash_str - Option hash string. If provided, this * overides the key hash in the SFP fuses. @@ -863,12 +929,9 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, hash_cmd = 1; }

- img = malloc(sizeof(struct fsl_secboot_img_priv)); - - if (!img) - return -1; - - memset(img, 0, sizeof(struct fsl_secboot_img_priv)); + ret = secboot_init(&img); + if (ret) + goto exit;

/* Update the information in Private Struct */ hdr = &img->hdr; @@ -923,5 +986,7 @@ int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, }

exit: + /* Free Img as it was malloc'ed*/ + free(img); return ret; } diff --git a/include/fsl_validate.h b/include/fsl_validate.h index a71e1ce..7aae5c9 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -40,8 +40,8 @@ struct fsl_secboot_img_hdr { u8 num_srk; u8 srk_sel; u8 reserve; - u8 ie_flag; } len_kr; + u8 ie_flag;

u32 uid_flag;

@@ -69,6 +69,10 @@ struct fsl_secboot_img_hdr { #define MAX_KEY_ENTRIES 8 #endif

+#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#define IE_FLAG_MASK 0x1 +#define IE_TABLE_HDR_ADR 0x5839c0000 +#endif

#else /* CONFIG_ESBC_HDR_LS */

@@ -150,6 +154,10 @@ struct fsl_secboot_img_hdr { #define MAX_KEY_ENTRIES 4 #endif

+#if defined(CONFIG_FSL_ISBC_KEY_EXT) +#define IE_FLAG_MASK 0xFFFFFFFF +#endif + #endif /* CONFIG_ESBC_HDR_LS */

@@ -202,6 +210,17 @@ struct fsl_secboot_sg_table { }; #endif

+/* ESBC global structure. + * Data to be used across verification of different images. + * Stores follwoing Data: + * IE Table + */ +struct fsl_secboot_glb { +#if defined(CONFIG_FSL_ISBC_KEY_EXT) + uintptr_t ie_addr; + struct ie_key_info ie_tbl; +#endif +}; /* * ESBC private structure. * Private structure used by ESBC to store following fields @@ -213,7 +232,7 @@ struct fsl_secboot_sg_table { */ struct fsl_secboot_img_priv { uint32_t hdr_location; - u32 ie_addr; + uintptr_t ie_addr; u32 key_len; struct fsl_secboot_img_hdr hdr;