[U-Boot] [PATCH 0/3] fpga: zynqmp: Fpga changes
Hi,
these patches are syncing latest firmware expectation and showing information about fpga status.
Thanks, Michal
Nitin Jain (1): fpga: zynqmp: Add support to get the PCAP status for fpga info command
Siva Durga Prasad Paladugu (2): fpga: zynqmp: Update zynqmp_load() as per latest xilfpga fpga: zynqmp: Fix the nonsecure bitstream loading issue
arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 ++ drivers/fpga/zynqmppl.c | 28 +++++++++++++++++++++------- include/zynqmppl.h | 1 + 3 files changed, 24 insertions(+), 7 deletions(-)
From: Nitin Jain nitin.jain@xilinx.com
This patch adds support for ZynqMP platform to print FPGA PCAP status for "fpga status" command.
Signed-off-by: Nitin Jain nitinj@xilinx.com Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
drivers/fpga/zynqmppl.c | 14 ++++++++++++++ include/zynqmppl.h | 1 + 2 files changed, 15 insertions(+)
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 57a4e6c88e7a..80388ae7f2cf 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -224,6 +224,20 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return ret; }
+static int zynqmp_pcap_info(xilinx_desc *desc) +{ + int ret; + u32 ret_payload[PAYLOAD_ARG_CNT]; + + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0, + 0, ret_payload); + if (!ret) + printf("PCAP status\t0x%x\n", ret_payload[1]); + + return ret; +} + struct xilinx_fpga_op zynqmp_op = { .load = zynqmp_load, + .info = zynqmp_pcap_info, }; diff --git a/include/zynqmppl.h b/include/zynqmppl.h index 4c8c2f88f04c..8b3ce8ef7706 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -12,6 +12,7 @@
#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 #define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 +#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017 #define ZYNQMP_FPGA_OP_INIT (1 << 0) #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2)
From: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com
Latest xilfpga expects to set BIT5 of flags for nonsecure bitsream and also expects length in bytes instead of words This patch does the same.
Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
arch/arm/include/asm/arch-zynqmp/sys_proto.h | 2 ++ drivers/fpga/zynqmppl.c | 6 +----- 2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index ad3dc9aba50d..3daf0e81d80c 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -14,6 +14,8 @@ #define ZYNQMP_SIP_SVC_PM_SECURE_IMG_LOAD 0xC200002D #define KEY_PTR_LEN 32
+#define ZYNQMP_FPGA_BIT_NS 5 + enum { IDCODE, VERSION, diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 80388ae7f2cf..aae0efc7348e 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -209,13 +209,9 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, debug("%s called!\n", __func__); flush_dcache_range(bin_buf, bin_buf + bsize);
- if (bsize % 4) - bsize = bsize / 4 + 1; - else - bsize = bsize / 4; - buf_lo = (u32)bin_buf; buf_hi = upper_32_bits(bin_buf); + bstype |= BIT(ZYNQMP_FPGA_BIT_NS); ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, bstype, ret_payload); if (ret)
On Wed, Mar 28, 2018 at 9:30 AM, Michal Simek michal.simek@xilinx.com wrote:
From: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com
Latest xilfpga expects to set BIT5 of flags for nonsecure bitsream and also expects length in bytes instead of words This patch does the same.
Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com
Reviewed-by: Joe Hershberger joe.hershberger@ni.com
From: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com
Xilfpga library expects the size of bitstream in a pointer but currenly we are passing the size as a value. This patch fixes this issue.
Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com Signed-off-by: Nava kishore Manne navam@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---
drivers/fpga/zynqmppl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index aae0efc7348e..43e8b2520e35 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -11,6 +11,7 @@ #include <zynqmppl.h> #include <linux/sizes.h> #include <asm/arch/sys_proto.h> +#include <memalign.h>
#define DUMMY_WORD 0xffffffff
@@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype) { + ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1); u32 swap; ulong bin_buf; int ret; @@ -205,15 +207,17 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return FPGA_FAIL;
bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap); + bsizeptr = (u32 *)&bsize;
debug("%s called!\n", __func__); flush_dcache_range(bin_buf, bin_buf + bsize); + flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t));
buf_lo = (u32)bin_buf; buf_hi = upper_32_bits(bin_buf); bstype |= BIT(ZYNQMP_FPGA_BIT_NS); - ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize, - bstype, ret_payload); + ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, + (u32)(uintptr_t)bsizeptr, bstype, ret_payload); if (ret) debug("PL FPGA LOAD fail\n");
On 03/28/2018 04:30 PM, Michal Simek wrote:
From: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com
Xilfpga library expects the size of bitstream in a pointer but currenly we are passing the size as a value. This patch fixes this issue.
This breaks fpga loadb on zynqmp with FSBL 0.3 for me, so please revert. The commit message is not clear on what the "issue" is or whether the FSBL version has any relevance or whether the ABI changed somewhere in the xilinx blobs, but it is clear reverting this patch fixes an issue for me.
Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com Signed-off-by: Nava kishore Manne navam@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com
drivers/fpga/zynqmppl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index aae0efc7348e..43e8b2520e35 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -11,6 +11,7 @@ #include <zynqmppl.h> #include <linux/sizes.h> #include <asm/arch/sys_proto.h> +#include <memalign.h>
#define DUMMY_WORD 0xffffffff
@@ -195,6 +196,7 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf, static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, bitstream_type bstype) {
- ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1); u32 swap; ulong bin_buf; int ret;
@@ -205,15 +207,17 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, return FPGA_FAIL;
bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
bsizeptr = (u32 *)&bsize;
debug("%s called!\n", __func__); flush_dcache_range(bin_buf, bin_buf + bsize);
flush_dcache_range((ulong)bsizeptr, (ulong)bsizeptr + sizeof(size_t));
This will trigger unaligned cache flush warning, FYI. And the buffer is u32, while here you use size_t.
buf_lo = (u32)bin_buf; buf_hi = upper_32_bits(bin_buf); bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
- ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi, bsize,
bstype, ret_payload);
- ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
(u32)(uintptr_t)bsizeptr, bstype, ret_payload);
participants (3)
-
Joe Hershberger -
Marek Vasut -
Michal Simek