[PATCH v7 00/12] Support OF_UPSTREAM for StarFive JH7110
This patchset add OF_UPSTREAM support for StarFive JH7110 based boards. All the JH7110 based boards can use the DT from upstreaming linux kernel. The v1.3b board device tree is set as the default device tree. Support CONFIG_MULTI_DTB_FIT and the SPL selects the correct U-Boot dtb using the EEPROM information.
Note: 1. Mars CM (lite) are missing upstream dts and so are detected but not supported in this series. Users of Mars CM and Mars CM Lite may stay with U-Boot v2024.10 until this is resolved.
2. Property values of network phy0/1 for all JH7110 based boards now follow the upstream dts.
Changes since v6: - Drop the "snps,dw-mshc" override of compatible in patch 2, then add "starfive,jh7110-mmc" compatible in mmc driver to match upstream DT. - Delete newline at end of Mars DT file in patch 5. - Sort OF_LIST in patch 7. - Sort items of images and configurations in patch 8.
Changes since v5: - In patch 2, drop the override of rx-internal-delay-ps on phy0 and phy1. - In patch 5, drop "/delete-property/ motorcomm,tx-clk-10-inverted;" for Mars network phy0. - In patch 8, rename fdt and conf based on the compatible identifier of boards.
Changes since v4: - Merge patch 2, 3, 5 into patch 1, ensuring git bisect works. - Add a new patch to sort the list of JH7110 imply statements. - Drop the reparent of clock JH7110_AONCLK_APB_FUNC in patch 4, which is unnecessary and will cause errors in gmac0 initialization.
Changes since v3: - Add detection for Milk-V Mars CM (lite) boards in patch 13.
Changes since v2: - Drop patch 1, because the riscv of_upstream Makefile is created by Conor in commit 239e4705099c. - Drop phy0 rx delay for milkv u-boot dtsi in patch 9. - Add a Fixes tag for patch 13. - In patch 14, the PCB version is only obtained when the product_id is VF7110. Improve the commit messages.
Changes since v1: - Drop patch 12. - Modify patch 11 and add three new patches to support CONFIG_MULTI_DTB_FIT. The SPL selects the correct U-Boot dtb using the EEPROM information.
History: v6: https://lore.kernel.org/all/20241125003205.75327-1-hal.feng@starfivetech.com... v5: https://lore.kernel.org/all/20241119020425.51989-1-hal.feng@starfivetech.com... v4: https://lore.kernel.org/all/20241111020808.38974-1-hal.feng@starfivetech.com... v3: https://lore.kernel.org/all/20241105034328.56439-1-hal.feng@starfivetech.com... v2: https://lore.kernel.org/all/20241028015847.42344-1-hal.feng@starfivetech.com... v1: https://lore.kernel.org/all/20240930155919.111738-1-hal.feng@starfivetech.co...
Hal Feng (12): dts: starfive: Switch to using upstream DT riscv: dts: jh7110: Make u-boot device trees adapting to upstream DT mmc: dw_mmc: Add "starfive,jh7110-mmc" compatible to match upstream DT pcie: starfive: Make the driver compatible with upstream DT riscv: dts: jh7110: Move common code to the new jh7110-common-u-boot.dtsi riscv: dts: jh7110: Add u-boot device tree for JH7110 based boards board: starfive: spl: Drop the unneeded DT modification code configs: visionfive2: Enable MULTI_DTB_FIT for JH7110 based board DT riscv: dts: jh7110: Support multiple DTBs in a Fit image board: starfive: spl: Fix the wrong use of CONFIG_IS_ENABLED() board: starfive: spl: Support multiple DTBs for JH7110 based boards riscv: cpu: jh7110: Sort the list of imply statements
arch/riscv/cpu/jh7110/Kconfig | 19 +- arch/riscv/dts/Makefile | 1 - arch/riscv/dts/jh7110-common-u-boot.dtsi | 196 +++++ arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 6 + .../dts/jh7110-pine64-star64-u-boot.dtsi | 6 + .../jh7110-starfive-visionfive-2-u-boot.dtsi | 117 --- ...10-starfive-visionfive-2-v1.2a-u-boot.dtsi | 6 + ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 6 + .../dts/jh7110-starfive-visionfive-2.dts | 11 - .../dts/jh7110-starfive-visionfive-2.dtsi | 380 --------- arch/riscv/dts/jh7110-u-boot.dtsi | 36 +- arch/riscv/dts/jh7110.dtsi | 761 ------------------ board/starfive/visionfive2/spl.c | 391 +-------- configs/starfive_visionfive2_defconfig | 4 +- drivers/clk/starfive/clk-jh7110-pll.c | 6 +- drivers/clk/starfive/clk-jh7110.c | 44 +- drivers/mmc/snps_dw_mmc.c | 1 + drivers/pci/pcie_starfive_jh7110.c | 59 +- .../dt-bindings/clock/starfive,jh7110-crg.h | 258 ------ .../dt-bindings/reset/starfive,jh7110-crg.h | 183 ----- 20 files changed, 356 insertions(+), 2135 deletions(-) create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dts delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi delete mode 100644 arch/riscv/dts/jh7110.dtsi delete mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h delete mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h
base-commit: acab6e78aca767ef71470871842e5c090e3672c7
Enable OF_UPSTREAM to use upstream DT and add starfive/ prefix to the DEFAULT_DEVICE_TREE. Rename jh7110-starfive-visionfive-2-u-boot.dtsi to jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi and set the v1.3b device tree as the default device tree.
Drop redundant DT files from arch/riscv/dts/ and redundant clock and reset definitions from include/dt-bindings/.
Since the old clock definitions is a little different from those in upstream Linux, update the clock definitions in clock drivers accordingly.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Acked-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Hal Feng hal.feng@starfivetech.com --- arch/riscv/cpu/jh7110/Kconfig | 1 + arch/riscv/dts/Makefile | 1 - ...0-starfive-visionfive-2-v1.3b-u-boot.dtsi} | 0 .../dts/jh7110-starfive-visionfive-2.dts | 11 - .../dts/jh7110-starfive-visionfive-2.dtsi | 380 --------- arch/riscv/dts/jh7110-u-boot.dtsi | 2 +- arch/riscv/dts/jh7110.dtsi | 761 ------------------ configs/starfive_visionfive2_defconfig | 2 +- drivers/clk/starfive/clk-jh7110-pll.c | 6 +- drivers/clk/starfive/clk-jh7110.c | 44 +- .../dt-bindings/clock/starfive,jh7110-crg.h | 258 ------ .../dt-bindings/reset/starfive,jh7110-crg.h | 183 ----- 12 files changed, 28 insertions(+), 1621 deletions(-) rename arch/riscv/dts/{jh7110-starfive-visionfive-2-u-boot.dtsi => jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi} (100%) delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dts delete mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi delete mode 100644 arch/riscv/dts/jh7110.dtsi delete mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h delete mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index e5549a01b8..9904a60ddd 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -19,6 +19,7 @@ config STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD imply MMC_SPI + imply OF_UPSTREAM imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply SIFIVE_CACHE imply SIFIVE_CCACHE diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index de356584bf..07ebe530bd 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -7,7 +7,6 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb -dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi similarity index 100% rename from arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi rename to arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2.dts deleted file mode 100644 index 288ea39493..0000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dts +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2023 StarFive Technology Co., Ltd. - */ - -/dts-v1/; -#include "jh7110-starfive-visionfive-2.dtsi" - -/ { - compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; -}; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi deleted file mode 100644 index e11babc1cd..0000000000 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ /dev/null @@ -1,380 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -/dts-v1/; - -#include "jh7110.dtsi" -#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h> -#include <dt-bindings/gpio/gpio.h> -/ { - aliases { - serial0 = &uart0; - spi0 = &qspi; - mmc0 = &mmc0; - mmc1 = &mmc1; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c5 = &i2c5; - i2c6 = &i2c6; - ethernet0 = &gmac0; - ethernet1 = &gmac1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - cpus { - timebase-frequency = <4000000>; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x2 0x0>; - }; - - gpio-restart { - compatible = "gpio-restart"; - gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>; - }; -}; - -&osc { - clock-frequency = <24000000>; -}; - -&rtc_osc { - clock-frequency = <32768>; -}; - -&gmac0_rmii_refin { - clock-frequency = <50000000>; -}; - -&gmac0_rgmii_rxin { - clock-frequency = <125000000>; -}; - -&gmac1_rmii_refin { - clock-frequency = <50000000>; -}; - -&gmac1_rgmii_rxin { - clock-frequency = <125000000>; -}; - -&i2stx_bclk_ext { - clock-frequency = <12288000>; -}; - -&i2stx_lrck_ext { - clock-frequency = <192000>; -}; - -&i2srx_bclk_ext { - clock-frequency = <12288000>; -}; - -&i2srx_lrck_ext { - clock-frequency = <192000>; -}; - -&tdm_ext { - clock-frequency = <49152000>; -}; - -&mclk_ext { - clock-frequency = <12288000>; -}; - -&uart0 { - reg-offset = <0>; - current-speed = <115200>; - clock-frequency = <24000000>; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; -}; - -&i2c2 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - status = "okay"; -}; - -&i2c5 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - status = "okay"; - - pmic@36 { - compatible = "x-powers,axp15060"; - reg = <0x36>; - }; - - eeprom@50 { - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&i2c6 { - clock-frequency = <100000>; - i2c-sda-hold-time-ns = <300>; - i2c-sda-falling-time-ns = <510>; - i2c-scl-falling-time-ns = <510>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins>; - status = "okay"; -}; - -&sysgpio { - status = "okay"; - uart0_pins: uart0-0 { - tx-pins { - pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, - GPOEN_ENABLE, - GPI_NONE)>; - bias-disable; - drive-strength = <12>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - rx-pins { - pinmux = <GPIOMUX(6, GPOUT_LOW, - GPOEN_DISABLE, - GPI_SYS_UART0_RX)>; - bias-disable; /* external pull-up */ - drive-strength = <2>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; - }; - - i2c0_pins: i2c0-0 { - i2c-pins { - pinmux = <GPIOMUX(57, GPOUT_LOW, - GPOEN_SYS_I2C0_CLK, - GPI_SYS_I2C0_CLK)>, - <GPIOMUX(58, GPOUT_LOW, - GPOEN_SYS_I2C0_DATA, - GPI_SYS_I2C0_DATA)>; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - i2c2_pins: i2c2-0 { - i2c-pins { - pinmux = <GPIOMUX(3, GPOUT_LOW, - GPOEN_SYS_I2C2_CLK, - GPI_SYS_I2C2_CLK)>, - <GPIOMUX(2, GPOUT_LOW, - GPOEN_SYS_I2C2_DATA, - GPI_SYS_I2C2_DATA)>; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - i2c5_pins: i2c5-0 { - i2c-pins { - pinmux = <GPIOMUX(19, GPOUT_LOW, - GPOEN_SYS_I2C5_CLK, - GPI_SYS_I2C5_CLK)>, - <GPIOMUX(20, GPOUT_LOW, - GPOEN_SYS_I2C5_DATA, - GPI_SYS_I2C5_DATA)>; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - i2c6_pins: i2c6-0 { - i2c-pins { - pinmux = <GPIOMUX(16, GPOUT_LOW, - GPOEN_SYS_I2C6_CLK, - GPI_SYS_I2C6_CLK)>, - <GPIOMUX(17, GPOUT_LOW, - GPOEN_SYS_I2C6_DATA, - GPI_SYS_I2C6_DATA)>; - bias-disable; /* external pull-up */ - input-enable; - input-schmitt-enable; - }; - }; - - mmc0_pins: mmc0-pins { - mmc0-pins-rest { - pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, - GPOEN_ENABLE, GPI_NONE)>; - bias-pull-up; - drive-strength = <12>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - }; - - mmc1_pins: mmc1-pins { - mmc1-pins0 { - pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK, - GPOEN_ENABLE, GPI_NONE)>; - bias-pull-up; - drive-strength = <12>; - input-disable; - input-schmitt-disable; - slew-rate = <0>; - }; - - mmc1-pins1 { - pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD, - GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>, - <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0, - GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>, - <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1, - GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>, - <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2, - GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>, - <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3, - GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>; - bias-pull-up; - drive-strength = <12>; - input-enable; - input-schmitt-enable; - slew-rate = <0>; - }; - }; -}; - -&mmc0 { - compatible = "snps,dw-mshc"; - max-frequency = <100000000>; - bus-width = <8>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; - cap-mmc-highspeed; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - non-removable; - cap-mmc-hw-reset; - post-power-on-delay-ms = <200>; - status = "okay"; - -}; - -&mmc1 { - compatible = "snps,dw-mshc"; - max-frequency = <100000000>; - bus-width = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - no-sdio; - no-mmc; - cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>; - cap-sd-highspeed; - post-power-on-delay-ms = <200>; - status = "okay"; -}; - -&qspi { - spi-max-frequency = <250000000>; - status = "okay"; - - nor-flash@0 { - compatible = "jedec,spi-nor"; - reg=<0>; - spi-max-frequency = <100000000>; - cdns,tshsl-ns = <1>; - cdns,tsd2d-ns = <1>; - cdns,tchsh-ns = <1>; - cdns,tslch-ns = <1>; - }; -}; - -&pcie0 { - reset-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pcie1 { - reset-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&syscrg { - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, - <&syscrg JH7110_SYSCLK_BUS_ROOT>, - <&syscrg JH7110_SYSCLK_PERH_ROOT>, - <&syscrg JH7110_SYSCLK_QSPI_REF>; - assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>, - <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; - assigned-clock-rates = <0>, <0>, <0>, <0>; -}; - -&aoncrg { - assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>; - assigned-clock-parents = <&osc>; - assigned-clock-rates = <0>; -}; - -&gmac0 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; - }; -}; - -&gmac1 { - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy1: ethernet-phy@1 { - reg = <0>; - }; - }; -}; diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 2f560e7296..52c1d60859 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -62,7 +62,7 @@ <&syscrg JH7110_SYSRST_DDR_OSC>, <&syscrg JH7110_SYSRST_DDR_APB>; reset-names = "axi", "osc", "apb"; - clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; clock-names = "pll1_out"; clock-frequency = <2133>; }; diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi deleted file mode 100644 index 2cdc683d49..0000000000 --- a/arch/riscv/dts/jh7110.dtsi +++ /dev/null @@ -1,761 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 OR MIT -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - */ - -/dts-v1/; -#include <dt-bindings/clock/starfive,jh7110-crg.h> -#include <dt-bindings/reset/starfive,jh7110-crg.h> - -/ { - compatible = "starfive,jh7110"; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - S7_0: cpu@0 { - compatible = "sifive,s7", "riscv"; - reg = <0>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <16384>; - next-level-cache = <&ccache>; - riscv,isa = "rv64imac_zba_zbb"; - status = "disabled"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_1: cpu@1 { - compatible = "sifive,u74-mc", "riscv"; - reg = <1>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_2: cpu@2 { - compatible = "sifive,u74-mc", "riscv"; - reg = <2>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_3: cpu@3 { - compatible = "sifive,u74-mc", "riscv"; - reg = <3>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - U74_4: cpu@4 { - compatible = "sifive,u74-mc", "riscv"; - reg = <4>; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - riscv,isa = "rv64imafdc_zba_zbb"; - tlb-split; - - cpu4_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&S7_0>; - }; - - core1 { - cpu = <&U74_1>; - }; - - core2 { - cpu = <&U74_2>; - }; - - core3 { - cpu = <&U74_3>; - }; - - core4 { - cpu = <&U74_4>; - }; - }; - }; - }; - - timer { - compatible = "riscv,timer"; - interrupts-extended = <&cpu0_intc 5>, - <&cpu1_intc 5>, - <&cpu2_intc 5>, - <&cpu3_intc 5>, - <&cpu4_intc 5>; - }; - - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc"; - #clock-cells = <0>; - }; - - rtc_osc: rtc-oscillator { - compatible = "fixed-clock"; - clock-output-names = "rtc_osc"; - #clock-cells = <0>; - }; - - gmac0_rmii_refin: gmac0-rmii-refin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac0_rmii_refin"; - #clock-cells = <0>; - }; - - gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac0_rgmii_rxin"; - #clock-cells = <0>; - }; - - gmac1_rmii_refin: gmac1-rmii-refin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac1_rmii_refin"; - #clock-cells = <0>; - }; - - gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { - compatible = "fixed-clock"; - clock-output-names = "gmac1_rgmii_rxin"; - #clock-cells = <0>; - }; - - i2stx_bclk_ext: i2stx-bclk-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2stx_bclk_ext"; - #clock-cells = <0>; - }; - - i2stx_lrck_ext: i2stx-lrck-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2stx_lrck_ext"; - #clock-cells = <0>; - }; - - i2srx_bclk_ext: i2srx-bclk-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2srx_bclk_ext"; - #clock-cells = <0>; - }; - - i2srx_lrck_ext: i2srx-lrck-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "i2srx_lrck_ext"; - #clock-cells = <0>; - }; - - tdm_ext: tdm-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "tdm_ext"; - #clock-cells = <0>; - }; - - mclk_ext: mclk-ext-clock { - compatible = "fixed-clock"; - clock-output-names = "mclk_ext"; - #clock-cells = <0>; - }; - - stmmac_axi_setup: stmmac-axi-config { - snps,lpi_en; - snps,wr_osr_lmt = <4>; - snps,rd_osr_lmt = <4>; - snps,blen = <256 128 64 32 0 0 0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - clint: timer@2000000 { - compatible = "starfive,jh7110-clint", "sifive,clint0"; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>, - <&cpu4_intc 3>, <&cpu4_intc 7>; - }; - - plic: interrupt-controller@c000000 { - compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <0>; - riscv,ndev = <136>; - }; - - ccache: cache-controller@2010000 { - compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; - reg = <0x0 0x2010000 0x0 0x4000>; - interrupts = <1>, <3>, <4>, <2>; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <2048>; - cache-size = <2097152>; - cache-unified; - }; - - uart0: serial@10000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x10000000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, - <&syscrg JH7110_SYSCLK_UART0_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART0_APB>, - <&syscrg JH7110_SYSRST_UART0_CORE>; - interrupts = <32>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart1: serial@10010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x10010000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, - <&syscrg JH7110_SYSCLK_UART1_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART1_APB>, - <&syscrg JH7110_SYSRST_UART1_CORE>; - interrupts = <33>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart2: serial@10020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x10020000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, - <&syscrg JH7110_SYSCLK_UART2_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART2_APB>, - <&syscrg JH7110_SYSRST_UART2_CORE>; - interrupts = <34>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - i2c0: i2c@10030000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x10030000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C0_APB>; - interrupts = <35>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@10040000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x10040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C1_APB>; - interrupts = <36>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@10050000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x10050000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C2_APB>; - interrupts = <37>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - stgcrg: clock-controller@10230000 { - compatible = "starfive,jh7110-stgcrg"; - reg = <0x0 0x10230000 0x0 0x10000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - stg_syscon: stg_syscon@10240000 { - compatible = "starfive,jh7110-stg-syscon","syscon"; - reg = <0x0 0x10240000 0x0 0x1000>; - }; - - uart3: serial@12000000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x12000000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, - <&syscrg JH7110_SYSCLK_UART3_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART3_APB>, - <&syscrg JH7110_SYSRST_UART3_CORE>; - interrupts = <45>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart4: serial@12010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x12010000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, - <&syscrg JH7110_SYSCLK_UART4_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART4_APB>, - <&syscrg JH7110_SYSRST_UART4_CORE>; - interrupts = <46>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - uart5: serial@12020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x0 0x12020000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, - <&syscrg JH7110_SYSCLK_UART5_APB>; - clock-names = "baudclk", "apb_pclk"; - resets = <&syscrg JH7110_SYSRST_UART5_APB>, - <&syscrg JH7110_SYSRST_UART5_CORE>; - interrupts = <47>; - reg-io-width = <4>; - reg-shift = <2>; - status = "disabled"; - }; - - i2c3: i2c@12030000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12030000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C3_APB>; - interrupts = <48>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@12040000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C4_APB>; - interrupts = <49>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@12050000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12050000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C5_APB>; - interrupts = <50>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@12060000 { - compatible = "snps,designware-i2c"; - reg = <0x0 0x12060000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; - clock-names = "ref"; - resets = <&syscrg JH7110_SYSRST_I2C6_APB>; - interrupts = <51>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - power-controller@17030000 { - compatible = "starfive,jh7110-pmu"; - reg = <0x0 0x17030000 0x0 0x10000>; - interrupts = <111>; - }; - - qspi: spi@13010000 { - compatible = "cdns,qspi-nor"; - reg = <0x0 0x13010000 0x0 0x10000 - 0x0 0x21000000 0x0 0x400000>; - clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>; - clock-names = "clk_ref"; - resets = <&syscrg JH7110_SYSRST_QSPI_APB>, - <&syscrg JH7110_SYSRST_QSPI_AHB>, - <&syscrg JH7110_SYSRST_QSPI_REF>; - reset-names = "rst_apb", "rst_ahb", "rst_ref"; - cdns,fifo-depth = <256>; - cdns,fifo-width = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - - syscrg: clock-controller@13020000 { - compatible = "starfive,jh7110-syscrg"; - reg = <0x0 0x13020000 0x0 0x10000>; - clocks = <&osc>, <&gmac1_rmii_refin>, - <&gmac1_rgmii_rxin>, - <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, - <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>, - <&pllclk JH7110_SYSCLK_PLL0_OUT>, - <&pllclk JH7110_SYSCLK_PLL1_OUT>, - <&pllclk JH7110_SYSCLK_PLL2_OUT>; - clock-names = "osc", "gmac1_rmii_refin", - "gmac1_rgmii_rxin", - "i2stx_bclk_ext", "i2stx_lrck_ext", - "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext", - "pll0_out", "pll1_out", "pll2_out"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - sys_syscon: sys_syscon@13030000 { - compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd"; - reg = <0x0 0x13030000 0x0 0x1000>; - - pllclk: clock-controller { - compatible = "starfive,jh7110-pll"; - clocks = <&osc>; - #clock-cells = <1>; - }; - }; - - sysgpio: pinctrl@13040000 { - compatible = "starfive,jh7110-sys-pinctrl"; - reg = <0x0 0x13040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; - resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; - interrupts = <86>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - watchdog@13070000 { - compatible = "starfive,jh7110-wdt"; - reg = <0x0 0x13070000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, - <&syscrg JH7110_SYSCLK_WDT_CORE>; - clock-names = "apb", "core"; - resets = <&syscrg JH7110_SYSRST_WDT_APB>, - <&syscrg JH7110_SYSRST_WDT_CORE>; - }; - - mmc0: mmc@16010000 { - compatible = "starfive,jh7110-mmc"; - reg = <0x0 0x16010000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, - <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; - clock-names = "biu", "ciu"; - resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; - reset-names = "reset"; - interrupts = <74>; - fifo-depth = <32>; - fifo-watermark-aligned; - data-addr = <0>; - starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; - status = "disabled"; - }; - - mmc1: mmc@16020000 { - compatible = "starfive,jh7110-mmc"; - reg = <0x0 0x16020000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, - <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; - clock-names = "biu", "ciu"; - resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; - reset-names = "reset"; - interrupts = <75>; - fifo-depth = <32>; - fifo-watermark-aligned; - data-addr = <0>; - starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; - status = "disabled"; - }; - - gmac0: ethernet@16030000 { - compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; - reg = <0x0 0x16030000 0x0 0x10000>; - clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, - <&aoncrg JH7110_AONCLK_GMAC0_AHB>, - <&syscrg JH7110_SYSCLK_GMAC0_PTP>, - <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, - <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; - clock-names = "stmmaceth", "pclk", "ptp_ref", - "tx", "gtx"; - resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, - <&aoncrg JH7110_AONRST_GMAC0_AHB>; - reset-names = "stmmaceth", "ahb"; - interrupts = <7>, <6>, <5>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <8>; - rx-fifo-depth = <2048>; - tx-fifo-depth = <2048>; - snps,fixed-burst; - snps,no-pbl-x8; - snps,force_thresh_dma_mode; - snps,axi-config = <&stmmac_axi_setup>; - snps,tso; - snps,en-tx-lpi-clockgating; - snps,txpbl = <16>; - snps,rxpbl = <16>; - starfive,syscon = <&aon_syscon 0xc 0x12>; - status = "disabled"; - }; - - gmac1: ethernet@16040000 { - compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; - reg = <0x0 0x16040000 0x0 0x10000>; - clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, - <&syscrg JH7110_SYSCLK_GMAC1_AHB>, - <&syscrg JH7110_SYSCLK_GMAC1_PTP>, - <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, - <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; - clock-names = "stmmaceth", "pclk", "ptp_ref", - "tx", "gtx"; - resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, - <&syscrg JH7110_SYSRST_GMAC1_AHB>; - reset-names = "stmmaceth", "ahb"; - interrupts = <78>, <77>, <76>; - interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; - snps,multicast-filter-bins = <64>; - snps,perfect-filter-entries = <8>; - rx-fifo-depth = <2048>; - tx-fifo-depth = <2048>; - snps,fixed-burst; - snps,no-pbl-x8; - snps,force_thresh_dma_mode; - snps,axi-config = <&stmmac_axi_setup>; - snps,tso; - snps,en-tx-lpi-clockgating; - snps,txpbl = <16>; - snps,rxpbl = <16>; - starfive,syscon = <&sys_syscon 0x90 0x2>; - status = "disabled"; - }; - - rng: rng@1600c000 { - compatible = "starfive,jh7110-trng"; - reg = <0x0 0x1600C000 0x0 0x4000>; - clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>, - <&stgcrg JH7110_STGCLK_SEC_MISCAHB>; - clock-names = "hclk", "ahb"; - resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>; - interrupts = <30>; - }; - - aoncrg: clock-controller@17000000 { - compatible = "starfive,jh7110-aoncrg"; - reg = <0x0 0x17000000 0x0 0x10000>; - clocks = <&osc>, <&rtc_osc>, - <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>, - <&syscrg JH7110_SYSCLK_STG_AXIAHB>, - <&syscrg JH7110_SYSCLK_APB_BUS>, - <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>; - clock-names = "osc", "rtc_osc", "gmac0_rmii_refin", - "gmac0_rgmii_rxin", "stg_axiahb", - "apb_bus", "gmac0_gtxclk"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - aon_syscon: aon_syscon@17010000 { - compatible = "starfive,jh7110-aon-syscon","syscon"; - reg = <0x0 0x17010000 0x0 0x1000>; - }; - - aongpio: pinctrl@17020000 { - compatible = "starfive,jh7110-aon-pinctrl"; - reg = <0x0 0x17020000 0x0 0x10000>; - resets = <&aoncrg JH7110_AONRST_IOMUX>; - interrupts = <85>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - pcie0: pcie@2b000000 { - compatible = "starfive,jh7110-pcie"; - reg = <0x0 0x2b000000 0x0 0x1000000 - 0x9 0x40000000 0x0 0x10000000>; - reg-names = "reg", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, - <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; - interrupts = <56>; - interrupt-parent = <&plic>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, - <0x0 0x0 0x0 0x2 &plic 0x2>, - <0x0 0x0 0x0 0x3 &plic 0x3>, - <0x0 0x0 0x0 0x4 &plic 0x4>; - msi-parent = <&plic>; - device_type = "pci"; - starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; - bus-range = <0x0 0xff>; - clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, - <&stgcrg JH7110_STGCLK_PCIE0_TL>, - <&stgcrg JH7110_STGCLK_PCIE0_AXI>, - <&stgcrg JH7110_STGCLK_PCIE0_APB>; - clock-names = "noc", "tl", "axi", "apb"; - resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>, - <&stgcrg JH7110_STGRST_PCIE0_SLV0>, - <&stgcrg JH7110_STGRST_PCIE0_SLV>, - <&stgcrg JH7110_STGRST_PCIE0_BRG>, - <&stgcrg JH7110_STGRST_PCIE0_CORE>, - <&stgcrg JH7110_STGRST_PCIE0_APB>; - reset-names = "mst0", "slv0", "slv", "brg", - "core", "apb"; - status = "disabled"; - }; - - pcie1: pcie@2c000000 { - compatible = "starfive,jh7110-pcie"; - reg = <0x0 0x2c000000 0x0 0x1000000 - 0x9 0xc0000000 0x0 0x10000000>; - reg-names = "reg", "config"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, - <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; - interrupts = <57>; - interrupt-parent = <&plic>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>, - <0x0 0x0 0x0 0x2 &plic 0x2>, - <0x0 0x0 0x0 0x3 &plic 0x3>, - <0x0 0x0 0x0 0x4 &plic 0x4>; - msi-parent = <&plic>; - device_type = "pci"; - starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>; - bus-range = <0x0 0xff>; - clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, - <&stgcrg JH7110_STGCLK_PCIE1_TL>, - <&stgcrg JH7110_STGCLK_PCIE1_AXI>, - <&stgcrg JH7110_STGCLK_PCIE1_APB>; - clock-names = "noc", "tl", "axi", "apb"; - resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>, - <&stgcrg JH7110_STGRST_PCIE1_SLV0>, - <&stgcrg JH7110_STGRST_PCIE1_SLV>, - <&stgcrg JH7110_STGRST_PCIE1_BRG>, - <&stgcrg JH7110_STGRST_PCIE1_CORE>, - <&stgcrg JH7110_STGRST_PCIE1_APB>; - reset-names = "mst0", "slv0", "slv", "brg", - "core", "apb"; - status = "disabled"; - }; - }; -}; diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 319e1d358a..3385c25b3f 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=100000000 CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0xf0000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2" +CONFIG_DEFAULT_DEVICE_TREE="starfive/jh7110-starfive-visionfive-2-v1.3b" CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_SPL_MMC=y diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 6d2bfb3ecb..f8af17227c 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -374,13 +374,13 @@ static int jh7110_pll_clk_probe(struct udevice *dev) if (sysreg == FDT_ADDR_T_NONE) return -EINVAL;
- clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL0_OUT), starfive_jh7110_pll("pll0_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll0)); - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL1_OUT), starfive_jh7110_pll("pll1_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll1)); - clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT), + clk_dm(JH7110_PLL_ID_TRANS(JH7110_PLLCLK_PLL2_OUT), starfive_jh7110_pll("pll2_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll2));
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 191da75d7b..6387e949d5 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -495,37 +495,37 @@ static int jh7110_stgcrg_init(struct udevice *dev) { struct jh7110_clk_priv *priv = dev_get_priv(dev);
- clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APB), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APB), starfive_clk_gate(priv->reg, "usb_apb", "apb_bus", - OFFSET(JH7110_STGCLK_USB_APB))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_UTMI_APB), + OFFSET(JH7110_STGCLK_USB0_APB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_UTMI_APB), starfive_clk_gate(priv->reg, "usb_utmi_apb", "apb_bus", - OFFSET(JH7110_STGCLK_USB_UTMI_APB))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_AXI), + OFFSET(JH7110_STGCLK_USB0_UTMI_APB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_AXI), starfive_clk_gate(priv->reg, "usb_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_USB_AXI))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_LPM), + OFFSET(JH7110_STGCLK_USB0_AXI))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_LPM), starfive_clk_gate_divider(priv->reg, "usb_lpm", "oscillator", - OFFSET(JH7110_STGCLK_USB_LPM), 2)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_STB), + OFFSET(JH7110_STGCLK_USB0_LPM), 2)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_STB), starfive_clk_gate_divider(priv->reg, "usb_stb", "oscillator", - OFFSET(JH7110_STGCLK_USB_STB), 3)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_APP_125), + OFFSET(JH7110_STGCLK_USB0_STB), 3)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_APP_125), starfive_clk_gate(priv->reg, "usb_app_125", "usb_125m", - OFFSET(JH7110_STGCLK_USB_APP_125))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB_REFCLK), + OFFSET(JH7110_STGCLK_USB0_APP_125))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_USB0_REFCLK), starfive_clk_divider(priv->reg, "usb_refclk", "oscillator", - OFFSET(JH7110_STGCLK_USB_REFCLK), 2)); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI), + OFFSET(JH7110_STGCLK_USB0_REFCLK), 2)); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_AXI_MST0), starfive_clk_gate(priv->reg, "pcie0_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_PCIE0_AXI))); + OFFSET(JH7110_STGCLK_PCIE0_AXI_MST0))); clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE0_APB), starfive_clk_gate(priv->reg, "pcie0_apb", "apb_bus", @@ -534,10 +534,10 @@ static int jh7110_stgcrg_init(struct udevice *dev) starfive_clk_gate(priv->reg, "pcie0_tl", "stg_axiahb", OFFSET(JH7110_STGCLK_PCIE0_TL))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_AXI_MST0), starfive_clk_gate(priv->reg, "pcie1_axi", "stg_axiahb", - OFFSET(JH7110_STGCLK_PCIE1_AXI))); + OFFSET(JH7110_STGCLK_PCIE1_AXI_MST0))); clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_PCIE1_APB), starfive_clk_gate(priv->reg, "pcie1_apb", "apb_bus", @@ -548,14 +548,14 @@ static int jh7110_stgcrg_init(struct udevice *dev) OFFSET(JH7110_STGCLK_PCIE1_TL)));
/* Security clocks */ - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK), + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_AHB), starfive_clk_gate(priv->reg, "sec_ahb", "stg_axiahb", - OFFSET(JH7110_STGCLK_SEC_HCLK))); - clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB), + OFFSET(JH7110_STGCLK_SEC_AHB))); + clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISC_AHB), starfive_clk_gate(priv->reg, "sec_misc_ahb", "stg_axiahb", - OFFSET(JH7110_STGCLK_SEC_MISCAHB))); + OFFSET(JH7110_STGCLK_SEC_MISC_AHB)));
return 0; } diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h deleted file mode 100644 index b51e3829ff..0000000000 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang yanhong.wang@starfivetech.com - */ - -#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ - -#define JH7110_SYSCLK_PLL0_OUT 0 -#define JH7110_SYSCLK_PLL1_OUT 1 -#define JH7110_SYSCLK_PLL2_OUT 2 -#define JH7110_PLLCLK_END 3 - -#define JH7110_SYSCLK_CPU_ROOT 0 -#define JH7110_SYSCLK_CPU_CORE 1 -#define JH7110_SYSCLK_CPU_BUS 2 -#define JH7110_SYSCLK_GPU_ROOT 3 -#define JH7110_SYSCLK_PERH_ROOT 4 -#define JH7110_SYSCLK_BUS_ROOT 5 -#define JH7110_SYSCLK_NOCSTG_BUS 6 -#define JH7110_SYSCLK_AXI_CFG0 7 -#define JH7110_SYSCLK_STG_AXIAHB 8 -#define JH7110_SYSCLK_AHB0 9 -#define JH7110_SYSCLK_AHB1 10 -#define JH7110_SYSCLK_APB_BUS 11 -#define JH7110_SYSCLK_APB0 12 -#define JH7110_SYSCLK_PLL0_DIV2 13 -#define JH7110_SYSCLK_PLL1_DIV2 14 -#define JH7110_SYSCLK_PLL2_DIV2 15 -#define JH7110_SYSCLK_AUDIO_ROOT 16 -#define JH7110_SYSCLK_MCLK_INNER 17 -#define JH7110_SYSCLK_MCLK 18 -#define JH7110_SYSCLK_MCLK_OUT 19 -#define JH7110_SYSCLK_ISP_2X 20 -#define JH7110_SYSCLK_ISP_AXI 21 -#define JH7110_SYSCLK_GCLK0 22 -#define JH7110_SYSCLK_GCLK1 23 -#define JH7110_SYSCLK_GCLK2 24 -#define JH7110_SYSCLK_CORE 25 -#define JH7110_SYSCLK_CORE1 26 -#define JH7110_SYSCLK_CORE2 27 -#define JH7110_SYSCLK_CORE3 28 -#define JH7110_SYSCLK_CORE4 29 -#define JH7110_SYSCLK_DEBUG 30 -#define JH7110_SYSCLK_RTC_TOGGLE 31 -#define JH7110_SYSCLK_TRACE0 32 -#define JH7110_SYSCLK_TRACE1 33 -#define JH7110_SYSCLK_TRACE2 34 -#define JH7110_SYSCLK_TRACE3 35 -#define JH7110_SYSCLK_TRACE4 36 -#define JH7110_SYSCLK_TRACE_COM 37 -#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 -#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 -#define JH7110_SYSCLK_OSC_DIV2 40 -#define JH7110_SYSCLK_PLL1_DIV4 41 -#define JH7110_SYSCLK_PLL1_DIV8 42 -#define JH7110_SYSCLK_DDR_BUS 43 -#define JH7110_SYSCLK_DDR_AXI 44 -#define JH7110_SYSCLK_GPU_CORE 45 -#define JH7110_SYSCLK_GPU_CORE_CLK 46 -#define JH7110_SYSCLK_GPU_SYS_CLK 47 -#define JH7110_SYSCLK_GPU_APB 48 -#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 -#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISPCORE_2X 51 -#define JH7110_SYSCLK_ISP_TOP_CLK_ISP_AXI 52 -#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 -#define JH7110_SYSCLK_HIFI4_CORE 54 -#define JH7110_SYSCLK_HIFI4_AXI 55 -#define JH7110_SYSCLK_AXI_CFG1_DEC_MAIN 56 -#define JH7110_SYSCLK_AXI_CFG1_DEC_AHB 57 -#define JH7110_SYSCLK_VOUT_SRC 58 -#define JH7110_SYSCLK_VOUT_AXI 59 -#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AHB 61 -#define JH7110_SYSCLK_VOUT_TOP_CLK_VOUT_AXI 62 -#define JH7110_SYSCLK_VOUT_TOP_CLK_HDMITX0_MCLK 63 -#define JH7110_SYSCLK_VOUT_TOP_CLK_MIPIPHY_REF 64 -#define JH7110_SYSCLK_JPEGC_AXI 65 -#define JH7110_SYSCLK_CODAJ12_AXI 66 -#define JH7110_SYSCLK_CODAJ12_CORE 67 -#define JH7110_SYSCLK_CODAJ12_APB 68 -#define JH7110_SYSCLK_VDEC_AXI 69 -#define JH7110_SYSCLK_WAVE511_AXI 70 -#define JH7110_SYSCLK_WAVE511_BPU 71 -#define JH7110_SYSCLK_WAVE511_VCE 72 -#define JH7110_SYSCLK_WAVE511_APB 73 -#define JH7110_SYSCLK_VDEC_JPG_ARB_JPG 74 -#define JH7110_SYSCLK_VDEC_JPG_ARB_MAIN 75 -#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 -#define JH7110_SYSCLK_VENC_AXI 77 -#define JH7110_SYSCLK_WAVE420L_AXI 78 -#define JH7110_SYSCLK_WAVE420L_BPU 79 -#define JH7110_SYSCLK_WAVE420L_VCE 80 -#define JH7110_SYSCLK_WAVE420L_APB 81 -#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN_DIV 83 -#define JH7110_SYSCLK_AXI_CFG0_DEC_MAIN 84 -#define JH7110_SYSCLK_AXI_CFG0_DEC_HIFI4 85 -#define JH7110_SYSCLK_AXIMEM2_AXI 86 -#define JH7110_SYSCLK_QSPI_AHB 87 -#define JH7110_SYSCLK_QSPI_APB 88 -#define JH7110_SYSCLK_QSPI_REF_SRC 89 -#define JH7110_SYSCLK_QSPI_REF 90 -#define JH7110_SYSCLK_SDIO0_AHB 91 -#define JH7110_SYSCLK_SDIO1_AHB 92 -#define JH7110_SYSCLK_SDIO0_SDCARD 93 -#define JH7110_SYSCLK_SDIO1_SDCARD 94 -#define JH7110_SYSCLK_USB_125M 95 -#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 -#define JH7110_SYSCLK_GMAC1_AHB 97 -#define JH7110_SYSCLK_GMAC1_AXI 98 -#define JH7110_SYSCLK_GMAC_SRC 99 -#define JH7110_SYSCLK_GMAC1_GTXCLK 100 -#define JH7110_SYSCLK_GMAC1_RMII_RTX 101 -#define JH7110_SYSCLK_GMAC1_PTP 102 -#define JH7110_SYSCLK_GMAC1_RX 103 -#define JH7110_SYSCLK_GMAC1_RX_INV 104 -#define JH7110_SYSCLK_GMAC1_TX 105 -#define JH7110_SYSCLK_GMAC1_TX_INV 106 -#define JH7110_SYSCLK_GMAC1_GTXC 107 -#define JH7110_SYSCLK_GMAC0_GTXCLK 108 -#define JH7110_SYSCLK_GMAC0_PTP 109 -#define JH7110_SYSCLK_GMAC_PHY 110 -#define JH7110_SYSCLK_GMAC0_GTXC 111 -#define JH7110_SYSCLK_IOMUX_APB 112 -#define JH7110_SYSCLK_MAILBOX 113 -#define JH7110_SYSCLK_INT_CTRL_APB 114 -#define JH7110_SYSCLK_CAN0_APB 115 -#define JH7110_SYSCLK_CAN0_TIMER 116 -#define JH7110_SYSCLK_CAN0_CAN 117 -#define JH7110_SYSCLK_CAN1_APB 118 -#define JH7110_SYSCLK_CAN1_TIMER 119 -#define JH7110_SYSCLK_CAN1_CAN 120 -#define JH7110_SYSCLK_PWM_APB 121 -#define JH7110_SYSCLK_WDT_APB 122 -#define JH7110_SYSCLK_WDT_CORE 123 -#define JH7110_SYSCLK_TIMER_APB 124 -#define JH7110_SYSCLK_TIMER0 125 -#define JH7110_SYSCLK_TIMER1 126 -#define JH7110_SYSCLK_TIMER2 127 -#define JH7110_SYSCLK_TIMER3 128 -#define JH7110_SYSCLK_TEMP_APB 129 -#define JH7110_SYSCLK_TEMP_CORE 130 -#define JH7110_SYSCLK_SPI0_APB 131 -#define JH7110_SYSCLK_SPI1_APB 132 -#define JH7110_SYSCLK_SPI2_APB 133 -#define JH7110_SYSCLK_SPI3_APB 134 -#define JH7110_SYSCLK_SPI4_APB 135 -#define JH7110_SYSCLK_SPI5_APB 136 -#define JH7110_SYSCLK_SPI6_APB 137 -#define JH7110_SYSCLK_I2C0_APB 138 -#define JH7110_SYSCLK_I2C1_APB 139 -#define JH7110_SYSCLK_I2C2_APB 140 -#define JH7110_SYSCLK_I2C3_APB 141 -#define JH7110_SYSCLK_I2C4_APB 142 -#define JH7110_SYSCLK_I2C5_APB 143 -#define JH7110_SYSCLK_I2C6_APB 144 -#define JH7110_SYSCLK_UART0_APB 145 -#define JH7110_SYSCLK_UART0_CORE 146 -#define JH7110_SYSCLK_UART1_APB 147 -#define JH7110_SYSCLK_UART1_CORE 148 -#define JH7110_SYSCLK_UART2_APB 149 -#define JH7110_SYSCLK_UART2_CORE 150 -#define JH7110_SYSCLK_UART3_APB 151 -#define JH7110_SYSCLK_UART3_CORE 152 -#define JH7110_SYSCLK_UART4_APB 153 -#define JH7110_SYSCLK_UART4_CORE 154 -#define JH7110_SYSCLK_UART5_APB 155 -#define JH7110_SYSCLK_UART5_CORE 156 -#define JH7110_SYSCLK_PWMDAC_APB 157 -#define JH7110_SYSCLK_PWMDAC_CORE 158 -#define JH7110_SYSCLK_SPDIF_APB 159 -#define JH7110_SYSCLK_SPDIF_CORE 160 -#define JH7110_SYSCLK_I2STX0_APB 161 -#define JH7110_SYSCLK_I2STX0_BCLK_MST 162 -#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 -#define JH7110_SYSCLK_I2STX0_LRCK_MST 164 -#define JH7110_SYSCLK_I2STX0_BCLK 165 -#define JH7110_SYSCLK_I2STX0_BCLK_INV 166 -#define JH7110_SYSCLK_I2STX0_LRCK 167 -#define JH7110_SYSCLK_I2STX1_APB 168 -#define JH7110_SYSCLK_I2STX1_BCLK_MST 169 -#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 -#define JH7110_SYSCLK_I2STX1_LRCK_MST 171 -#define JH7110_SYSCLK_I2STX1_BCLK 172 -#define JH7110_SYSCLK_I2STX1_BCLK_INV 173 -#define JH7110_SYSCLK_I2STX1_LRCK 174 -#define JH7110_SYSCLK_I2SRX_APB 175 -#define JH7110_SYSCLK_I2SRX_BCLK_MST 176 -#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 -#define JH7110_SYSCLK_I2SRX_LRCK_MST 178 -#define JH7110_SYSCLK_I2SRX_BCLK 179 -#define JH7110_SYSCLK_I2SRX_BCLK_INV 180 -#define JH7110_SYSCLK_I2SRX_LRCK 181 -#define JH7110_SYSCLK_PDM_DMIC 182 -#define JH7110_SYSCLK_PDM_APB 183 -#define JH7110_SYSCLK_TDM_AHB 184 -#define JH7110_SYSCLK_TDM_APB 185 -#define JH7110_SYSCLK_TDM_INTERNAL 186 -#define JH7110_SYSCLK_TDM_CLK_TDM 187 -#define JH7110_SYSCLK_TDM_CLK_TDM_N 188 -#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 - -#define JH7110_SYSCLK_END 190 - -#define JH7110_AONCLK_OSC_DIV4 0 -#define JH7110_AONCLK_APB_FUNC 1 -#define JH7110_AONCLK_GMAC0_AHB 2 -#define JH7110_AONCLK_GMAC0_AXI 3 -#define JH7110_AONCLK_GMAC0_RMII_RTX 4 -#define JH7110_AONCLK_GMAC0_TX 5 -#define JH7110_AONCLK_GMAC0_TX_INV 6 -#define JH7110_AONCLK_GMAC0_RX 7 -#define JH7110_AONCLK_GMAC0_RX_INV 8 -#define JH7110_AONCLK_OTPC_APB 9 -#define JH7110_AONCLK_RTC_APB 10 -#define JH7110_AONCLK_RTC_INTERNAL 11 -#define JH7110_AONCLK_RTC_32K 12 -#define JH7110_AONCLK_RTC_CAL 13 - -#define JH7110_AONCLK_END 14 - -#define JH7110_STGCLK_HIFI4_CORE 0 -#define JH7110_STGCLK_USB_APB 1 -#define JH7110_STGCLK_USB_UTMI_APB 2 -#define JH7110_STGCLK_USB_AXI 3 -#define JH7110_STGCLK_USB_LPM 4 -#define JH7110_STGCLK_USB_STB 5 -#define JH7110_STGCLK_USB_APP_125 6 -#define JH7110_STGCLK_USB_REFCLK 7 -#define JH7110_STGCLK_PCIE0_AXI 8 -#define JH7110_STGCLK_PCIE0_APB 9 -#define JH7110_STGCLK_PCIE0_TL 10 -#define JH7110_STGCLK_PCIE1_AXI 11 -#define JH7110_STGCLK_PCIE1_APB 12 -#define JH7110_STGCLK_PCIE1_TL 13 -#define JH7110_STGCLK_PCIE01_MAIN 14 -#define JH7110_STGCLK_SEC_HCLK 15 -#define JH7110_STGCLK_SEC_MISCAHB 16 -#define JH7110_STGCLK_MTRX_GRP0_MAIN 17 -#define JH7110_STGCLK_MTRX_GRP0_BUS 18 -#define JH7110_STGCLK_MTRX_GRP0_STG 19 -#define JH7110_STGCLK_MTRX_GRP1_MAIN 20 -#define JH7110_STGCLK_MTRX_GRP1_BUS 21 -#define JH7110_STGCLK_MTRX_GRP1_STG 22 -#define JH7110_STGCLK_MTRX_GRP1_HIFI 23 -#define JH7110_STGCLK_E2_RTC 24 -#define JH7110_STGCLK_E2_CORE 25 -#define JH7110_STGCLK_E2_DBG 26 -#define JH7110_STGCLK_DMA1P_AXI 27 -#define JH7110_STGCLK_DMA1P_AHB 28 - -#define JH7110_STGCLK_END 29 - -#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h deleted file mode 100644 index 1d596581da..0000000000 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ /dev/null @@ -1,183 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2022 StarFive Technology Co., Ltd. - * - * Author: Yanhong Wang yanhong.wang@starfivetech.com - */ - -#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ -#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ - -/* SYSCRG resets */ -#define JH7110_SYSRST_JTAG2APB 0 -#define JH7110_SYSRST_SYSCON 1 -#define JH7110_SYSRST_IOMUX_APB 2 -#define JH7110_SYSRST_BUS 3 -#define JH7110_SYSRST_DEBUG 4 -#define JH7110_SYSRST_CORE0 5 -#define JH7110_SYSRST_CORE1 6 -#define JH7110_SYSRST_CORE2 7 -#define JH7110_SYSRST_CORE3 8 -#define JH7110_SYSRST_CORE4 9 -#define JH7110_SYSRST_CORE0_ST 10 -#define JH7110_SYSRST_CORE1_ST 11 -#define JH7110_SYSRST_CORE2_ST 12 -#define JH7110_SYSRST_CORE3_ST 13 -#define JH7110_SYSRST_CORE4_ST 14 -#define JH7110_SYSRST_TRACE0 15 -#define JH7110_SYSRST_TRACE1 16 -#define JH7110_SYSRST_TRACE2 17 -#define JH7110_SYSRST_TRACE3 18 -#define JH7110_SYSRST_TRACE4 19 -#define JH7110_SYSRST_TRACE_COM 20 -#define JH7110_SYSRST_GPU_APB 21 -#define JH7110_SYSRST_GPU_DOMA 22 -#define JH7110_SYSRST_NOC_BUS_APB_BUS 23 -#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24 -#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25 -#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26 -#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27 -#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28 -#define JH7110_SYSRST_NOC_BUS_DDRC 29 -#define JH7110_SYSRST_NOC_BUS_STG_AXI 30 -#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31 - -#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32 -#define JH7110_SYSRST_AXI_CFG1_DEC_AHB 33 -#define JH7110_SYSRST_AXI_CFG1_DEC_MAIN 34 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN 35 -#define JH7110_SYSRST_AXI_CFG0_DEC_MAIN_DIV 36 -#define JH7110_SYSRST_AXI_CFG0_DEC_HIFI4 37 -#define JH7110_SYSRST_DDR_AXI 38 -#define JH7110_SYSRST_DDR_OSC 39 -#define JH7110_SYSRST_DDR_APB 40 -#define JH7110_SYSRST_DOM_ISP_TOP_N 41 -#define JH7110_SYSRST_DOM_ISP_TOP_AXI 42 -#define JH7110_SYSRST_DOM_VOUT_TOP_SRC 43 -#define JH7110_SYSRST_CODAJ12_AXI 44 -#define JH7110_SYSRST_CODAJ12_CORE 45 -#define JH7110_SYSRST_CODAJ12_APB 46 -#define JH7110_SYSRST_WAVE511_AXI 47 -#define JH7110_SYSRST_WAVE511_BPU 48 -#define JH7110_SYSRST_WAVE511_VCE 49 -#define JH7110_SYSRST_WAVE511_APB 50 -#define JH7110_SYSRST_VDEC_JPG_ARB_JPG 51 -#define JH7110_SYSRST_VDEC_JPG_ARB_MAIN 52 -#define JH7110_SYSRST_AXIMEM0_AXI 53 -#define JH7110_SYSRST_WAVE420L_AXI 54 -#define JH7110_SYSRST_WAVE420L_BPU 55 -#define JH7110_SYSRST_WAVE420L_VCE 56 -#define JH7110_SYSRST_WAVE420L_APB 57 -#define JH7110_SYSRST_AXIMEM1_AXI 58 -#define JH7110_SYSRST_AXIMEM2_AXI 59 -#define JH7110_SYSRST_INTMEM 60 -#define JH7110_SYSRST_QSPI_AHB 61 -#define JH7110_SYSRST_QSPI_APB 62 -#define JH7110_SYSRST_QSPI_REF 63 - -#define JH7110_SYSRST_SDIO0_AHB 64 -#define JH7110_SYSRST_SDIO1_AHB 65 -#define JH7110_SYSRST_GMAC1_AXI 66 -#define JH7110_SYSRST_GMAC1_AHB 67 -#define JH7110_SYSRST_MAILBOX 68 -#define JH7110_SYSRST_SPI0_APB 69 -#define JH7110_SYSRST_SPI1_APB 70 -#define JH7110_SYSRST_SPI2_APB 71 -#define JH7110_SYSRST_SPI3_APB 72 -#define JH7110_SYSRST_SPI4_APB 73 -#define JH7110_SYSRST_SPI5_APB 74 -#define JH7110_SYSRST_SPI6_APB 75 -#define JH7110_SYSRST_I2C0_APB 76 -#define JH7110_SYSRST_I2C1_APB 77 -#define JH7110_SYSRST_I2C2_APB 78 -#define JH7110_SYSRST_I2C3_APB 79 -#define JH7110_SYSRST_I2C4_APB 80 -#define JH7110_SYSRST_I2C5_APB 81 -#define JH7110_SYSRST_I2C6_APB 82 -#define JH7110_SYSRST_UART0_APB 83 -#define JH7110_SYSRST_UART0_CORE 84 -#define JH7110_SYSRST_UART1_APB 85 -#define JH7110_SYSRST_UART1_CORE 86 -#define JH7110_SYSRST_UART2_APB 87 -#define JH7110_SYSRST_UART2_CORE 88 -#define JH7110_SYSRST_UART3_APB 89 -#define JH7110_SYSRST_UART3_CORE 90 -#define JH7110_SYSRST_UART4_APB 91 -#define JH7110_SYSRST_UART4_CORE 92 -#define JH7110_SYSRST_UART5_APB 93 -#define JH7110_SYSRST_UART5_CORE 94 -#define JH7110_SYSRST_SPDIF_APB 95 - -#define JH7110_SYSRST_PWMDAC_APB 96 -#define JH7110_SYSRST_PDM_DMIC 97 -#define JH7110_SYSRST_PDM_APB 98 -#define JH7110_SYSRST_I2SRX_APB 99 -#define JH7110_SYSRST_I2SRX_BCLK 100 -#define JH7110_SYSRST_I2STX0_APB 101 -#define JH7110_SYSRST_I2STX0_BCLK 102 -#define JH7110_SYSRST_I2STX1_APB 103 -#define JH7110_SYSRST_I2STX1_BCLK 104 -#define JH7110_SYSRST_TDM_AHB 105 -#define JH7110_SYSRST_TDM_CORE 106 -#define JH7110_SYSRST_TDM_APB 107 -#define JH7110_SYSRST_PWM_APB 108 -#define JH7110_SYSRST_WDT_APB 109 -#define JH7110_SYSRST_WDT_CORE 110 -#define JH7110_SYSRST_CAN0_APB 111 -#define JH7110_SYSRST_CAN0_CORE 112 -#define JH7110_SYSRST_CAN0_TIMER 113 -#define JH7110_SYSRST_CAN1_APB 114 -#define JH7110_SYSRST_CAN1_CORE 115 -#define JH7110_SYSRST_CAN1_TIMER 116 -#define JH7110_SYSRST_TIMER_APB 117 -#define JH7110_SYSRST_TIMER0 118 -#define JH7110_SYSRST_TIMER1 119 -#define JH7110_SYSRST_TIMER2 120 -#define JH7110_SYSRST_TIMER3 121 -#define JH7110_SYSRST_INT_CTRL_APB 122 -#define JH7110_SYSRST_TEMP_APB 123 -#define JH7110_SYSRST_TEMP_CORE 124 -#define JH7110_SYSRST_JTAG_CERTIFICATION 125 - -#define JH7110_SYSRST_END 126 - -/* AONCRG resets */ -#define JH7110_AONRST_GMAC0_AXI 0 -#define JH7110_AONRST_GMAC0_AHB 1 -#define JH7110_AONRST_IOMUX 2 -#define JH7110_AONRST_PMU_APB 3 -#define JH7110_AONRST_PMU_WKUP 4 -#define JH7110_AONRST_RTC_APB 5 -#define JH7110_AONRST_RTC_CAL 6 -#define JH7110_AONRST_RTC_32K 7 - -#define JH7110_AONRST_END 8 - -/* STGCRG resets */ -#define JH7110_STGRST_SYSCON_PRESETN 0 -#define JH7110_STGRST_HIFI4_CORE 1 -#define JH7110_STGRST_HIFI4_AXI 2 -#define JH7110_STGRST_SEC_TOP_HRESETN 3 -#define JH7110_STGRST_E24_CORE 4 -#define JH7110_STGRST_DMA1P_AXI 5 -#define JH7110_STGRST_DMA1P_AHB 6 -#define JH7110_STGRST_USB_AXI 7 -#define JH7110_STGRST_USB_APB 8 -#define JH7110_STGRST_USB_UTMI_APB 9 -#define JH7110_STGRST_USB_PWRUP 10 -#define JH7110_STGRST_PCIE0_MST0 11 -#define JH7110_STGRST_PCIE0_SLV0 12 -#define JH7110_STGRST_PCIE0_SLV 13 -#define JH7110_STGRST_PCIE0_BRG 14 -#define JH7110_STGRST_PCIE0_CORE 15 -#define JH7110_STGRST_PCIE0_APB 16 -#define JH7110_STGRST_PCIE1_MST0 17 -#define JH7110_STGRST_PCIE1_SLV0 18 -#define JH7110_STGRST_PCIE1_SLV 19 -#define JH7110_STGRST_PCIE1_BRG 20 -#define JH7110_STGRST_PCIE1_CORE 21 -#define JH7110_STGRST_PCIE1_APB 22 - -#define JH7110_STGRST_END 23 - -#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
Add u-boot features to the U-Boot device tree.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Acked-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Hal Feng hal.feng@starfivetech.com --- ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 33 +++++++++++++++--- arch/riscv/dts/jh7110-u-boot.dtsi | 34 +++++++++++++++++++ 2 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi index 3012466b30..7953459e67 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -6,6 +6,10 @@ #include "binman.dtsi" #include "jh7110-u-boot.dtsi" / { + aliases { + spi0 = &qspi; + }; + chosen { bootph-pre-ram; }; @@ -27,6 +31,9 @@
&uart0 { bootph-pre-ram; + reg-offset = <0>; + current-speed = <115200>; + clock-frequency = <24000000>; };
&mmc0 { @@ -39,30 +46,45 @@
&qspi { bootph-pre-ram; + spi-max-frequency = <250000000>;
- nor-flash@0 { + flash@0 { bootph-pre-ram; + /delete-property/ cdns,read-delay; + spi-max-frequency = <100000000>; }; };
+&syscrg { + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, + <&syscrg JH7110_SYSCLK_BUS_ROOT>, + <&syscrg JH7110_SYSCLK_PERH_ROOT>, + <&syscrg JH7110_SYSCLK_QSPI_REF>; + assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; + assigned-clock-rates = <0>, <0>, <0>, <0>; +}; + &sysgpio { bootph-pre-ram; };
&mmc0_pins { bootph-pre-ram; - mmc0-pins-rest { + rst-pins { bootph-pre-ram; }; };
&mmc1_pins { bootph-pre-ram; - mmc1-pins0 { + clk-pins { bootph-pre-ram; };
- mmc1-pins1 { + mmc-pins { bootph-pre-ram; }; }; @@ -78,6 +100,9 @@ bootph-pre-ram; eeprom@50 { bootph-pre-ram; + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; }; };
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 52c1d60859..21a2ab1789 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -46,6 +46,15 @@ }; };
+ timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu0_intc 5>, + <&cpu1_intc 5>, + <&cpu2_intc 5>, + <&cpu3_intc 5>, + <&cpu4_intc 5>; + }; + soc { bootph-pre-ram;
@@ -73,10 +82,35 @@ bootph-pre-ram; };
+&gmac0_rgmii_rxin { + bootph-pre-ram; +}; + &gmac0_rmii_refin { bootph-pre-ram; };
+&gmac1_rgmii_rxin { + bootph-pre-ram; +}; + +&gmac1_rmii_refin { + bootph-pre-ram; +}; + +&stmmac_axi_setup { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <4>; +}; + +&gmac0 { + snps,perfect-filter-entries = <8>; +}; + +&gmac1 { + snps,perfect-filter-entries = <8>; +}; + &aoncrg { bootph-pre-ram; };
On Mon, Dec 2, 2024 at 7:05 PM Hal Feng hal.feng@starfivetech.com wrote:
Add u-boot features to the U-Boot device tree.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Acked-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Hal Feng hal.feng@starfivetech.com
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 33 +++++++++++++++--- arch/riscv/dts/jh7110-u-boot.dtsi | 34 +++++++++++++++++++ 2 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi index 3012466b30..7953459e67 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -6,6 +6,10 @@ #include "binman.dtsi" #include "jh7110-u-boot.dtsi" / {
aliases {spi0 = &qspi;};chosen { bootph-pre-ram; };@@ -27,6 +31,9 @@
&uart0 { bootph-pre-ram;
reg-offset = <0>;current-speed = <115200>;clock-frequency = <24000000>;};
&mmc0 { @@ -39,30 +46,45 @@
&qspi { bootph-pre-ram;
spi-max-frequency = <250000000>;
nor-flash@0 {
flash@0 { bootph-pre-ram;/delete-property/ cdns,read-delay;spi-max-frequency = <100000000>; };};
+&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,<&syscrg JH7110_SYSCLK_BUS_ROOT>,<&syscrg JH7110_SYSCLK_PERH_ROOT>,<&syscrg JH7110_SYSCLK_QSPI_REF>;assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,<&pllclk JH7110_PLLCLK_PLL2_OUT>,<&pllclk JH7110_PLLCLK_PLL2_OUT>,<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;assigned-clock-rates = <0>, <0>, <0>, <0>;+};
&sysgpio { bootph-pre-ram; };
&mmc0_pins { bootph-pre-ram;
mmc0-pins-rest {
rst-pins { bootph-pre-ram; };};
&mmc1_pins { bootph-pre-ram;
mmc1-pins0 {
clk-pins { bootph-pre-ram; };
mmc1-pins1 {
mmc-pins { bootph-pre-ram; };}; @@ -78,6 +100,9 @@ bootph-pre-ram; eeprom@50 { bootph-pre-ram;
compatible = "atmel,24c04";reg = <0x50>;pagesize = <16>; };};
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 52c1d60859..21a2ab1789 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -46,6 +46,15 @@ }; };
timer {compatible = "riscv,timer";interrupts-extended = <&cpu0_intc 5>,<&cpu1_intc 5>,<&cpu2_intc 5>,<&cpu3_intc 5>,<&cpu4_intc 5>;};soc { bootph-pre-ram;@@ -73,10 +82,35 @@ bootph-pre-ram; };
+&gmac0_rgmii_rxin {
bootph-pre-ram;+};
&gmac0_rmii_refin { bootph-pre-ram; };
+&gmac1_rgmii_rxin {
bootph-pre-ram;+};
+&gmac1_rmii_refin {
bootph-pre-ram;+};
+&stmmac_axi_setup {
snps,wr_osr_lmt = <4>;snps,rd_osr_lmt = <4>;+};
+&gmac0 {
snps,perfect-filter-entries = <8>;+};
+&gmac1 {
snps,perfect-filter-entries = <8>;+};
Redundant &stmmac_axi_setup &gmac0 &gmac1 property overrides (upstream has all these). Drop.
&aoncrg { bootph-pre-ram; }; -- 2.43.2
There's also a redundant &S7_0 { status = "okay"; }; which can be dropped, it is no-op since that alias is already set to be status="okay".
I tested on Star64 network function and cold boot, is fine. What remains are the liberal use of bootph-pre-ram properties, the DRAM Memory Controller dmc which does not appear yet in Linux, the timer {} node; elsewhere the eeprom and uart of which the eeprom and bootph-pre-ram properties can probably get upstream easily enough later on.
Your choice if you want to trim these redundant properties here or if it should be done as a later clean-up patch, as upstream does not have the same values for these properties all.
-E
On 05.12.24 03:07, E Shattow wrote: On Mon, Dec 2, 2024 at 7:05 PM Hal Feng hal.feng@starfivetech.com wrote:
Add u-boot features to the U-Boot device tree.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Acked-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Hal Feng hal.feng@starfivetech.com
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 33 +++++++++++++++--- arch/riscv/dts/jh7110-u-boot.dtsi | 34 +++++++++++++++++++ 2 files changed, 63 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi index 3012466b30..7953459e67 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -6,6 +6,10 @@ #include "binman.dtsi" #include "jh7110-u-boot.dtsi" / {
aliases {spi0 = &qspi;};chosen { bootph-pre-ram; };@@ -27,6 +31,9 @@
&uart0 { bootph-pre-ram;
reg-offset = <0>;current-speed = <115200>;clock-frequency = <24000000>;};
&mmc0 { @@ -39,30 +46,45 @@
&qspi { bootph-pre-ram;
spi-max-frequency = <250000000>;
nor-flash@0 {
flash@0 { bootph-pre-ram;/delete-property/ cdns,read-delay;spi-max-frequency = <100000000>; };};
+&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,<&syscrg JH7110_SYSCLK_BUS_ROOT>,<&syscrg JH7110_SYSCLK_PERH_ROOT>,<&syscrg JH7110_SYSCLK_QSPI_REF>;assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,<&pllclk JH7110_PLLCLK_PLL2_OUT>,<&pllclk JH7110_PLLCLK_PLL2_OUT>,<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;assigned-clock-rates = <0>, <0>, <0>, <0>; };&sysgpio { bootph-pre-ram; };
&mmc0_pins { bootph-pre-ram;
mmc0-pins-rest {
rst-pins { bootph-pre-ram; };};
&mmc1_pins { bootph-pre-ram;
mmc1-pins0 {
clk-pins { bootph-pre-ram; };
mmc1-pins1 {
mmc-pins { bootph-pre-ram; };}; @@ -78,6 +100,9 @@ bootph-pre-ram; eeprom@50 { bootph-pre-ram;
compatible = "atmel,24c04";reg = <0x50>;pagesize = <16>; };};
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index 52c1d60859..21a2ab1789 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -46,6 +46,15 @@ }; };
timer {compatible = "riscv,timer";interrupts-extended = <&cpu0_intc 5>,<&cpu1_intc 5>,<&cpu2_intc 5>,<&cpu3_intc 5>,<&cpu4_intc 5>;};soc { bootph-pre-ram;@@ -73,10 +82,35 @@ bootph-pre-ram; };
+&gmac0_rgmii_rxin {
bootph-pre-ram;+};
&gmac0_rmii_refin { bootph-pre-ram; };
+&gmac1_rgmii_rxin {
bootph-pre-ram;+};
+&gmac1_rmii_refin {
bootph-pre-ram;+};
+&stmmac_axi_setup {
snps,wr_osr_lmt = <4>;snps,rd_osr_lmt = <4>;+};
+&gmac0 {
snps,perfect-filter-entries = <8>; };+&gmac1 {
snps,perfect-filter-entries = <8>; };Redundant &stmmac_axi_setup &gmac0 &gmac1 property overrides (upstream has all these). Drop.
OK. Actually these properties are unused in U-Boot.
&aoncrg { bootph-pre-ram; }; -- 2.43.2
There's also a redundant &S7_0 { status = "okay"; }; which can be dropped, it is no-op since that alias is already set to be status="okay".
OK. Drop it.
I tested on Star64 network function and cold boot, is fine. What remains are the liberal use of bootph-pre-ram properties, the DRAM Memory Controller dmc which does not appear yet in Linux, the timer {} node; elsewhere the eeprom and uart of which the eeprom and bootph-pre-ram properties can probably get upstream easily enough later on.
Your choice if you want to trim these redundant properties here or if it should be done as a later clean-up patch, as upstream does not have the same values for these properties all.
I prefer to send a clean-up patch after some changes like qspi and eeprom are synced to upstream Linux. Because the clean-up work is not the purpose of this series and I will note all properties this series changes in the cover letter.
Best regards, Hal
Make the U-Boot JH7110 MMC driver compatible with upstream DT.
Signed-off-by: Hal Feng hal.feng@starfivetech.com --- drivers/mmc/snps_dw_mmc.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 47ab5654bd..92880e0ed8 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -186,6 +186,7 @@ static int snps_dwmmc_bind(struct udevice *dev)
static const struct udevice_id snps_dwmmc_ids[] = { { .compatible = "snps,dw-mshc" }, + { .compatible = "starfive,jh7110-mmc" }, { } };
-----Original Message----- From: U-Boot u-boot-bounces@lists.denx.de On Behalf Of Hal Feng Sent: Tuesday, December 3, 2024 12:04 PM To: Leo ycliang@andestech.com; Tom Rini trini@konsulko.com; Sumit Garg sumit.garg@linaro.org; Rick Chen rick@andestech.com; Heinrich Schuchardt xypron.glpk@gmx.de; H Bell dmoo_dv@protonmail.com; E Shattow lucent@gmail.com; Conor Dooley conor.dooley@microchip.com; Nam Cao namcao@linutronix.de; Bo Gan ganboing@gmail.com Cc: Emil Renner Berthing emil.renner.berthing@canonical.com; Minda Chen minda.chen@starfivetech.com; Hal Feng hal.feng@starfivetech.com; u-boot@lists.denx.de Subject: [PATCH v7 03/12] mmc: dw_mmc: Add "starfive, jh7110-mmc" compatible to match upstream DT
Make the U-Boot JH7110 MMC driver compatible with upstream DT.
Signed-off-by: Hal Feng hal.feng@starfivetech.com
Reviewed-by: Jaehoon Chung jh80.chung@samsung.com
Best Regards, Jaehoon Chung
drivers/mmc/snps_dw_mmc.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c index 47ab5654bd..92880e0ed8 100644 --- a/drivers/mmc/snps_dw_mmc.c +++ b/drivers/mmc/snps_dw_mmc.c @@ -186,6 +186,7 @@ static int snps_dwmmc_bind(struct udevice *dev)
static const struct udevice_id snps_dwmmc_ids[] = { { .compatible = "snps,dw-mshc" },
- { .compatible = "starfive,jh7110-mmc" }, { }
};
-- 2.43.2
There are difference between upstream DT and the old DT in terms of reg base, reset gpio and syscon. Make the driver compatible with upstream DT.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com --- drivers/pci/pcie_starfive_jh7110.c | 59 +++++++++++++++--------------- 1 file changed, 30 insertions(+), 29 deletions(-)
diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c index 569fbfd35c..51aca7359f 100644 --- a/drivers/pci/pcie_starfive_jh7110.c +++ b/drivers/pci/pcie_starfive_jh7110.c @@ -25,13 +25,19 @@ #include "pcie_plda_common.h"
/* system control */ -#define STG_SYSCON_K_RP_NEP_MASK BIT(8) +#define STG_SYSCON_PCIE0_BASE 0x48 +#define STG_SYSCON_PCIE1_BASE 0x1f8 + +#define STG_SYSCON_AR_OFFSET 0x78 #define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8) #define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8 +#define STG_SYSCON_AW_OFFSET 0x7c #define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0) #define STG_SYSCON_CLKREQ_MASK BIT(22) #define STG_SYSCON_CKREF_SRC_SHIFT 18 #define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18) +#define STG_SYSCON_RP_NEP_OFFSET 0xe8 +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
DECLARE_GLOBAL_DATA_PTR;
@@ -41,9 +47,7 @@ struct starfive_pcie { struct reset_ctl_bulk rsts; struct gpio_desc reset_gpio; struct regmap *regmap; - u32 stg_arfun; - u32 stg_awfun; - u32 stg_rp_nep; + unsigned int stg_pcie_base; };
static int starfive_pcie_atr_init(struct starfive_pcie *priv) @@ -92,7 +96,6 @@ static int starfive_pcie_get_syscon(struct udevice *dev) struct starfive_pcie *priv = dev_get_priv(dev); struct udevice *syscon; struct ofnode_phandle_args syscfg_phandle; - u32 cells[4]; int ret;
/* get corresponding syscon phandle */ @@ -117,20 +120,6 @@ static int starfive_pcie_get_syscon(struct udevice *dev) return -ENODEV; }
- /* get syscon register offset */ - ret = dev_read_u32_array(dev, "starfive,stg-syscon", - cells, ARRAY_SIZE(cells)); - if (ret) { - dev_err(dev, "Get syscon register err %d\n", ret); - return -EINVAL; - } - - dev_dbg(dev, "Get syscon values: %x, %x, %x\n", - cells[1], cells[2], cells[3]); - priv->stg_arfun = cells[1]; - priv->stg_awfun = cells[2]; - priv->stg_rp_nep = cells[3]; - return 0; }
@@ -138,8 +127,9 @@ static int starfive_pcie_parse_dt(struct udevice *dev) { struct starfive_pcie *priv = dev_get_priv(dev); int ret; + u32 domain_nr;
- priv->plda.reg_base = (void *)dev_read_addr_name(dev, "reg"); + priv->plda.reg_base = (void *)dev_read_addr_name(dev, "apb"); if (priv->plda.reg_base == (void __iomem *)FDT_ADDR_T_NONE) { dev_err(dev, "Missing required reg address range\n"); return -EINVAL; @@ -147,7 +137,7 @@ static int starfive_pcie_parse_dt(struct udevice *dev)
priv->plda.cfg_base = (void *)dev_read_addr_size_name(dev, - "config", + "cfg", &priv->plda.cfg_size); if (priv->plda.cfg_base == (void __iomem *)FDT_ADDR_T_NONE) { dev_err(dev, "Missing required config address range"); @@ -172,7 +162,18 @@ static int starfive_pcie_parse_dt(struct udevice *dev) return ret; }
- ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + ret = dev_read_u32(dev, "linux,pci-domain", &domain_nr); + if (ret) { + dev_err(dev, "Can't get pci domain: %d\n", ret); + return ret; + } + + if (domain_nr == 0) + priv->stg_pcie_base = STG_SYSCON_PCIE0_BASE; + else + priv->stg_pcie_base = STG_SYSCON_PCIE1_BASE; + + ret = gpio_request_by_name(dev, "perst-gpios", 0, &priv->reset_gpio, GPIOD_IS_OUT); if (ret) { dev_err(dev, "Can't get reset-gpio: %d\n", ret); @@ -208,12 +209,12 @@ static int starfive_pcie_init_port(struct udevice *dev) /* Disable physical functions except #0 */ for (i = 1; i < PLDA_FUNC_NUM; i++) { regmap_update_bits(priv->regmap, - priv->stg_arfun, + priv->stg_pcie_base + STG_SYSCON_AR_OFFSET, STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, (i << PLDA_PHY_FUNC_SHIFT) << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, i << PLDA_PHY_FUNC_SHIFT);
@@ -222,11 +223,11 @@ static int starfive_pcie_init_port(struct udevice *dev)
/* Disable physical functions */ regmap_update_bits(priv->regmap, - priv->stg_arfun, + priv->stg_pcie_base + STG_SYSCON_AR_OFFSET, STG_SYSCON_AXI4_SLVL_ARFUNC_MASK, 0); regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_AXI4_SLVL_AWFUNC_MASK, 0);
@@ -273,17 +274,17 @@ static int starfive_pcie_probe(struct udevice *dev) return ret;
regmap_update_bits(priv->regmap, - priv->stg_rp_nep, + priv->stg_pcie_base + STG_SYSCON_RP_NEP_OFFSET, STG_SYSCON_K_RP_NEP_MASK, STG_SYSCON_K_RP_NEP_MASK);
regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_CKREF_SRC_MASK, 2 << STG_SYSCON_CKREF_SRC_SHIFT);
regmap_update_bits(priv->regmap, - priv->stg_awfun, + priv->stg_pcie_base + STG_SYSCON_AW_OFFSET, STG_SYSCON_CLKREQ_MASK, STG_SYSCON_CLKREQ_MASK);
To support JH7110 based boards besides v1.3B, add a common dtsi and add common code to it.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com --- arch/riscv/dts/jh7110-common-u-boot.dtsi | 142 ++++++++++++++++++ ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 138 +---------------- 2 files changed, 143 insertions(+), 137 deletions(-) create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi new file mode 100644 index 0000000000..7953459e67 --- /dev/null +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include "binman.dtsi" +#include "jh7110-u-boot.dtsi" +/ { + aliases { + spi0 = &qspi; + }; + + chosen { + bootph-pre-ram; + }; + + firmware { + spi0 = &qspi; + bootph-pre-ram; + }; + + config { + bootph-pre-ram; + u-boot,spl-payload-offset = <0x100000>; + }; + + memory@40000000 { + bootph-pre-ram; + }; +}; + +&uart0 { + bootph-pre-ram; + reg-offset = <0>; + current-speed = <115200>; + clock-frequency = <24000000>; +}; + +&mmc0 { + bootph-pre-ram; +}; + +&mmc1 { + bootph-pre-ram; +}; + +&qspi { + bootph-pre-ram; + spi-max-frequency = <250000000>; + + flash@0 { + bootph-pre-ram; + /delete-property/ cdns,read-delay; + spi-max-frequency = <100000000>; + }; +}; + +&syscrg { + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, + <&syscrg JH7110_SYSCLK_BUS_ROOT>, + <&syscrg JH7110_SYSCLK_PERH_ROOT>, + <&syscrg JH7110_SYSCLK_QSPI_REF>; + assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>, + <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; + assigned-clock-rates = <0>, <0>, <0>, <0>; +}; + +&sysgpio { + bootph-pre-ram; +}; + +&mmc0_pins { + bootph-pre-ram; + rst-pins { + bootph-pre-ram; + }; +}; + +&mmc1_pins { + bootph-pre-ram; + clk-pins { + bootph-pre-ram; + }; + + mmc-pins { + bootph-pre-ram; + }; +}; + +&i2c5_pins { + bootph-pre-ram; + i2c-pins { + bootph-pre-ram; + }; +}; + +&i2c5 { + bootph-pre-ram; + eeprom@50 { + bootph-pre-ram; + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&binman { + itb { + fit { + images { + fdt-1 { + description = "NAME"; + load = <0x40400000>; + compression = "none"; + + uboot_fdt_blob: blob-ext { + filename = "u-boot.dtb"; + }; + }; + }; + + configurations { + conf-1 { + fdt = "fdt-1"; + }; + }; + }; + }; + + spl-img { + filename = "spl/u-boot-spl.bin.normal.out"; + + mkimage { + args = "-T sfspl"; + + u-boot-spl { + }; + }; + }; +}; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi index 7953459e67..e6bc6630dc 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -3,140 +3,4 @@ * Copyright (C) 2023 StarFive Technology Co., Ltd. */
-#include "binman.dtsi" -#include "jh7110-u-boot.dtsi" -/ { - aliases { - spi0 = &qspi; - }; - - chosen { - bootph-pre-ram; - }; - - firmware { - spi0 = &qspi; - bootph-pre-ram; - }; - - config { - bootph-pre-ram; - u-boot,spl-payload-offset = <0x100000>; - }; - - memory@40000000 { - bootph-pre-ram; - }; -}; - -&uart0 { - bootph-pre-ram; - reg-offset = <0>; - current-speed = <115200>; - clock-frequency = <24000000>; -}; - -&mmc0 { - bootph-pre-ram; -}; - -&mmc1 { - bootph-pre-ram; -}; - -&qspi { - bootph-pre-ram; - spi-max-frequency = <250000000>; - - flash@0 { - bootph-pre-ram; - /delete-property/ cdns,read-delay; - spi-max-frequency = <100000000>; - }; -}; - -&syscrg { - assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>, - <&syscrg JH7110_SYSCLK_BUS_ROOT>, - <&syscrg JH7110_SYSCLK_PERH_ROOT>, - <&syscrg JH7110_SYSCLK_QSPI_REF>; - assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>, - <&pllclk JH7110_PLLCLK_PLL2_OUT>, - <&pllclk JH7110_PLLCLK_PLL2_OUT>, - <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; - assigned-clock-rates = <0>, <0>, <0>, <0>; -}; - -&sysgpio { - bootph-pre-ram; -}; - -&mmc0_pins { - bootph-pre-ram; - rst-pins { - bootph-pre-ram; - }; -}; - -&mmc1_pins { - bootph-pre-ram; - clk-pins { - bootph-pre-ram; - }; - - mmc-pins { - bootph-pre-ram; - }; -}; - -&i2c5_pins { - bootph-pre-ram; - i2c-pins { - bootph-pre-ram; - }; -}; - -&i2c5 { - bootph-pre-ram; - eeprom@50 { - bootph-pre-ram; - compatible = "atmel,24c04"; - reg = <0x50>; - pagesize = <16>; - }; -}; - -&binman { - itb { - fit { - images { - fdt-1 { - description = "NAME"; - load = <0x40400000>; - compression = "none"; - - uboot_fdt_blob: blob-ext { - filename = "u-boot.dtb"; - }; - }; - }; - - configurations { - conf-1 { - fdt = "fdt-1"; - }; - }; - }; - }; - - spl-img { - filename = "spl/u-boot-spl.bin.normal.out"; - - mkimage { - args = "-T sfspl"; - - u-boot-spl { - }; - }; - }; -}; +#include "jh7110-common-u-boot.dtsi"
On Mon, Dec 2, 2024 at 7:06 PM Hal Feng hal.feng@starfivetech.com wrote:
To support JH7110 based boards besides v1.3B, add a common dtsi and add common code to it.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com
arch/riscv/dts/jh7110-common-u-boot.dtsi | 142 ++++++++++++++++++ ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 138 +---------------- 2 files changed, 143 insertions(+), 137 deletions(-) create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi new file mode 100644 index 0000000000..7953459e67 --- /dev/null +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/*
- Copyright (C) 2023 StarFive Technology Co., Ltd.
- */
+#include "binman.dtsi" +#include "jh7110-u-boot.dtsi" +/ {
aliases {spi0 = &qspi;};chosen {bootph-pre-ram;};firmware {spi0 = &qspi;bootph-pre-ram;};config {bootph-pre-ram;u-boot,spl-payload-offset = <0x100000>;};memory@40000000 {bootph-pre-ram;};+};
+&uart0 {
bootph-pre-ram;reg-offset = <0>;current-speed = <115200>;clock-frequency = <24000000>;+};
+&mmc0 {
bootph-pre-ram;+};
+&mmc1 {
bootph-pre-ram;+};
+&qspi {
bootph-pre-ram;
spi-max-frequency = <250000000>;
Drop this line spi-max-frequency 250Mhz. The driver expects spi-max-frequency in any sub-node, and not here?
flash@0 {bootph-pre-ram;
/delete-property/ cdns,read-delay;
Drop this line /delete-property/ because it is a problem for the parser if we need to re-define 'cdns,read-delay' later in dts files downstream of jh7110-common-u-boot.dtsi
If you want drivers/spi/cadence_qspi.c:spi_calibration() to do this work then it needs to be the same upstream. In my testing on 4GB Star64 the calibration (via /delete-property/ cdns,read-delay) method with spi-max-frequency less than exactly 49.8MHz results in a failure to write SPI-NOR correctly. When spi-max-frequency is approximately 25MHz up to 49.799999MHz and written with a known good tool then the boot may be successful but "Main section boot fail,use backup section" or other errors on boot after using that unstable configuration of U-Boot to write U-Boot image to the SPI-NOR. No problems writing and boot during testing with spi-max-frequency 49.8MHz up to 100MHz (not tested above 100MHz).
The upstream dts has spi-max-frequency 12MHz which is not successful with any of the read-delay values I tested: 0 1 2 3 4 5
spi-max-frequency = <100000000>;
Why 12MHz upstream and 100MHz here? Something is wrong but I do not know is it U-Boot or Linux?
Success: + /delete-property/ cdns,read-delay; + spi-max-frequency = <100000000>;
Success: + cdns,read-delay = <2>; - /delete-property/ cdns,read-delay; + spi-max-frequency = <100000000>;
Failure: + cdns,read-delay = <2>; + spi-max-frequency = <50000000>;
The actual fix is going to need testing Linux and U-Boot on all the boards I do not have access to.
For the moment we can: - /delete-property/ cdns,read-delay; + cdns,read-delay = <2>; + spi-max-frequency = <100000000>;
or do nothing (but yes please drop that 250Mhz line it is non-op I think).
What do you think? Or else we discuss here and follow with patches in future to fix the mess. I really do not want any /delete-property/ to be in dtsi but I don't know why it is so different between U-Boot and Linux and cannot personally test all the possible boards to verify a change.
};+};
+&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,<&syscrg JH7110_SYSCLK_BUS_ROOT>,<&syscrg JH7110_SYSCLK_PERH_ROOT>,<&syscrg JH7110_SYSCLK_QSPI_REF>;assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,<&pllclk JH7110_PLLCLK_PLL2_OUT>,<&pllclk JH7110_PLLCLK_PLL2_OUT>,<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;assigned-clock-rates = <0>, <0>, <0>, <0>;+};
+&sysgpio {
bootph-pre-ram;+};
+&mmc0_pins {
bootph-pre-ram;rst-pins {bootph-pre-ram;};+};
+&mmc1_pins {
bootph-pre-ram;clk-pins {bootph-pre-ram;};mmc-pins {bootph-pre-ram;};+};
+&i2c5_pins {
bootph-pre-ram;i2c-pins {bootph-pre-ram;};+};
+&i2c5 {
bootph-pre-ram;eeprom@50 {bootph-pre-ram;compatible = "atmel,24c04";reg = <0x50>;pagesize = <16>;};+};
+&binman {
itb {fit {images {fdt-1 {description = "NAME";load = <0x40400000>;compression = "none";uboot_fdt_blob: blob-ext {filename = "u-boot.dtb";};};};configurations {conf-1 {fdt = "fdt-1";};};};};spl-img {filename = "spl/u-boot-spl.bin.normal.out";mkimage {args = "-T sfspl";u-boot-spl {};};};+}; diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi index 7953459e67..e6bc6630dc 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi @@ -3,140 +3,4 @@
- Copyright (C) 2023 StarFive Technology Co., Ltd.
*/
-#include "binman.dtsi" -#include "jh7110-u-boot.dtsi" -/ {
aliases {spi0 = &qspi;};chosen {bootph-pre-ram;};firmware {spi0 = &qspi;bootph-pre-ram;};config {bootph-pre-ram;u-boot,spl-payload-offset = <0x100000>;};memory@40000000 {bootph-pre-ram;};-};
-&uart0 {
bootph-pre-ram;reg-offset = <0>;current-speed = <115200>;clock-frequency = <24000000>;-};
-&mmc0 {
bootph-pre-ram;-};
-&mmc1 {
bootph-pre-ram;-};
-&qspi {
bootph-pre-ram;spi-max-frequency = <250000000>;flash@0 {bootph-pre-ram;/delete-property/ cdns,read-delay;spi-max-frequency = <100000000>;};-};
-&syscrg {
assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,<&syscrg JH7110_SYSCLK_BUS_ROOT>,<&syscrg JH7110_SYSCLK_PERH_ROOT>,<&syscrg JH7110_SYSCLK_QSPI_REF>;assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,<&pllclk JH7110_PLLCLK_PLL2_OUT>,<&pllclk JH7110_PLLCLK_PLL2_OUT>,<&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;assigned-clock-rates = <0>, <0>, <0>, <0>;-};
-&sysgpio {
bootph-pre-ram;-};
-&mmc0_pins {
bootph-pre-ram;rst-pins {bootph-pre-ram;};-};
-&mmc1_pins {
bootph-pre-ram;clk-pins {bootph-pre-ram;};mmc-pins {bootph-pre-ram;};-};
-&i2c5_pins {
bootph-pre-ram;i2c-pins {bootph-pre-ram;};-};
-&i2c5 {
bootph-pre-ram;eeprom@50 {bootph-pre-ram;compatible = "atmel,24c04";reg = <0x50>;pagesize = <16>;};-};
-&binman {
itb {fit {images {fdt-1 {description = "NAME";load = <0x40400000>;compression = "none";uboot_fdt_blob: blob-ext {filename = "u-boot.dtb";};};};configurations {conf-1 {fdt = "fdt-1";};};};};spl-img {filename = "spl/u-boot-spl.bin.normal.out";mkimage {args = "-T sfspl";u-boot-spl {};};};-};
+#include "jh7110-common-u-boot.dtsi"
2.43.2
-E
On 04.12.24 03:16, E Shattow wrote: On Mon, Dec 2, 2024 at 7:06 PM Hal Feng hal.feng@starfivetech.com wrote:
To support JH7110 based boards besides v1.3B, add a common dtsi and add common code to it.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com
arch/riscv/dts/jh7110-common-u-boot.dtsi | 142
++++++++++++++++++
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 138 +---------------- 2 files changed, 143 insertions(+), 137 deletions(-) create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi new file mode 100644 index 0000000000..7953459e67 --- /dev/null +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/*
- Copyright (C) 2023 StarFive Technology Co., Ltd.
- */
+#include "binman.dtsi" +#include "jh7110-u-boot.dtsi" +/ {
aliases {spi0 = &qspi;};chosen {bootph-pre-ram;};firmware {spi0 = &qspi;bootph-pre-ram;};config {bootph-pre-ram;u-boot,spl-payload-offset = <0x100000>;};memory@40000000 {bootph-pre-ram;};+};
+&uart0 {
bootph-pre-ram;reg-offset = <0>;current-speed = <115200>;clock-frequency = <24000000>;+};
+&mmc0 {
bootph-pre-ram;+};
+&mmc1 {
bootph-pre-ram;+};
+&qspi {
bootph-pre-ram;
spi-max-frequency = <250000000>;Drop this line spi-max-frequency 250Mhz. The driver expects spi-max- frequency in any sub-node, and not here?
Yes, this property is used in sub-node, we can drop this later.
flash@0 {bootph-pre-ram;
/delete-property/ cdns,read-delay;Drop this line /delete-property/ because it is a problem for the parser if we need to re-define 'cdns,read-delay' later in dts files downstream of jh7110- common-u-boot.dtsi
If you want drivers/spi/cadence_qspi.c:spi_calibration() to do this work then it needs to be the same upstream. In my testing on 4GB Star64 the calibration (via /delete-property/ cdns,read-delay) method with spi-max-frequency less than exactly 49.8MHz results in a failure to write SPI- NOR correctly. When spi-max-frequency is approximately 25MHz up to 49.799999MHz and written with a known good tool then the boot may be successful but "Main section boot fail,use backup section" or other errors on boot after using that unstable configuration of U-Boot to write U-Boot image to the SPI-NOR. No problems writing and boot during testing with spi-max-frequency 49.8MHz up to 100MHz (not tested above 100MHz).
The upstream dts has spi-max-frequency 12MHz which is not successful with any of the read-delay values I tested: 0 1 2 3 4 5
spi-max-frequency = <100000000>;Why 12MHz upstream and 100MHz here? Something is wrong but I do not know is it U-Boot or Linux?
Success:
/delete-property/ cdns,read-delay;spi-max-frequency = <100000000>;Success:
cdns,read-delay = <2>;
/delete-property/ cdns,read-delay;
spi-max-frequency = <100000000>;Failure:
cdns,read-delay = <2>;spi-max-frequency = <50000000>;The actual fix is going to need testing Linux and U-Boot on all the boards I do not have access to.
For the moment we can:
/delete-property/ cdns,read-delay;
cdns,read-delay = <2>;spi-max-frequency = <100000000>;or do nothing (but yes please drop that 250Mhz line it is non-op I think).
What do you think? Or else we discuss here and follow with patches in future to fix the mess. I really do not want any /delete-property/ to be in dtsi but I don't know why it is so different between U-Boot and Linux and cannot personally test all the possible boards to verify a change.
I don't know the cause of this problem either. But all properties added in this patch already existed in U-Boot DT before. I tried my best to keep the U-Boot DT the same as the one before OF_UPSTREAM applied.
I tested and found that the qspi flash can work successfully in Linux and U-Boot with the settings you suggested above.
cdns,read-delay = <2>; spi-max-frequency = <100000000>;
If /delete-property/ is really not suitable to exist in this dtsi, we can modify as above in U-Boot and upstream this change to Liunx. After this change is accepted by Linux, I will drop these two properties in U-Boot.
Best regards, Hal
On Tue, Dec 3, 2024 at 10:52 PM Hal Feng hal.feng@starfivetech.com wrote:
On 04.12.24 03:16, E Shattow wrote: On Mon, Dec 2, 2024 at 7:06 PM Hal Feng hal.feng@starfivetech.com wrote:
To support JH7110 based boards besides v1.3B, add a common dtsi and add common code to it.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com
arch/riscv/dts/jh7110-common-u-boot.dtsi | 142
++++++++++++++++++
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 138 +---------------- 2 files changed, 143 insertions(+), 137 deletions(-) create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi new file mode 100644 index 0000000000..7953459e67 --- /dev/null +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/*
- Copyright (C) 2023 StarFive Technology Co., Ltd.
- */
+#include "binman.dtsi" +#include "jh7110-u-boot.dtsi" +/ {
aliases {spi0 = &qspi;};chosen {bootph-pre-ram;};firmware {spi0 = &qspi;bootph-pre-ram;};config {bootph-pre-ram;u-boot,spl-payload-offset = <0x100000>;};memory@40000000 {bootph-pre-ram;};+};
+&uart0 {
bootph-pre-ram;reg-offset = <0>;current-speed = <115200>;clock-frequency = <24000000>;+};
+&mmc0 {
bootph-pre-ram;+};
+&mmc1 {
bootph-pre-ram;+};
+&qspi {
bootph-pre-ram;
spi-max-frequency = <250000000>;Drop this line spi-max-frequency 250Mhz. The driver expects spi-max- frequency in any sub-node, and not here?
Yes, this property is used in sub-node, we can drop this later.
flash@0 {bootph-pre-ram;
/delete-property/ cdns,read-delay;Drop this line /delete-property/ because it is a problem for the parser if we need to re-define 'cdns,read-delay' later in dts files downstream of jh7110- common-u-boot.dtsi
If you want drivers/spi/cadence_qspi.c:spi_calibration() to do this work then it needs to be the same upstream. In my testing on 4GB Star64 the calibration (via /delete-property/ cdns,read-delay) method with spi-max-frequency less than exactly 49.8MHz results in a failure to write SPI- NOR correctly. When spi-max-frequency is approximately 25MHz up to 49.799999MHz and written with a known good tool then the boot may be successful but "Main section boot fail,use backup section" or other errors on boot after using that unstable configuration of U-Boot to write U-Boot image to the SPI-NOR. No problems writing and boot during testing with spi-max-frequency 49.8MHz up to 100MHz (not tested above 100MHz).
The upstream dts has spi-max-frequency 12MHz which is not successful with any of the read-delay values I tested: 0 1 2 3 4 5
spi-max-frequency = <100000000>;Why 12MHz upstream and 100MHz here? Something is wrong but I do not know is it U-Boot or Linux?
Success:
/delete-property/ cdns,read-delay;spi-max-frequency = <100000000>;Success:
cdns,read-delay = <2>;
/delete-property/ cdns,read-delay;
spi-max-frequency = <100000000>;Failure:
cdns,read-delay = <2>;spi-max-frequency = <50000000>;The actual fix is going to need testing Linux and U-Boot on all the boards I do not have access to.
For the moment we can:
/delete-property/ cdns,read-delay;
cdns,read-delay = <2>;spi-max-frequency = <100000000>;or do nothing (but yes please drop that 250Mhz line it is non-op I think).
What do you think? Or else we discuss here and follow with patches in future to fix the mess. I really do not want any /delete-property/ to be in dtsi but I don't know why it is so different between U-Boot and Linux and cannot personally test all the possible boards to verify a change.
I don't know the cause of this problem either. But all properties added in this patch already existed in U-Boot DT before. I tried my best to keep the U-Boot DT the same as the one before OF_UPSTREAM applied.
I tested and found that the qspi flash can work successfully in Linux and U-Boot with the settings you suggested above.
cdns,read-delay = <2>; spi-max-frequency = <100000000>;
Good report on testing Linux and U-Boot, thank you Hal.
If /delete-property/ is really not suitable to exist in this dtsi, we can modify as above in U-Boot and upstream this change to Liunx. After this change is accepted by Linux, I will drop these two properties in U-Boot.
Best regards, Hal
Yes let's do that. So long as it all works on VF2 1.2a, VF 1.3b, Mars, and Star64. I have tested Star64. You have tested I guess VF2 1.3b? And if we miss some, it's okay even if there is a problem for some board we did not test, the workaround is easy in u-boot specific dtsi per-board because we have avoided '/delete-property/' in the common dtsi.
-E
On 04.12.24 18:56, E Shattow wrote: On Tue, Dec 3, 2024 at 10:52 PM Hal Feng hal.feng@starfivetech.com wrote:
On 04.12.24 03:16, E Shattow wrote: On Mon, Dec 2, 2024 at 7:06 PM Hal Feng hal.feng@starfivetech.com wrote:
To support JH7110 based boards besides v1.3B, add a common dtsi and add common code to it.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com
arch/riscv/dts/jh7110-common-u-boot.dtsi | 142
++++++++++++++++++
...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 138 +---------------- 2 files changed, 143 insertions(+), 137 deletions(-) create mode 100644 arch/riscv/dts/jh7110-common-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi new file mode 100644 index 0000000000..7953459e67 --- /dev/null +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/*
- Copyright (C) 2023 StarFive Technology Co., Ltd.
- */
+#include "binman.dtsi" +#include "jh7110-u-boot.dtsi" +/ {
aliases {spi0 = &qspi;};chosen {bootph-pre-ram;};firmware {spi0 = &qspi;bootph-pre-ram;};config {bootph-pre-ram;u-boot,spl-payload-offset = <0x100000>;};memory@40000000 {bootph-pre-ram;};+};
+&uart0 {
bootph-pre-ram;reg-offset = <0>;current-speed = <115200>;clock-frequency = <24000000>; };+&mmc0 {
bootph-pre-ram;+};
+&mmc1 {
bootph-pre-ram;+};
+&qspi {
bootph-pre-ram;
spi-max-frequency = <250000000>;Drop this line spi-max-frequency 250Mhz. The driver expects spi-max- frequency in any sub-node, and not here?
Yes, this property is used in sub-node, we can drop this later.
flash@0 {bootph-pre-ram;
/delete-property/ cdns,read-delay;Drop this line /delete-property/ because it is a problem for the parser if we need to re-define 'cdns,read-delay' later in dts files downstream of jh7110- common-u-boot.dtsi
If you want drivers/spi/cadence_qspi.c:spi_calibration() to do this work then it needs to be the same upstream. In my testing on 4GB Star64 the calibration (via /delete-property/ cdns,read-delay) method with spi-max-frequency less than exactly 49.8MHz results in a failure to write SPI- NOR correctly. When spi-max-frequency is approximately 25MHz up to 49.799999MHz and written with a known
good
tool then the boot may be successful but "Main section boot fail,use
backup section"
or other errors on boot after using that unstable configuration of U-Boot to write U-Boot image to the SPI-NOR. No problems writing and boot during testing with spi-max-frequency 49.8MHz up to 100MHz (not tested above 100MHz).
The upstream dts has spi-max-frequency 12MHz which is not successful with any of the read-delay values I tested: 0 1 2 3 4 5
spi-max-frequency = <100000000>;Why 12MHz upstream and 100MHz here? Something is wrong but I do not know is it U-Boot or Linux?
Success:
/delete-property/ cdns,read-delay;spi-max-frequency = <100000000>;Success:
cdns,read-delay = <2>;
/delete-property/ cdns,read-delay;
spi-max-frequency = <100000000>;Failure:
cdns,read-delay = <2>;spi-max-frequency = <50000000>;The actual fix is going to need testing Linux and U-Boot on all the boards I do not have access to.
For the moment we can:
/delete-property/ cdns,read-delay;
cdns,read-delay = <2>;spi-max-frequency = <100000000>;or do nothing (but yes please drop that 250Mhz line it is non-op I think).
What do you think? Or else we discuss here and follow with patches in future to fix the mess. I really do not want any /delete-property/ to be in dtsi but I don't know why it is so different between U-Boot and Linux and cannot personally test all the
possible boards to verify a change.
I don't know the cause of this problem either. But all properties added in this patch already existed in U-Boot DT before. I tried my best to keep the U-Boot DT the same as the one before OF_UPSTREAM
applied.
I tested and found that the qspi flash can work successfully in Linux and U-Boot with the settings you suggested above.
cdns,read-delay = <2>; spi-max-frequency = <100000000>;
Good report on testing Linux and U-Boot, thank you Hal.
If /delete-property/ is really not suitable to exist in this dtsi, we can modify as above in U-Boot and upstream this change to Liunx. After this change is accepted by Linux, I will drop these two properties in U-Boot.
Best regards, Hal
Yes let's do that. So long as it all works on VF2 1.2a, VF 1.3b, Mars, and Star64. I have tested Star64. You have tested I guess VF2 1.3b? And if we miss some, it's okay even if there is a problem for some board we did not test, the workaround is easy in u-boot specific dtsi per-board because we have avoided '/delete-property/' in the common dtsi.
OK. Yeah, I tested on VF2 1.3b and VF2 1.2a is very similar to VF2 1.3b.
Best regards, Hal
To support the other JH7110 based boards, add u-boot device tree for them.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Cc: Heinrich Schuchardt xypron.glpk@gmx.de Cc: H Bell dmoo_dv@protonmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com --- arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi | 6 ++++++ arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi | 6 ++++++ .../dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi | 6 ++++++ 3 files changed, 18 insertions(+) create mode 100644 arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi create mode 100644 arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
diff --git a/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi new file mode 100644 index 0000000000..9df1e5db55 --- /dev/null +++ b/arch/riscv/dts/jh7110-milkv-mars-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + */ + +#include "jh7110-common-u-boot.dtsi" diff --git a/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi new file mode 100644 index 0000000000..9df1e5db55 --- /dev/null +++ b/arch/riscv/dts/jh7110-pine64-star64-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + */ + +#include "jh7110-common-u-boot.dtsi" diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi new file mode 100644 index 0000000000..9df1e5db55 --- /dev/null +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + */ + +#include "jh7110-common-u-boot.dtsi"
As OF_UPSTREAM is implemented, these code are redundant.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com --- board/starfive/visionfive2/spl.c | 356 ------------------------------- 1 file changed, 356 deletions(-)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index 3fd535e7cf..38132ecccd 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -20,364 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; #define JH7110_CLK_CPU_ROOT_SHIFT 24 #define JH7110_CLK_CPU_ROOT_MASK GENMASK(29, 24)
-struct starfive_vf2_pro { - const char *path; - const char *name; - const char *value; -}; - -static const struct starfive_vf2_pro milk_v_mars[] = { - {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, - {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, - - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-adj-enabled", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-100-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-1000-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-clk-drv-microamp", "3970"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-data-drv-microamp", "2910"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "rx-internal-delay-ps", "1500"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "tx-internal-delay-ps", "1500"}, -}; - -static const struct starfive_vf2_pro starfive_vera[] = { - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "rx-internal-delay-ps", - "1900"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", "tx-internal-delay-ps", - "1350"} -}; - -static const struct starfive_vf2_pro starfive_verb[] = { - {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, - {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, - - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-adj-enabled", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-100-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-1000-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-clk-drv-microamp", "3970"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-data-drv-microamp", "2910"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "rx-internal-delay-ps", "1500"}, - - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,tx-clk-adj-enabled", NULL}, - { "/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,tx-clk-100-inverted", NULL}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,rx-clk-drv-microamp", "3970"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,rx-data-drv-microamp", "2910"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "rx-internal-delay-ps", "0"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "tx-internal-delay-ps", "0"}, -}; - -static const struct starfive_vf2_pro star64_pine64[] = { - {"/soc/ethernet@16030000", "starfive,tx-use-rgmii-clk", NULL}, - {"/soc/ethernet@16040000", "starfive,tx-use-rgmii-clk", NULL}, - - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-adj-enabled", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-10-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-100-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,tx-clk-1000-inverted", NULL}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-clk-drv-microamp", "2910"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "motorcomm,rx-data-drv-microamp", "2910"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "rx-internal-delay-ps", "1900"}, - {"/soc/ethernet@16030000/mdio/ethernet-phy@0", - "tx-internal-delay-ps", "1500"}, - - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,tx-clk-adj-enabled", NULL}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,tx-clk-10-inverted", NULL}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,tx-clk-100-inverted", NULL}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,rx-clk-drv-microamp", "2910"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "motorcomm,rx-data-drv-microamp", "2910"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "rx-internal-delay-ps", "0"}, - {"/soc/ethernet@16040000/mdio/ethernet-phy@1", - "tx-internal-delay-ps", "300"}, -}; - -void spl_fdt_fixup_mars(void *fdt) -{ - static const char compat[] = "milkv,mars\0starfive,jh7110"; - u32 phandle; - u8 i; - int offset; - int ret; - - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", - "Milk-V Mars"); - - /* gmac0 */ - offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_AONCLK_GMAC0_RMII_RTX); - - /* gmac1 */ - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"), - "status", "disabled"); - - for (i = 0; i < ARRAY_SIZE(milk_v_mars); i++) { - offset = fdt_path_offset(fdt, milk_v_mars[i].path); - - if (milk_v_mars[i].value) - ret = fdt_setprop_u32(fdt, offset, milk_v_mars[i].name, - dectoul(milk_v_mars[i].value, NULL)); - else - ret = fdt_setprop_empty(fdt, offset, milk_v_mars[i].name); - - if (ret) { - pr_err("%s set prop %s fail.\n", __func__, milk_v_mars[i].name); - break; - } - } -} - -void spl_fdt_fixup_mars_cm(void *fdt) -{ - const char *compat; - const char *model; - int compat_size; - - spl_fdt_fixup_mars(fdt); - - if (!get_mmc_size_from_eeprom()) { - int offset; - static const char - compat_cm_lite[] = "milkv,mars-cm-lite\0starfive,jh7110"; - - model = "Milk-V Mars CM Lite"; - compat = compat_cm_lite; - compat_size = sizeof(compat_cm_lite); - - offset = fdt_path_offset(fdt, "/soc/pinctrl/mmc0-pins/mmc0-pins-rest"); - /* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */ - fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016); - } else { - static const char - compat_cm[] = "milkv,mars-cm\0starfive,jh7110"; - - model = "Milk-V Mars CM"; - compat = compat_cm; - compat_size = sizeof(compat_cm); - } - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), - "compatible", compat, compat_size); - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model); -} - -void spl_fdt_fixup_version_a(void *fdt) -{ - static const char compat[] = "starfive,visionfive-2-v1.2a\0starfive,jh7110"; - u32 phandle; - u8 i; - int offset; - int ret; - - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", - "StarFive VisionFive 2 v1.2A"); - - offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_RX); - - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_SYSCLK_GMAC1_RMII_RTX); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_SYSCLK_GMAC1_RMII_RTX); - - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/soc/ethernet@16040000"), - "phy-mode", "rmii"); - - for (i = 0; i < ARRAY_SIZE(starfive_vera); i++) { - offset = fdt_path_offset(fdt, starfive_vera[i].path); - - if (starfive_vera[i].value) - ret = fdt_setprop_u32(fdt, offset, starfive_vera[i].name, - dectoul(starfive_vera[i].value, NULL)); - else - ret = fdt_setprop_empty(fdt, offset, starfive_vera[i].name); - - if (ret) { - pr_err("%s set prop %s fail.\n", __func__, starfive_vera[i].name); - break; - } - } -} - -void spl_fdt_fixup_version_b(void *fdt) -{ - static const char compat[] = "starfive,visionfive-2-v1.3b\0starfive,jh7110"; - u32 phandle; - u8 i; - int offset; - int ret; - - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", - "StarFive VisionFive 2 v1.3B"); - - /* gmac0 */ - offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_AONCLK_GMAC0_RMII_RTX); - - /* gmac1 */ - offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_SYSCLK_GMAC1_RMII_RTX); - - for (i = 0; i < ARRAY_SIZE(starfive_verb); i++) { - offset = fdt_path_offset(fdt, starfive_verb[i].path); - - if (starfive_verb[i].value) - ret = fdt_setprop_u32(fdt, offset, starfive_verb[i].name, - dectoul(starfive_verb[i].value, NULL)); - else - ret = fdt_setprop_empty(fdt, offset, starfive_verb[i].name); - - if (ret) { - pr_err("%s set prop %s fail.\n", __func__, starfive_verb[i].name); - break; - } - } -} - -void spl_fdt_fixup_star64(void *fdt) -{ - static const char compat[] = "pine64,star64\0starfive,jh7110"; - u32 phandle; - u8 i; - int offset; - int ret; - - fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat, sizeof(compat)); - fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", - "Pine64 Star64"); - - /* gmac0 */ - offset = fdt_path_offset(fdt, "/soc/clock-controller@17000000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16030000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_AONCLK_GMAC0_TX); - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_AONCLK_GMAC0_RMII_RTX); - - /* gmac1 */ - offset = fdt_path_offset(fdt, "/soc/clock-controller@13020000"); - phandle = fdt_get_phandle(fdt, offset); - offset = fdt_path_offset(fdt, "/soc/ethernet@16040000"); - - fdt_setprop_u32(fdt, offset, "assigned-clocks", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clocks", JH7110_SYSCLK_GMAC1_TX); - fdt_setprop_u32(fdt, offset, "assigned-clock-parents", phandle); - fdt_appendprop_u32(fdt, offset, "assigned-clock-parents", - JH7110_SYSCLK_GMAC1_RMII_RTX); - - for (i = 0; i < ARRAY_SIZE(star64_pine64); i++) { - offset = fdt_path_offset(fdt, star64_pine64[i].path); - - if (star64_pine64[i].value) - ret = fdt_setprop_u32(fdt, offset, star64_pine64[i].name, - dectoul(star64_pine64[i].value, NULL)); - else - ret = fdt_setprop_empty(fdt, offset, star64_pine64[i].name); - - if (ret) { - pr_err("%s set prop %s fail.\n", __func__, star64_pine64[i].name); - break; - } - } -} - void spl_perform_fixups(struct spl_image_info *spl_image) { - u8 version; - const char *product_id; - - product_id = get_product_id_from_eeprom(); - if (!product_id) { - pr_err("Can't read EEPROM\n"); - return; - } - if (!strncmp(product_id, "MARC", 4)) { - spl_fdt_fixup_mars_cm(spl_image->fdt_addr); - } else if (!strncmp(product_id, "MARS", 4)) { - spl_fdt_fixup_mars(spl_image->fdt_addr); - } else if (!strncmp(product_id, "VF7110", 6)) { - version = get_pcb_revision_from_eeprom(); - switch (version) { - case 'a': - case 'A': - spl_fdt_fixup_version_a(spl_image->fdt_addr); - break; - - case 'b': - case 'B': - default: - spl_fdt_fixup_version_b(spl_image->fdt_addr); - break; - }; - } else if (!strncmp(product_id, "STAR64", 6)) { - spl_fdt_fixup_star64(spl_image->fdt_addr); - } else { - pr_err("Unknown product %s\n", product_id); - }; - /* Update the memory size which read from eeprom or DT */ fdt_fixup_memory(spl_image->fdt_addr, 0x40000000, gd->ram_size); }
So JH7110 based boards can select their own DT at runtime.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com --- configs/starfive_visionfive2_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 3385c25b3f..b19931fb0a 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -82,6 +82,8 @@ CONFIG_CMD_WDT=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_BOARD=y +CONFIG_OF_LIST="starfive/jh7110-milkv-mars starfive/jh7110-pine64-star64 starfive/jh7110-starfive-visionfive-2-v1.2a starfive/jh7110-starfive-visionfive-2-v1.3b" +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SECT_SIZE_AUTO=y
Support multiple DTBs for JH7110 based boards, so they can select the correct DT at runtime.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: E Shattow lucent@gmail.com Signed-off-by: Hal Feng hal.feng@starfivetech.com --- arch/riscv/dts/jh7110-common-u-boot.dtsi | 66 +++++++++++++++++++++--- 1 file changed, 60 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi index 7953459e67..a928faf520 100644 --- a/arch/riscv/dts/jh7110-common-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -110,20 +110,74 @@ itb { fit { images { - fdt-1 { - description = "NAME"; + fdt-jh7110-milkv-mars { + description = "jh7110-milkv-mars"; load = <0x40400000>; compression = "none";
- uboot_fdt_blob: blob-ext { - filename = "u-boot.dtb"; + blob-ext { + filename = "dts/upstream/src/riscv/starfive/jh7110-milkv-mars.dtb"; + }; + }; + + fdt-jh7110-pine64-star64 { + description = "jh7110-pine64-star64"; + load = <0x40400000>; + compression = "none"; + + blob-ext { + filename = "dts/upstream/src/riscv/starfive/jh7110-pine64-star64.dtb"; + }; + }; + + fdt-jh7110-starfive-visionfive-2-v1.2a { + description = "jh7110-starfive-visionfive-2-v1.2a"; + load = <0x40400000>; + compression = "none"; + + blob-ext { + filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"; + }; + }; + + fdt-jh7110-starfive-visionfive-2-v1.3b { + description = "jh7110-starfive-visionfive-2-v1.3b"; + load = <0x40400000>; + compression = "none"; + + blob-ext { + filename = "dts/upstream/src/riscv/starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"; }; }; };
configurations { - conf-1 { - fdt = "fdt-1"; + conf-jh7110-milkv-mars { + description = "jh7110-milkv-mars"; + firmware = "opensbi"; + loadables = "uboot"; + fdt = "fdt-jh7110-milkv-mars"; + }; + + conf-jh7110-pine64-star64 { + description = "jh7110-pine64-star64"; + firmware = "opensbi"; + loadables = "uboot"; + fdt = "fdt-jh7110-pine64-star64"; + }; + + conf-jh7110-starfive-visionfive-2-v1.2a { + description = "jh7110-starfive-visionfive-2-v1.2a"; + firmware = "opensbi"; + loadables = "uboot"; + fdt = "fdt-jh7110-starfive-visionfive-2-v1.2a"; + }; + + conf-jh7110-starfive-visionfive-2-v1.3b { + description = "jh7110-starfive-visionfive-2-v1.3b"; + firmware = "opensbi"; + loadables = "uboot"; + fdt = "fdt-jh7110-starfive-visionfive-2-v1.3b"; }; }; };
The prefix "SPL_" is not needed when using CONFIG_IS_ENABLED().
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: Heinrich Schuchardt xypron.glpk@gmx.de Fixes: 5ecf9b0b8a75 ("board: starfive: add StarFive VisionFive v2 board support") Signed-off-by: Hal Feng hal.feng@starfivetech.com --- board/starfive/visionfive2/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index 38132ecccd..cf7f39d5c5 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -110,7 +110,7 @@ void board_init_f(ulong dummy) } }
-#if CONFIG_IS_ENABLED(SPL_LOAD_FIT) +#if CONFIG_IS_ENABLED(LOAD_FIT) int board_fit_config_name_match(const char *name) { /* boot using first FIT config */
Get product ID and the other information from EEPROM, use them to select the correct DTB.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Reviewed-by: Heinrich Schuchardt xypron.glpk@gmx.de Signed-off-by: Hal Feng hal.feng@starfivetech.com --- board/starfive/visionfive2/spl.c | 33 ++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index cf7f39d5c5..22afd76c6b 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -113,7 +113,36 @@ void board_init_f(ulong dummy) #if CONFIG_IS_ENABLED(LOAD_FIT) int board_fit_config_name_match(const char *name) { - /* boot using first FIT config */ - return 0; + const char *product_id; + u8 version; + + product_id = get_product_id_from_eeprom(); + + if (!strncmp(product_id, "VF7110", 6)) { + version = get_pcb_revision_from_eeprom(); + if ((version == 'b' || version == 'B') && + !strcmp(name, "jh7110-starfive-visionfive-2-v1.3b")) + return 0; + + if ((version == 'a' || version == 'A') && + !strcmp(name, "jh7110-starfive-visionfive-2-v1.2a")) + return 0; + } else if (!strncmp(product_id, "MARS", 4) && + !strcmp(name, "jh7110-milkv-mars")) { + return 0; + } else if (!strncmp(product_id, "MARC", 4)) { + if (!get_mmc_size_from_eeprom()) { + if (!strcmp(name, "jh7110-milkv-mars-cm-lite")) + return 0; + } else { + if (!strcmp(name, "jh7110-milkv-mars-cm")) + return 0; + } + } else if (!strncmp(product_id, "STAR64", 6) && + !strcmp(name, "jh7110-pine64-star64")) { + return 0; + } + + return -EINVAL; } #endif
The imply statements should be sorted in the sequence of appearance in .config.
Tested-by: Anand Moon linux.amoon@gmail.com Tested-by: E Shattow lucent@gmail.com Suggested-by: Heinrich Schuchardt xypron.glpk@gmx.de Signed-off-by: Hal Feng hal.feng@starfivetech.com --- arch/riscv/cpu/jh7110/Kconfig | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 9904a60ddd..fa47e55226 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -16,17 +16,17 @@ config STARFIVE_JH7110 select SYS_CACHE_SHIFT_6 select SPL_ZERO_MEM_BEFORE_USE select PINCTRL_STARFIVE_JH7110 + imply SMP + imply SPL_RISCV_ACLINT + imply SIFIVE_CACHE + imply SPL_SYS_MALLOC_CLEAR_ON_INIT + imply SPL_LOAD_FIT + imply SPL_CPU + imply SPL_OPENSBI + imply OF_UPSTREAM + imply SIFIVE_CCACHE imply MMC imply MMC_BROKEN_CD imply MMC_SPI - imply OF_UPSTREAM - imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) - imply SIFIVE_CACHE - imply SIFIVE_CCACHE - imply SMP imply SPI - imply SPL_CPU - imply SPL_LOAD_FIT - imply SPL_OPENSBI - imply SPL_RISCV_ACLINT - imply SPL_SYS_MALLOC_CLEAR_ON_INIT + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
participants (3)
-
E Shattow -
Hal Feng -
Jaehoon Chung