[U-Boot] [UBOOT PATCH 0/2] spi: Moved spi u-bbot headers to Kconfig
This seris of patch moved spi headers to Kconfig. These are the configs: -CONFIG_SYS_ZYNQ_SPI_WAIT -CONFIG_XILINX_SPI_IDLE_VAL -CONFIG_SYS_ZYNQ_QSPI_WAIT
Vipul Kumar (2): qspi: Added Kconfig support for CONFIG_SYS_ZYNQ_QSPI_WAIT spi: Added Kconfig support for SYS_ZYNQ_SPI_WAIT and XILINX_SPI_IDLE_VAL
drivers/spi/Kconfig | 18 ++++++++++++++++++ drivers/spi/xilinx_spi.c | 4 ---- drivers/spi/zynq_qspi.c | 3 --- drivers/spi/zynq_spi.c | 3 --- 4 files changed, 18 insertions(+), 10 deletions(-)
-- 2.7.4
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This patch added Kconfig support for CONFIG_SYS_ZYNQ_QSPI_WAIT and set it to default value 10 milliseconds.
Signed-off-by: Vipul Kumar vipulk@xilinx.com Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com --- drivers/spi/Kconfig | 6 ++++++ drivers/spi/zynq_qspi.c | 3 --- 2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 235a8c7..436e9ad 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -204,6 +204,12 @@ config ZYNQ_QSPI Zynq QSPI IP core. This IP is used to connect the flash in 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
+config SYS_ZYNQ_QSPI_WAIT + int "Define Zynq QSPI wait time in ms" + default 10 + help + Define default Zynq QSPI wait time in milliseconds. + endif # if DM_SPI
config SOFT_SPI diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 255e02f..c9241aa 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -46,9 +46,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_QSPI_FIFO_DEPTH 63 -#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT -#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ -#endif
/* zynq qspi register set */ struct zynq_qspi_regs { -- 2.7.4
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On 16.2.2018 15:14, Vipul Kumar wrote:
This patch added Kconfig support for CONFIG_SYS_ZYNQ_QSPI_WAIT and set it to default value 10 milliseconds.
Signed-off-by: Vipul Kumar vipulk@xilinx.com Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com
drivers/spi/Kconfig | 6 ++++++ drivers/spi/zynq_qspi.c | 3 --- 2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 235a8c7..436e9ad 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -204,6 +204,12 @@ config ZYNQ_QSPI Zynq QSPI IP core. This IP is used to connect the flash in 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
+config SYS_ZYNQ_QSPI_WAIT
- int "Define Zynq QSPI wait time in ms"
here I am missing depends on ZYNQ_QSPI.
M
- default 10
- help
Define default Zynq QSPI wait time in milliseconds.endif # if DM_SPI
config SOFT_SPI diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c index 255e02f..c9241aa 100644 --- a/drivers/spi/zynq_qspi.c +++ b/drivers/spi/zynq_qspi.c @@ -46,9 +46,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_QSPI_FIFO_DEPTH 63 -#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT -#define CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ -#endif
/* zynq qspi register set */ struct zynq_qspi_regs {
This patch added Kconfig support for CONFIG_SYS_ZYNQ_SPI_WAIT and CONFIG_XILINX_SPI_IDLE_VAL and set default value.
Signed-off-by: Vipul Kumar vipulk@xilinx.com Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com --- drivers/spi/Kconfig | 12 ++++++++++++ drivers/spi/xilinx_spi.c | 4 ---- drivers/spi/zynq_spi.c | 3 --- 3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 436e9ad..bcb28cf 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -210,6 +210,18 @@ config SYS_ZYNQ_QSPI_WAIT help Define default Zynq QSPI wait time in milliseconds.
+config SYS_ZYNQ_SPI_WAIT + int "Define Zynq SPI wait time in ms" + default 10 + help + Define default Zynq SPI wait time in milliseconds. + +config XILINX_SPI_IDLE_VAL + hex "Define the default SPI idle value" + default 0xFFFFFFFF + help + Set the default SPI idle value. + endif # if DM_SPI
config SOFT_SPI diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index a951a77..9781ea9 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -74,10 +74,6 @@ SPICR_SPE) #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
-#ifndef CONFIG_XILINX_SPI_IDLE_VAL -#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) -#endif - #ifndef CONFIG_SYS_XILINX_SPI_LIST #define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE } #endif diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index ed2b8cb..be8f525 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -33,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_SPI_FIFO_DEPTH 128 -#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT -#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ -#endif
/* zynq spi register set */ struct zynq_spi_regs { -- 2.7.4
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On 16.2.2018 15:14, Vipul Kumar wrote:
This patch added Kconfig support for CONFIG_SYS_ZYNQ_SPI_WAIT and CONFIG_XILINX_SPI_IDLE_VAL and set default value.
Signed-off-by: Vipul Kumar vipulk@xilinx.com Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com
drivers/spi/Kconfig | 12 ++++++++++++ drivers/spi/xilinx_spi.c | 4 ---- drivers/spi/zynq_spi.c | 3 --- 3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 436e9ad..bcb28cf 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -210,6 +210,18 @@ config SYS_ZYNQ_QSPI_WAIT help Define default Zynq QSPI wait time in milliseconds.
+config SYS_ZYNQ_SPI_WAIT
- int "Define Zynq SPI wait time in ms"
The same here - add depends on XILINX_SPI.
M
- default 10
- help
Define default Zynq SPI wait time in milliseconds.+config XILINX_SPI_IDLE_VAL
- hex "Define the default SPI idle value"
- default 0xFFFFFFFF
- help
Set the default SPI idle value.endif # if DM_SPI
config SOFT_SPI diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index a951a77..9781ea9 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -74,10 +74,6 @@ SPICR_SPE) #define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
-#ifndef CONFIG_XILINX_SPI_IDLE_VAL -#define CONFIG_XILINX_SPI_IDLE_VAL GENMASK(7, 0) -#endif
#ifndef CONFIG_SYS_XILINX_SPI_LIST #define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE } #endif diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index ed2b8cb..be8f525 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -33,9 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
#define ZYNQ_SPI_FIFO_DEPTH 128 -#ifndef CONFIG_SYS_ZYNQ_SPI_WAIT -#define CONFIG_SYS_ZYNQ_SPI_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */ -#endif
/* zynq spi register set */ struct zynq_spi_regs {
participants (2)
-
Michal Simek -
Vipul Kumar