[U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue, this is a workaround.
Signed-off-by: Zhao Qiang B45475@freescale.com --- drivers/pci/fsl_pci_init.c | 17 +++++++++++++++++ include/configs/T208xQDS.h | 1 + 2 files changed, 18 insertions(+)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 231b075..327fa7d 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -481,6 +481,23 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) #endif }
+#ifdef CONFIG_FSL_PCIE_T2080QDS_RESET + int i; + /* assert PCIe reset */ + setbits_be32(&pci->pdb_stat, 0x08000000); + (void) in_be32(&pci->pdb_stat); + udelay(1000); + /* clear PCIe reset */ + clrbits_be32(&pci->pdb_stat, 0x08000000); + asm("sync;isync"); + for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) { + pci_hose_read_config_word(hose, dev, PCI_LTSSM, + <ssm); + udelay(1000); + } + +#endif + #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 if (enabled == 0) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 395472b..851b4f9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controler 2 */ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCIE_T2080QDS_RESET #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */
Hi Zhao,
Can you please rephrase the subject. No need to mention T2080QDS twice in the subject
-----Original Message----- From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Zhao Qiang Sent: Tuesday, March 10, 2015 2:55 PM To: u-boot@lists.denx.de; Sun York-R58495 Cc: Zhao Qiang-B45475 Subject: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue, this is a workaround.
Can you please rephrase the description.
is this issue only occur with mentioned protocol or other SerDes protocol has not been tested?
Signed-off-by: Zhao Qiang B45475@freescale.com
drivers/pci/fsl_pci_init.c | 17 +++++++++++++++++ include/configs/T208xQDS.h | 1 + 2 files changed, 18 insertions(+)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 231b075..327fa7d 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -481,6 +481,23 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) #endif }
+#ifdef CONFIG_FSL_PCIE_T2080QDS_RESET
int i;/* assert PCIe reset */setbits_be32(&pci->pdb_stat, 0x08000000);(void) in_be32(&pci->pdb_stat);udelay(1000);/* clear PCIe reset */clrbits_be32(&pci->pdb_stat, 0x08000000);asm("sync;isync");for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {pci_hose_read_config_word(hose, dev, PCI_LTSSM,<ssm);udelay(1000);}+#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 if (enabled == 0) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 395472b..851b4f9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controler 2 */ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCIE_T2080QDS_RESET
As your patch is reseting PCIe independent of SerDes Protocols What about defining CONFIG_FSL_PCIE_RESET
Regards, Prabhakar
Resending as some issue in my mail-box.
Regards, Prabhakar
-----Original Message----- From: Kushwaha Prabhakar-B32579 Sent: Wednesday, March 11, 2015 10:01 AM To: 'Zhao Qiang'; u-boot@lists.denx.de; Sun York-R58495 Subject: RE: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
Hi Zhao,
Can you please rephrase the subject. No need to mention T2080QDS twice in the subject
-----Original Message----- From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Zhao Qiang Sent: Tuesday, March 10, 2015 2:55 PM To: u-boot@lists.denx.de; Sun York-R58495 Cc: Zhao Qiang-B45475 Subject: [U-Boot] [PATCH] T2080QDS/PCIe: Soft Reset PCIe on T2080QDS for down-training issue
T2080QDS PEX1/Slot#1 will down-train from x4 to x2, with SRDS_PRTCL_S1 = 0x66 and SRDS_PRTCL_S2 = 0x15. Soft reset PCIe can fix this issue, this is a workaround.
Can you please rephrase the description.
is this issue only occur with mentioned protocol or other SerDes protocol has not been tested?
Signed-off-by: Zhao Qiang B45475@freescale.com
drivers/pci/fsl_pci_init.c | 17 +++++++++++++++++ include/configs/T208xQDS.h | 1 + 2 files changed, 18 insertions(+)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 231b075..327fa7d 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -481,6 +481,23 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) #endif }
+#ifdef CONFIG_FSL_PCIE_T2080QDS_RESET
int i;/* assert PCIe reset */setbits_be32(&pci->pdb_stat, 0x08000000);(void) in_be32(&pci->pdb_stat);udelay(1000);/* clear PCIe reset */clrbits_be32(&pci->pdb_stat, 0x08000000);asm("sync;isync");for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {pci_hose_read_config_word(hose, dev, PCI_LTSSM,<ssm);udelay(1000);}+#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 if (enabled == 0) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 395472b..851b4f9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -558,6 +558,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controler 2 */ #define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_PCIE4 /* PCIE controler 4 */ +#define CONFIG_FSL_PCIE_T2080QDS_RESET
As your patch is reseting PCIe independent of SerDes Protocols What about defining CONFIG_FSL_PCIE_RESET
Regards, Prabhakar
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prabhakar＠freescale.com -
Zhao Qiang