On Sat, Feb 2, 2019 at 11:17 AM Jörg Krause joerg.krause@embedded.rocks wrote:

Hi,

On Thu, 2019-01-17 at 07:16 -0600, Adam Ford wrote:

...

The initialization of the NAND in SPL hard-coded ecc.bytes, ecc.size, and ecc.strength which may work for some NAND parts, but it not appropriate for others. With the pending patch "mxs_nand: Fix BCH read timeout error on boards requiring ECC" the driver can auto configure the ECC when these entries are blank. This patch has been tested in NAND flash with oob 64 and oob 128.

Signed-off-by: Adam Ford aford173@gmail.com

Maybe you can give me a hint where the driver actually does the auto configuration?

I've tested the patch on a custom i.MX6ULL board with a Micron NAND flash. The SPL loader is able to boot from NAND with and without this patch.

I am traveling right now, so I don;t have my editor or source code, but I can tell you that the patch found in http://patchwork.ozlabs.org/patch/1020160/ sets up the ECC, and if these values are not set they will get set. I won't be back to the office until a week from Monday.

The reason I found I needed this patch was because I have boards with different flash parts that used different ECC values. One my board boards didn't need the patch because the ECC matched the values hard-coded here, but my other board would get ECC errors during SPL because these values didn't match what U-Boot used when it wrote to flash.

If your board works with and without the patch, I am guessing the ECC values generated by the above mentioned patch probably set them to the same values that were hard coded before.

adam

Tested-by: Jörg Krause joerg.krause@embedded.rocks

...

diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 2d84bfffe2..95fa452cef 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1191,9 +1191,6 @@ int mxs_nand_init_spl(struct nand_chip *nand) nand->ecc.read_page = mxs_nand_ecc_read_page;

  nand->ecc.mode          = NAND_ECC_HW;

• nand->ecc.bytes         = 9;
  

• nand->ecc.size          = 512;
  

• nand->ecc.strength      = 8;
  
  return 0;
  

}

On Mon, Feb 4, 2019 at 12:20 PM Tim Harvey tharvey@gateworks.com wrote:

On Thu, Jan 17, 2019 at 5:17 AM Adam Ford aford173@gmail.com wrote:

...

The initialization of the NAND in SPL hard-coded ecc.bytes, ecc.size, and ecc.strength which may work for some NAND parts, but it not appropriate for others. With the pending patch "mxs_nand: Fix BCH read timeout error on boards requiring ECC" the driver can auto configure the ECC when these entries are blank. This patch has been tested in NAND flash with oob 64 and oob 128.

Signed-off-by: Adam Ford aford173@gmail.com

diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 2d84bfffe2..95fa452cef 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1191,9 +1191,6 @@ int mxs_nand_init_spl(struct nand_chip *nand) nand->ecc.read_page = mxs_nand_ecc_read_page;

    nand->ecc.mode          = NAND_ECC_HW;

•   nand->ecc.bytes         = 9;
  

•   nand->ecc.size          = 512;
  

•   nand->ecc.strength      = 8;
  
    return 0;
  

}

Thanks Adam,

This resolves failed booting on Gateworks Ventana IMX6 with NAND SPL for Micron MT29F16G08AD 16Gbit (oob=224) and Cypress S34ML16G202BH 16Gbit (oob=128).

This fixes the regressions occuring with 5346c31e305a37d39f535cc0d5ae87d8b7e81230: mtd: nand: mxs_nand: use self init

Acked-by: Tim Harvey tharvey@gateworks.com

Tested-by: Tim Harvey tharvey@gateworks.com for GW5104 with Micron MT29F16G08AD 16Gbit (oob=224) and Cypress S34ML16G202BH 16Gbit (oob=128)

Scott / Stefano,

Any chance this can get reviewed and/or applied for the next release? We've got a few people who have their respective tested-by comments.

adam

Tim