Föll wrote:

Hi,

A small question:

Why have you switched from AMCC 440EP to the Freescale 8349E ?

Hi Tobias,

My custom board design is; 1GHz digitizer, multiple Altera Stratix II FPGAs, and an MPC8349E/EA processor. The processor is the PCI interface, and the FPGAs are on the local bus (running at up to 133MHz). The boards digitize data, and then use front panel cables to transfer digitized data to other boards containing FPGAs. The FPGAs cross-correlate and average the data. The averaged data is transferred from about 20 boards per chassis to a system slot processor.

The system slot processor driver for the previous generation boards used character drivers that created /dev nodes that were read from using the user-space select() and read() calls. The driver implementation used the doorbell registers on a PLX PCI9054 PCI Master/Target chipset to generate receiver-ready and transmitter-empty interrupt handshakes. This protocol inherently implements flow-control. Think of this as a serial port analogy, with the serial port FIFO being a block of memory that is transferred using DMA. Its very efficient, with the driver being able to hit 120MB/s during DMA.

The new boards will have 10x the density due to the larger FPGAs, so will require 10x processor. Since this application is I/O bound, I started looking for PowerPC processors that had FPUs and three independent buses; PCI, memory, and local-bus. Most of the PowerQUICC processors only had two buses, whereas the 440EP had three. Also if you look in the configuration space headers for most PCI capable PowerQUICCs, you will find that they cannot generate a PCI interrupt (the interrupt register is hard-wired to 0). These devices are intended as PCI hosts, not targets.

However ... if you look in the 440EP data sheet you will find that to generate a PCI interrupt it has only 1 bit that can be toggled, and if you look for a method that the system slot CPU can use to interrupt the 440EP core ... well, you'll just keep looking and looking ... yep, there is no way for the system slot processor to interrupt the 440EP core. You could add some external logic to the local bus, and memory map that to PCI, and then toggle a bit in that hardware to generate an external interrupt on the device ... but thats a hack.

I purchased the Yosemite board to evaluate the 440EP, and my evaluation indicated that it wasn't suitable - only a ~$800 oversight, and a few evenings figuring out some of the cool features on my logic analyzer, so no loss really. To see if there was a more suitable processor, I sent a request to this mailing group for suggestions. Wolfgang Denx suggested I look at the MPC8349E, and he was right, it met my requirements. So I got a Freescale MPC8349E-MDS-PB PCI form-factor development board, and I've been happy with it, so I'm designing that into the new boards.

I'll happily share all my development work, so ask away. I'm in schematic capture at the moment, and once thats close to completion I'll post a link.

Cheers Dave