[U-Boot] [PATCH 0/6] rockchip: rk3399: GMAC support for the RK3399 SoC
The RK3399 includes the Designware Gigabit Ethernet controller IP and requires similar configuration as the RK3288. However, the configuration register offsets (within GRF) and bit offsets (within the registers) differ.
This changeset refactors the gmac_rockchip.c driver to handle both RK3288 and RK3399 devices. It further adds the necessary pinctrl and clock support for GMAC capability on the RK3399.
Tested with a RK3399-Q7 (on-module KSZ9031 PHY) at 100MBit and 1GBit.
Philipp Tomsich (6): rockchip: pinctrl: rk3399: add GMAC (RGMII only) support rockchip: clk: rk3399: fix warnings for unused variables in SPL/non-SPL rockchip: clk: rk3399: add clocking support for Ethernet net: gmac_rockchip: Add support for the RK3399 GMAC dts: rk3399: add gmac for the rk3399 dts: rk3399-puma: add gmac for the RK3399-Q7
arch/arm/dts/rk3399-puma.dts | 30 +++++ arch/arm/dts/rk3399.dtsi | 55 ++++++++++ arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 68 ++++++------ arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 84 +++++++++++++- arch/arm/include/asm/arch-rockchip/periph.h | 1 + drivers/clk/rockchip/clk_rk3399.c | 9 ++ drivers/net/gmac_rockchip.c | 140 +++++++++++++++++++----- drivers/pinctrl/rockchip/pinctrl_rk3399.c | 42 +++++++ 8 files changed, 367 insertions(+), 62 deletions(-)
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII signalling mode: * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID * adds the required defines (in the GRF support) for configuring the GPIOC pins for RGMII * configures the RGMII pins (in GPIOC) when requested via pinctrl
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 37 ++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/periph.h | 1 + drivers/pinctrl/rockchip/pinctrl_rk3399.c | 42 +++++++++++++++++++++++++ 3 files changed, 80 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index 4701cfb..8e20533 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -342,23 +342,60 @@ enum { GRF_UART0BT_SOUT = 1,
/* GRF_GPIO3A_IOMUX */ + GRF_GPIO3A0_SEL_SHIFT = 0, + GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT, + GRF_MAC_TXD2 = 1, + GRF_GPIO3A1_SEL_SHIFT = 2, + GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT, + GRF_MAC_TXD3 = 1, + GRF_GPIO3A2_SEL_SHIFT = 4, + GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT, + GRF_MAC_RXD2 = 1, + GRF_GPIO3A3_SEL_SHIFT = 6, + GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT, + GRF_MAC_RXD3 = 1, GRF_GPIO3A4_SEL_SHIFT = 8, GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, + GRF_MAC_TXD0 = 1, GRF_SPI0NORCODEC_RXD = 2, GRF_GPIO3A5_SEL_SHIFT = 10, GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, + GRF_MAC_TXD1 = 1, GRF_SPI0NORCODEC_TXD = 2, GRF_GPIO3A6_SEL_SHIFT = 12, GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, + GRF_MAC_RXD0 = 1, GRF_SPI0NORCODEC_CLK = 2, GRF_GPIO3A7_SEL_SHIFT = 14, GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, + GRF_MAC_RXD1 = 1, GRF_SPI0NORCODEC_CSN0 = 2,
/* GRF_GPIO3B_IOMUX */ GRF_GPIO3B0_SEL_SHIFT = 0, GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, + GRF_MAC_MDC = 1, GRF_SPI0NORCODEC_CSN1 = 2, + GRF_GPIO3B1_SEL_SHIFT = 2, + GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT, + GRF_MAC_RXDV = 1, + GRF_GPIO3B3_SEL_SHIFT = 6, + GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT, + GRF_MAC_CLK = 1, + GRF_GPIO3B4_SEL_SHIFT = 8, + GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT, + GRF_MAC_TXEN = 1, + GRF_GPIO3B5_SEL_SHIFT = 10, + GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT, + GRF_MAC_MDIO = 1, + GRF_GPIO3B6_SEL_SHIFT = 12, + GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT, + GRF_MAC_RXCLK = 1, + + /* GRF_GPIO3C_IOMUX */ + GRF_GPIO3C1_SEL_SHIFT = 2, + GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT, + GRF_MAC_TXCLK = 1,
/* GRF_GPIO4B_IOMUX */ GRF_GPIO4B0_SEL_SHIFT = 0, diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h index fa6069b..239a274 100644 --- a/arch/arm/include/asm/arch-rockchip/periph.h +++ b/arch/arm/include/asm/arch-rockchip/periph.h @@ -38,6 +38,7 @@ enum periph_id { PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_HDMI, + PERIPH_ID_GMAC,
PERIPH_ID_COUNT,
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index a74793a..507bec4 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -202,6 +202,39 @@ static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id) } }
+#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id) +{ + rk_clrsetreg(&grf->gpio3a_iomux, + GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK | + GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK | + GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK | + GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK, + GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT | + GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT | + GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT | + GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT | + GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT | + GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT | + GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT | + GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT); + rk_clrsetreg(&grf->gpio3b_iomux, + GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK | + GRF_GPIO3B3_SEL_MASK | + GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK | + GRF_GPIO3B6_SEL_MASK, + GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT | + GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT | + GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT | + GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT | + GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT | + GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT); + rk_clrsetreg(&grf->gpio3c_iomux, + GRF_GPIO3C1_SEL_MASK, + GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT); +} +#endif + static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); @@ -243,6 +276,11 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk3399_sdmmc_config(priv->grf, func); break; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case PERIPH_ID_GMAC: + pinctrl_rk3399_gmac_config(priv->grf, func); + break; +#endif default: return -EINVAL; } @@ -283,6 +321,10 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_I2C5; case 65: return PERIPH_ID_SDMMC1; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case 12: + return PERIPH_ID_GMAC; +#endif } #endif return -ENOENT;
On 24 March 2017 at 12:24, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII signalling mode:
- adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
- adds the required defines (in the GRF support) for configuring the GPIOC pins for RGMII
- configures the RGMII pins (in GPIOC) when requested via pinctrl
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 37 ++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/periph.h | 1 + drivers/pinctrl/rockchip/pinctrl_rk3399.c | 42 +++++++++++++++++++++++++ 3 files changed, 80 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 25 March 2017 at 21:47, Simon Glass sjg@chromium.org wrote:
On 24 March 2017 at 12:24, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII signalling mode:
- adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID
- adds the required defines (in the GRF support) for configuring the GPIOC pins for RGMII
- configures the RGMII pins (in GPIOC) when requested via pinctrl
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 37 ++++++++++++++++++++++ arch/arm/include/asm/arch-rockchip/periph.h | 1 + drivers/pinctrl/rockchip/pinctrl_rk3399.c | 42 +++++++++++++++++++++++++ 3 files changed, 80 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
Due to differences in the code paths for SPL and non-SPL, some static constant structures remain unused in each build variant. This raises warnings with recent GCC versions (we currently use GCC-6.3).
The warnings addressed in this commit (by matching #if conditions for the variable definition with their uses) are:
* for the SPL build: drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); ^~~~~~~~~~~~~ drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); ^~~~~~~~~~~~~ * for the non-SPL build: drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); ^~~~~~~~~~~~~
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
drivers/clk/rockchip/clk_rk3399.c | 5 +++++ 1 file changed, 5 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 922ce7e..453c6dd 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -47,9 +47,12 @@ struct pll_div { .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
+#if defined(CONFIG_SPL_BUILD) static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); +#else static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); +#endif
static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); @@ -1009,7 +1012,9 @@ static void pmuclk_init(struct rk3399_pmucru *pmucru)
static int rk3399_pmuclk_probe(struct udevice *dev) { +#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); +#endif
#if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
On 24 March 2017 at 12:24, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
Due to differences in the code paths for SPL and non-SPL, some static constant structures remain unused in each build variant. This raises warnings with recent GCC versions (we currently use GCC-6.3).
The warnings addressed in this commit (by matching #if conditions for the variable definition with their uses) are:
- for the SPL build: drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); ^~~~~~~~~~~~~ drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); ^~~~~~~~~~~~~
- for the non-SPL build: drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); ^~~~~~~~~~~~~
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
drivers/clk/rockchip/clk_rk3399.c | 5 +++++ 1 file changed, 5 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 25 March 2017 at 21:48, Simon Glass sjg@chromium.org wrote:
On 24 March 2017 at 12:24, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
Due to differences in the code paths for SPL and non-SPL, some static constant structures remain unused in each build variant. This raises warnings with recent GCC versions (we currently use GCC-6.3).
The warnings addressed in this commit (by matching #if conditions for the variable definition with their uses) are:
- for the SPL build: drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); ^~~~~~~~~~~~~ drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); ^~~~~~~~~~~~~
- for the non-SPL build: drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); ^~~~~~~~~~~~~
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
drivers/clk/rockchip/clk_rk3399.c | 5 +++++ 1 file changed, 5 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock is ungated through a call to clk_set_rate(...). Even though nothing needs to be done on the RK3399 (the clock gates are open and the clock is external), we need to implement enough support to at least return success to enable driver probing.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
drivers/clk/rockchip/clk_rk3399.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 453c6dd..1ac4ff4 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -802,6 +802,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_EMMC: ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); break; + case SCLK_MAC: + /* nothing to do, as this is an external clock */ + ret = rate; + break; case SCLK_I2C1: case SCLK_I2C2: case SCLK_I2C3:
On 24 March 2017 at 12:24, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock is ungated through a call to clk_set_rate(...). Even though nothing needs to be done on the RK3399 (the clock gates are open and the clock is external), we need to implement enough support to at least return success to enable driver probing.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
drivers/clk/rockchip/clk_rk3399.c | 4 ++++ 1 file changed, 4 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 25 March 2017 at 21:48, Simon Glass sjg@chromium.org wrote:
On 24 March 2017 at 12:24, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock is ungated through a call to clk_set_rate(...). Even though nothing needs to be done on the RK3399 (the clock gates are open and the clock is external), we need to implement enough support to at least return success to enable driver probing.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
drivers/clk/rockchip/clk_rk3399.c | 4 ++++ 1 file changed, 4 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it is a Designware GMAC core and requires similar configuration as the RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit). The key difference is that the register offsets (within the GRF block) and bit-offsets (within those registers) used to hold the configuration differ between the various RK32/33 CPUs.
This change refactors the gmac_rockchip.c driver to use a function table (selected via driver_data) to factor our these differences. Each function's implementation then matches the underlying processor.
Some collateral changes are needed in the definitions describing the bits and offsets in the GRF are needed to prefix each set of symbolic constants with the SoC name to avoid name clashes... and in doing so, the shifts for masks and constants have been moved into the header files for readability (and to make it easier to stay below 80 chars).
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
---
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 68 ++++++------ arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 47 +++++++- drivers/net/gmac_rockchip.c | 140 +++++++++++++++++++----- 3 files changed, 193 insertions(+), 62 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index aaffd19..1a7c819 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -720,20 +720,20 @@ enum {
/* GRF_SOC_CON1 */ enum { - RMII_MODE_SHIFT = 0xe, - RMII_MODE_MASK = 1, - RMII_MODE = 1, + RK3288_RMII_MODE_SHIFT = 14, + RK3288_RMII_MODE_MASK = (1 << RK3288_RMII_MODE_SHIFT), + RK3288_RMII_MODE = (1 << RK3288_RMII_MODE_SHIFT),
- GMAC_CLK_SEL_SHIFT = 0xc, - GMAC_CLK_SEL_MASK = 3, - GMAC_CLK_SEL_125M = 0, - GMAC_CLK_SEL_25M = 0x3, - GMAC_CLK_SEL_2_5M = 0x2, + RK3288_GMAC_CLK_SEL_SHIFT = 12, + RK3288_GMAC_CLK_SEL_MASK = (3 << RK3288_GMAC_CLK_SEL_SHIFT), + RK3288_GMAC_CLK_SEL_125M = (0 << RK3288_GMAC_CLK_SEL_SHIFT), + RK3288_GMAC_CLK_SEL_25M = (3 << RK3288_GMAC_CLK_SEL_SHIFT), + RK3288_GMAC_CLK_SEL_2_5M = (2 << RK3288_GMAC_CLK_SEL_SHIFT),
- RMII_CLK_SEL_SHIFT = 0xb, - RMII_CLK_SEL_MASK = 1, - RMII_CLK_SEL_2_5M = 0, - RMII_CLK_SEL_25M, + RK3288_RMII_CLK_SEL_SHIFT = 11, + RK3288_RMII_CLK_SEL_MASK = (1 << RK3288_RMII_CLK_SEL_SHIFT), + RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT), + RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT),
GMAC_SPEED_SHIFT = 0xa, GMAC_SPEED_MASK = 1, @@ -743,10 +743,10 @@ enum { GMAC_FLOWCTRL_SHIFT = 0x9, GMAC_FLOWCTRL_MASK = 1,
- GMAC_PHY_INTF_SEL_SHIFT = 0x6, - GMAC_PHY_INTF_SEL_MASK = 0x7, - GMAC_PHY_INTF_SEL_RGMII = 0x1, - GMAC_PHY_INTF_SEL_RMII = 0x4, + RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6, + RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), + RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), + RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT),
HOST_REMAP_SHIFT = 0x5, HOST_REMAP_MASK = 1 @@ -801,21 +801,27 @@ enum {
/* GRF_SOC_CON3 */ enum { - RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, - RXCLK_DLY_ENA_GMAC_MASK = 1, - RXCLK_DLY_ENA_GMAC_DISABLE = 0, - RXCLK_DLY_ENA_GMAC_ENABLE, - - TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, - TXCLK_DLY_ENA_GMAC_MASK = 1, - TXCLK_DLY_ENA_GMAC_DISABLE = 0, - TXCLK_DLY_ENA_GMAC_ENABLE, - - CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, - CLK_RX_DL_CFG_GMAC_MASK = 0x7f, - - CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, - CLK_TX_DL_CFG_GMAC_MASK = 0x7f, + RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, + RK3288_RXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3288_RXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + + RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, + RK3288_TXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), + RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + + RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, + RK3288_CLK_RX_DL_CFG_GMAC_MASK = + (0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT), + + RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, + RK3288_CLK_TX_DL_CFG_GMAC_MASK = + (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT), };
#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index 8e20533..c424753 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -144,7 +144,9 @@ struct rk3399_grf_regs { }; u32 gpio4d_iomux; u32 reserved21[4]; - u32 gpio2_p[3][4]; + u32 gpio2_p[4]; + u32 gpio3_p[4]; + u32 gpio4_p[4]; u32 reserved22[4]; u32 gpio2_sr[3][4]; u32 reserved23[4]; @@ -215,7 +217,9 @@ struct rk3399_pmugrf_regs { }; u32 gpio1d_iomux; u32 reserved1[8]; - u32 gpio0_p[2][4]; + u32 gpio0_p[2]; + u32 reserved2[2]; + u32 gpio1_p[4]; u32 reserved3[8]; u32 gpio0a_e; u32 reserved4; @@ -481,4 +485,43 @@ enum {
};
+/* GRF_SOC_CON5 */ +enum { + RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9, + RK3399_GMAC_PHY_INTF_SEL_MASK = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), + RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), + RK3399_GMAC_PHY_INTF_SEL_RMII = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), + + RK3399_GMAC_CLK_SEL_SHIFT = 4, + RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT), + RK3399_GMAC_CLK_SEL_125M = (0 << RK3399_GMAC_CLK_SEL_SHIFT), + RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT), + RK3399_GMAC_CLK_SEL_2_5M = (2 << RK3399_GMAC_CLK_SEL_SHIFT), +}; + +/* GRF_SOC_CON6 */ +enum { + RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15, + RK3399_RXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT), + RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3399_RXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT), + + RK3399_TXCLK_DLY_ENA_GMAC_SHIFT = 7, + RK3399_TXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT), + RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3399_TXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT), + + RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8, + RK3399_CLK_RX_DL_CFG_GMAC_MASK = + (0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT), + + RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0, + RK3399_CLK_TX_DL_CFG_GMAC_MASK = + (0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT), +}; + #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */ diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index e9b202a..5e2ca76 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -14,7 +14,9 @@ #include <asm/io.h> #include <asm/arch/periph.h> #include <asm/arch/clock.h> +#include <asm/arch/hardware.h> #include <asm/arch/grf_rk3288.h> +#include <asm/arch/grf_rk3399.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> #include "designware.h" @@ -32,32 +34,45 @@ struct gmac_rockchip_platdata { int rx_delay; };
+struct rk_gmac_ops { + int (*fix_mac_speed)(struct dw_eth_dev *priv); + void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); +}; + + static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + + /* Check the new naming-style first... */ + pdata->tx_delay = fdtdec_get_int(blob, node, "tx_delay", -ENOENT); + pdata->rx_delay = fdtdec_get_int(blob, node, "rx_delay", -ENOENT);
- pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "tx-delay", 0x30); - pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "rx-delay", 0x10); + /* ... and fall back to the old naming style or default, if necessary */ + if (pdata->tx_delay == -ENOENT) + pdata->tx_delay = fdtdec_get_int(blob, node, "tx-delay", 0x30); + if (pdata->rx_delay == -ENOENT) + pdata->rx_delay = fdtdec_get_int(blob, node, "rx-delay", 0x10);
return designware_eth_ofdata_to_platdata(dev); }
-static int gmac_rockchip_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) { struct rk3288_grf *grf; int clk;
switch (priv->phydev->speed) { case 10: - clk = GMAC_CLK_SEL_2_5M; + clk = RK3288_GMAC_CLK_SEL_2_5M; break; case 100: - clk = GMAC_CLK_SEL_25M; + clk = RK3288_GMAC_CLK_SEL_25M; break; case 1000: - clk = GMAC_CLK_SEL_125M; + clk = RK3288_GMAC_CLK_SEL_125M; break; default: debug("Unknown phy speed: %d\n", priv->phydev->speed); @@ -65,17 +80,83 @@ static int gmac_rockchip_fix_mac_speed(struct dw_eth_dev *priv) }
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - rk_clrsetreg(&grf->soc_con1, - GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT, - clk << GMAC_CLK_SEL_SHIFT); + rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); + + return 0; +} + +static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk3399_grf_regs *grf; + int clk; + + switch (priv->phydev->speed) { + case 10: + clk = RK3399_GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = RK3399_GMAC_CLK_SEL_25M; + break; + case 1000: + clk = RK3399_GMAC_CLK_SEL_125M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk);
return 0; }
+static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk3288_grf *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con1, + RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, + RK3288_GMAC_PHY_INTF_SEL_RGMII); + + rk_clrsetreg(&grf->soc_con3, + RK3288_RXCLK_DLY_ENA_GMAC_MASK | + RK3288_TXCLK_DLY_ENA_GMAC_MASK | + RK3288_CLK_RX_DL_CFG_GMAC_MASK | + RK3288_CLK_TX_DL_CFG_GMAC_MASK, + RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | + RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | + pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); +} + +static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk3399_grf_regs *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + rk_clrsetreg(&grf->soc_con5, + RK3399_GMAC_PHY_INTF_SEL_MASK, + RK3399_GMAC_PHY_INTF_SEL_RGMII); + + rk_clrsetreg(&grf->soc_con6, + RK3399_RXCLK_DLY_ENA_GMAC_MASK | + RK3399_TXCLK_DLY_ENA_GMAC_MASK | + RK3399_CLK_RX_DL_CFG_GMAC_MASK | + RK3399_CLK_TX_DL_CFG_GMAC_MASK, + RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | + RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | + pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); +} + static int gmac_rockchip_probe(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); - struct rk3288_grf *grf; + struct rk_gmac_ops *ops = + (struct rk_gmac_ops *)dev_get_driver_data(dev); struct clk clk; int ret;
@@ -89,21 +170,7 @@ static int gmac_rockchip_probe(struct udevice *dev) return ret;
/* Set to RGMII mode */ - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - rk_clrsetreg(&grf->soc_con1, - RMII_MODE_MASK << RMII_MODE_SHIFT | - GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT, - GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT); - - rk_clrsetreg(&grf->soc_con3, - RXCLK_DLY_ENA_GMAC_MASK << RXCLK_DLY_ENA_GMAC_SHIFT | - TXCLK_DLY_ENA_GMAC_MASK << TXCLK_DLY_ENA_GMAC_SHIFT | - CLK_RX_DL_CFG_GMAC_MASK << CLK_RX_DL_CFG_GMAC_SHIFT | - CLK_TX_DL_CFG_GMAC_MASK << CLK_TX_DL_CFG_GMAC_SHIFT, - RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT | - TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT | - pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT | - pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT); + ops->set_to_rgmii(pdata);
return designware_eth_probe(dev); } @@ -112,12 +179,14 @@ static int gmac_rockchip_eth_start(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct dw_eth_dev *priv = dev_get_priv(dev); + struct rk_gmac_ops *ops = + (struct rk_gmac_ops *)dev_get_driver_data(dev); int ret;
ret = designware_eth_init(priv, pdata->enetaddr); if (ret) return ret; - ret = gmac_rockchip_fix_mac_speed(priv); + ret = ops->fix_mac_speed(priv); if (ret) return ret; ret = designware_eth_enable(priv); @@ -136,8 +205,21 @@ const struct eth_ops gmac_rockchip_eth_ops = { .write_hwaddr = designware_eth_write_hwaddr, };
+const struct rk_gmac_ops rk3288_gmac_ops = { + .fix_mac_speed = rk3288_gmac_fix_mac_speed, + .set_to_rgmii = rk3288_gmac_set_to_rgmii, +}; + +const struct rk_gmac_ops rk3399_gmac_ops = { + .fix_mac_speed = rk3399_gmac_fix_mac_speed, + .set_to_rgmii = rk3399_gmac_set_to_rgmii, +}; + static const struct udevice_id rockchip_gmac_ids[] = { - { .compatible = "rockchip,rk3288-gmac" }, + { .compatible = "rockchip,rk3288-gmac", + .data = (ulong)&rk3288_gmac_ops }, + { .compatible = "rockchip,rk3399-gmac", + .data = (ulong)&rk3399_gmac_ops }, { } };
On Fri, Mar 24, 2017 at 2:24 PM, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it is a Designware GMAC core and requires similar configuration as the RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit). The key difference is that the register offsets (within the GRF block) and bit-offsets (within those registers) used to hold the configuration differ between the various RK32/33 CPUs.
This change refactors the gmac_rockchip.c driver to use a function table (selected via driver_data) to factor our these differences. Each
Typo: "factor out".
function's implementation then matches the underlying processor.
Some collateral changes are needed in the definitions describing the bits and offsets in the GRF are needed to prefix each set of symbolic constants with the SoC name to avoid name clashes... and in doing so, the shifts for masks and constants have been moved into the header files for readability (and to make it easier to stay below 80 chars).
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
On 25 March 2017 at 13:09, Joe Hershberger joe.hershberger@gmail.com wrote:
On Fri, Mar 24, 2017 at 2:24 PM, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it is a Designware GMAC core and requires similar configuration as the RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit). The key difference is that the register offsets (within the GRF block) and bit-offsets (within those registers) used to hold the configuration differ between the various RK32/33 CPUs.
This change refactors the gmac_rockchip.c driver to use a function table (selected via driver_data) to factor our these differences. Each
Typo: "factor out".
function's implementation then matches the underlying processor.
Some collateral changes are needed in the definitions describing the bits and offsets in the GRF are needed to prefix each set of symbolic constants with the SoC name to avoid name clashes... and in doing so, the shifts for masks and constants have been moved into the header files for readability (and to make it easier to stay below 80 chars).
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
Acked-by: Simon Glass sjg@chromium.org
I can fix the typo when applying if there are no other comments.
On Sat, Mar 25, 2017 at 11:48 PM, Simon Glass sjg@chromium.org wrote:
On 25 March 2017 at 13:09, Joe Hershberger joe.hershberger@gmail.com wrote:
On Fri, Mar 24, 2017 at 2:24 PM, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it is a Designware GMAC core and requires similar configuration as the RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit). The key difference is that the register offsets (within the GRF block) and bit-offsets (within those registers) used to hold the configuration differ between the various RK32/33 CPUs.
This change refactors the gmac_rockchip.c driver to use a function table (selected via driver_data) to factor our these differences. Each
Typo: "factor out".
function's implementation then matches the underlying processor.
Some collateral changes are needed in the definitions describing the bits and offsets in the GRF are needed to prefix each set of symbolic constants with the SoC name to avoid name clashes... and in doing so, the shifts for masks and constants have been moved into the header files for readability (and to make it easier to stay below 80 chars).
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
Acked-by: Simon Glass sjg@chromium.org
I can fix the typo when applying if there are no other comments.
Sounds good - go for it.
-Joe
On 26 March 2017 at 07:52, Joe Hershberger joe.hershberger@gmail.com wrote:
On Sat, Mar 25, 2017 at 11:48 PM, Simon Glass sjg@chromium.org wrote:
On 25 March 2017 at 13:09, Joe Hershberger joe.hershberger@gmail.com wrote:
On Fri, Mar 24, 2017 at 2:24 PM, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
The GMAC in the RK3399 is very similar to the RK3288 variant (i.e. it is a Designware GMAC core and requires similar configuration as the RK3288 to switch it to RGMII and set up the TX/RX delays for Gigabit). The key difference is that the register offsets (within the GRF block) and bit-offsets (within those registers) used to hold the configuration differ between the various RK32/33 CPUs.
This change refactors the gmac_rockchip.c driver to use a function table (selected via driver_data) to factor our these differences. Each
Typo: "factor out".
function's implementation then matches the underlying processor.
Some collateral changes are needed in the definitions describing the bits and offsets in the GRF are needed to prefix each set of symbolic constants with the SoC name to avoid name clashes... and in doing so, the shifts for masks and constants have been moved into the header files for readability (and to make it easier to stay below 80 chars).
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
Acked-by: Joe Hershberger joe.hershberger@ni.com
Acked-by: Simon Glass sjg@chromium.org
I can fix the typo when applying if there are no other comments.
Sounds good - go for it.
-Joe
Fixed, and:
Applied to u-boot-rockchip, thanks!
This change adds the gmac node (i.e. the GMAC Ethernet controller) as defined in the Linux DTS.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
arch/arm/dts/rk3399.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 456fdb6..754d34a 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -600,6 +600,25 @@ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; };
+ gmac: eth@fe300000 { + compatible = "rockchip,rk3399-gmac"; + reg = <0x0 0xfe300000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, + <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + resets = <&cru SRST_A_GMAC>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + spdif: spdif@ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; @@ -865,6 +884,42 @@ }; };
+ gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = + /* mac_txclk */ + <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_rxclk */ + <3 14 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdio */ + <3 13 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_clk */ + <3 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxdv */ + <3 9 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ + <3 8 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd1 */ + <3 7 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd0 */ + <3 6 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_txd0 */ + <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_rxd3 */ + <3 3 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd2 */ + <3 2 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd3 */ + <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_txd2 */ + <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; + }; + }; + sdmmc { sdmmc_bus1: sdmmc-bus1 { rockchip,pins =
On 24 March 2017 at 12:24, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
This change adds the gmac node (i.e. the GMAC Ethernet controller) as defined in the Linux DTS.
It's useful to mention which version/commit of Linux you got it from.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3399.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
On 25 March 2017 at 21:48, Simon Glass sjg@chromium.org wrote:
On 24 March 2017 at 12:24, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
This change adds the gmac node (i.e. the GMAC Ethernet controller) as defined in the Linux DTS.
It's useful to mention which version/commit of Linux you got it from.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3399.dtsi | 55 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
This change enables the Gigabit Ethernet support on the RK3399-Q7.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
arch/arm/dts/rk3399-puma.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts index 31f9c3d..01cb3fa 100644 --- a/arch/arm/dts/rk3399-puma.dts +++ b/arch/arm/dts/rk3399-puma.dts @@ -50,6 +50,20 @@ regulator-name = "vcc5v0_host"; gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; };
&emmc_phy { @@ -122,3 +136,19 @@ }; }; }; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x10>; + rx_delay = <0x10>; + status = "okay"; +};
Hi Philipp,
On 24 March 2017 at 12:24, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
This change enables the Gigabit Ethernet support on the RK3399-Q7.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3399-puma.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
But I don't see this board in mainline. What tree are you basing this patch on?
- Simon
Simon,
On 26 Mar 2017, at 05:48, Simon Glass sjg@chromium.org wrote:
Hi Philipp,
On 24 March 2017 at 12:24, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
This change enables the Gigabit Ethernet support on the RK3399-Q7.
X-AffectedPlatforms: RK3399-Q7 Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3399-puma.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)
Acked-by: Simon Glass sjg@chromium.org
But I don't see this board in mainline. What tree are you basing this patch on?
This is still our prerelease development tree (I can publish via git.theobroma-systems.com http://git.theobroma-systems.com/, if that makes your and everyone’s life easier) and I only included this one to provide context for the underlying change-set.
I’ll send the patches for device-tree and defconfig in one of the next patch submissions, but have been holding back as we depend on Andre’s FIT image support.
Regards, Philipp.
participants (4)
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Dr. Philipp Tomsich -
Joe Hershberger -
Philipp Tomsich
-
Simon Glass