[U-Boot] [PATCH 0/5] peach_pi: Add support for FIMD and DP
Add support for the eDP panel supported on peach_pi.
Sjoerd Simons(1): [PATCH 1/5] Exynos5800: The Peach-Pi board does not have a Parade video bridge
Ajay Kumar (4): [PATCH 2/5] arm: exynos: add display clocks for Exynos5800 [PATCH 3/5] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels [PATCH 4/5] exynos5420: Add LCD and LED powerup settings for peach-pi [PATCH 5/5] peach_pi: dts: Add lcd poweron delay
arch/arm/cpu/armv7/exynos/clock.c | 63 +++++++++++++++++++++++- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 4 +- arch/arm/dts/exynos5800-peach-pi.dts | 6 +-- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ board/samsung/smdk5420/smdk5420.c | 32 +++++++----- 5 files changed, 88 insertions(+), 20 deletions(-)
From: Sjoerd Simons sjoerd.simons@collabora.co.uk
Unlike the Peach-Pit board, there is no parade edp to lvds bridge on the Pi. So drop it from device-tree.
Signed-off-by: Sjoerd Simons sjoerd.simons@collabora.co.uk Acked-by: Simon Glass sjg@chromium.org Tested-by: Simon Glass sjg@chromium.org --- arch/arm/dts/exynos5800-peach-pi.dts | 5 ----- 1 file changed, 5 deletions(-)
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 8aedf8e..2f9d2db 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -63,11 +63,6 @@ reg = <0x20>; compatible = "maxim,max98090-codec"; }; - - edp-lvds-bridge@48 { - compatible = "parade,ps8625"; - reg = <0x48>; - }; };
sound@3830000 {
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- arch/arm/cpu/armv7/exynos/clock.c | 63 +++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ 2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 8fab135..1a34ad6 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1066,6 +1066,36 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; }
+static unsigned long exynos5800_get_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned long sclk; + unsigned sel; + unsigned ratio; + + sel = (readl(&clk->src_disp10) >> 4) & 7; + + /* + * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into + * PLLs. The first element is a placeholder to bypass the + * default settig. + */ + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, + IPLL, EPLL, RPLL}; + if (sel) + sclk = get_pll_clk(reg_map[sel]); + else + sclk = 24000000; + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + ratio = readl(&clk->div_disp10) & 0xf; + + return sclk / (ratio + 1); +} + void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); }
+void exynos5800_set_lcd_clk(void) +{ + struct exynos5420_clock *clk = + (struct exynos5420_clock *)samsung_get_base_clock(); + unsigned int cfg; + + /* + * Use RPLL for pixel clock + * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] + * ================== + * 111: SCLK_RPLL + */ + cfg = readl(&clk->src_disp10) | (7 << 4); + writel(cfg, &clk->src_disp10); + + /* + * CLK_DIV_DISP10 + * FIMD1_RATIO [3:0] + */ + cfg = readl(&clk->div_disp10); + cfg &= ~(0xf << 0); + cfg |= (0 << 0); + writel(cfg, &clk->div_disp10); +} + void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1669,8 +1724,10 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else { - if (proid_is_exynos5420() || proid_is_exynos5800()) + if (proid_is_exynos5420()) return exynos5420_get_lcd_clk(); + else if (proid_is_exynos5800()) + return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); } @@ -1683,8 +1740,10 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk(); - else if (proid_is_exynos5420() || proid_is_exynos5800()) + else if (proid_is_exynos5420()) exynos5420_set_lcd_clk(); + else + exynos5800_set_lcd_clk(); } }
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..bf3d348 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -16,6 +16,9 @@ #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 +#define IPLL 10
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) #define MASK_RATIO(x) (0xf << (x << 4))
Dear Ajay Kumar,
On 5 December 2014 at 23:13, Ajay Kumar ajaykumar.rs@samsung.com wrote:
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
arch/arm/cpu/armv7/exynos/clock.c | 63 +++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ 2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 8fab135..1a34ad6 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1066,6 +1066,36 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; }
+static unsigned long exynos5800_get_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned long sclk;unsigned sel;
just unsigned? why don't you specify in detail?
unsigned ratio;sel = (readl(&clk->src_disp10) >> 4) & 7;
please add comment how you get "sel" from disp10. and if 7 means mask then please use 0x7. it looks more clearly.
+
/** Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into* PLLs. The first element is a placeholder to bypass the* default settig.*/const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL,IPLL, EPLL, RPLL};
please don't define local variable at middle of function. you can move it to top of the function or it seems to use sel is true then you can move it into the if statement.
if (sel)sclk = get_pll_clk(reg_map[sel]);elsesclk = 24000000;
please define this value.
/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/ratio = readl(&clk->div_disp10) & 0xf;return sclk / (ratio + 1);+}
void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); }
+void exynos5800_set_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned int cfg;/** Use RPLL for pixel clock* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]* ==================* 111: SCLK_RPLL*/cfg = readl(&clk->src_disp10) | (7 << 4);writel(cfg, &clk->src_disp10);/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/cfg = readl(&clk->div_disp10);cfg &= ~(0xf << 0);cfg |= (0 << 0);
it looks meaningless.
writel(cfg, &clk->div_disp10);+}
void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1669,8 +1724,10 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else {
if (proid_is_exynos5420() || proid_is_exynos5800())
if (proid_is_exynos5420()) return exynos5420_get_lcd_clk();else if (proid_is_exynos5800())return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); }@@ -1683,8 +1740,10 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk();
else if (proid_is_exynos5420() || proid_is_exynos5800())
else if (proid_is_exynos5420()) exynos5420_set_lcd_clk();elseexynos5800_set_lcd_clk(); }}
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..bf3d348 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -16,6 +16,9 @@ #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 +#define IPLL 10
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))
1.7.9.5
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Thanks, Minkyu Kang.
On Fri, Dec 5, 2014 at 9:02 PM, Minkyu Kang promsoft@gmail.com wrote:
Dear Ajay Kumar,
On 5 December 2014 at 23:13, Ajay Kumar ajaykumar.rs@samsung.com wrote:
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
arch/arm/cpu/armv7/exynos/clock.c | 63 +++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ 2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 8fab135..1a34ad6 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1066,6 +1066,36 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; }
+static unsigned long exynos5800_get_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned long sclk;unsigned sel;just unsigned? why don't you specify in detail?
unsigned ratio;sel = (readl(&clk->src_disp10) >> 4) & 7;please add comment how you get "sel" from disp10. and if 7 means mask then please use 0x7. it looks more clearly.
/** Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into* PLLs. The first element is a placeholder to bypass the* default settig.*/const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL,IPLL, EPLL, RPLL};please don't define local variable at middle of function. you can move it to top of the function or it seems to use sel is true then you can move it into the if statement.
if (sel)sclk = get_pll_clk(reg_map[sel]);elsesclk = 24000000;please define this value.
/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/ratio = readl(&clk->div_disp10) & 0xf;return sclk / (ratio + 1);+}
void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); }
+void exynos5800_set_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned int cfg;/** Use RPLL for pixel clock* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]* ==================* 111: SCLK_RPLL*/cfg = readl(&clk->src_disp10) | (7 << 4);writel(cfg, &clk->src_disp10);/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/cfg = readl(&clk->div_disp10);cfg &= ~(0xf << 0);cfg |= (0 << 0);it looks meaningless.
writel(cfg, &clk->div_disp10);+}
void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1669,8 +1724,10 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else {
if (proid_is_exynos5420() || proid_is_exynos5800())
if (proid_is_exynos5420()) return exynos5420_get_lcd_clk();else if (proid_is_exynos5800())return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); }@@ -1683,8 +1740,10 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk();
else if (proid_is_exynos5420() || proid_is_exynos5800())
else if (proid_is_exynos5420()) exynos5420_set_lcd_clk();elseexynos5800_set_lcd_clk(); }}
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..bf3d348 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -16,6 +16,9 @@ #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 +#define IPLL 10
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))
1.7.9.5
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Thanks, Minkyu Kang. -- from. prom.
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi Minkyu,
On Mon, Dec 8, 2014 at 11:07 AM, Ajay kumar ajaynumb@gmail.com wrote:
On Fri, Dec 5, 2014 at 9:02 PM, Minkyu Kang promsoft@gmail.com wrote:
Dear Ajay Kumar,
On 5 December 2014 at 23:13, Ajay Kumar ajaykumar.rs@samsung.com wrote:
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
arch/arm/cpu/armv7/exynos/clock.c | 63 +++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ 2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 8fab135..1a34ad6 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1066,6 +1066,36 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; }
+static unsigned long exynos5800_get_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned long sclk;unsigned sel;just unsigned? why don't you specify in detail?
I will fix this.
unsigned ratio;sel = (readl(&clk->src_disp10) >> 4) & 7;please add comment how you get "sel" from disp10. and if 7 means mask then please use 0x7. it looks more clearly.
Ok.
/** Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into* PLLs. The first element is a placeholder to bypass the* default settig.*/const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL,IPLL, EPLL, RPLL};please don't define local variable at middle of function. you can move it to top of the function or it seems to use sel is true then you can move it into the if statement.
I will move this to the top of the function.
if (sel)sclk = get_pll_clk(reg_map[sel]);elsesclk = 24000000;please define this value.
Ok.
/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/ratio = readl(&clk->div_disp10) & 0xf;return sclk / (ratio + 1);+}
void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); }
+void exynos5800_set_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned int cfg;/** Use RPLL for pixel clock* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]* ==================* 111: SCLK_RPLL*/cfg = readl(&clk->src_disp10) | (7 << 4);writel(cfg, &clk->src_disp10);/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/cfg = readl(&clk->div_disp10);cfg &= ~(0xf << 0);cfg |= (0 << 0);it looks meaningless.
Why not? I agree that the calculation can be skipped, and directly FIMD clock divider can be set to 0. But, I prefer to keep the readability. In fact, similar "meaningless" code is already part of the tree: http://git.denx.de/?p=u-boot/u-boot-samsung.git;a=blob;f=arch/arm/cpu/armv7/...
Ajay
writel(cfg, &clk->div_disp10);+}
void exynos4_set_mipi_clk(void) { struct exynos4_clock *clk = @@ -1669,8 +1724,10 @@ unsigned long get_lcd_clk(void) if (cpu_is_exynos4()) return exynos4_get_lcd_clk(); else {
if (proid_is_exynos5420() || proid_is_exynos5800())
if (proid_is_exynos5420()) return exynos5420_get_lcd_clk();else if (proid_is_exynos5800())return exynos5800_get_lcd_clk(); else return exynos5_get_lcd_clk(); }@@ -1683,8 +1740,10 @@ void set_lcd_clk(void) else { if (proid_is_exynos5250()) exynos5_set_lcd_clk();
else if (proid_is_exynos5420() || proid_is_exynos5800())
else if (proid_is_exynos5420()) exynos5420_set_lcd_clk();elseexynos5800_set_lcd_clk(); }}
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..bf3d348 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -16,6 +16,9 @@ #define BPLL 5 #define RPLL 6 #define SPLL 7 +#define CPLL 8 +#define DPLL 9 +#define IPLL 10
#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8))
#define MASK_RATIO(x) (0xf << (x << 4))
1.7.9.5
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Thanks, Minkyu Kang. -- from. prom.
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi Ajay,
On 7 December 2014 at 22:43, Ajay kumar ajaynumb@gmail.com wrote:
Hi Minkyu,
On Mon, Dec 8, 2014 at 11:07 AM, Ajay kumar ajaynumb@gmail.com wrote:
On Fri, Dec 5, 2014 at 9:02 PM, Minkyu Kang promsoft@gmail.com wrote:
Dear Ajay Kumar,
On 5 December 2014 at 23:13, Ajay Kumar ajaykumar.rs@samsung.com
wrote:
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
arch/arm/cpu/armv7/exynos/clock.c | 63 +++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ 2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 8fab135..1a34ad6 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1066,6 +1066,36 @@ static unsigned long
exynos5420_get_lcd_clk(void)
return pclk;}
+static unsigned long exynos5800_get_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned long sclk;unsigned sel;just unsigned? why don't you specify in detail?
I will fix this.
unsigned ratio;sel = (readl(&clk->src_disp10) >> 4) & 7;please add comment how you get "sel" from disp10. and if 7 means mask then please use 0x7. it looks more clearly.
Ok.
/** Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into* PLLs. The first element is a placeholder to bypass the* default settig.*/const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL,IPLL, EPLL, RPLL};please don't define local variable at middle of function. you can move it to top of the function or it seems to use sel is true then you can move it into the if statement.
I will move this to the top of the function.
if (sel)sclk = get_pll_clk(reg_map[sel]);elsesclk = 24000000;please define this value.
Ok.
/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/ratio = readl(&clk->div_disp10) & 0xf;return sclk / (ratio + 1);+}
void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); }
+void exynos5800_set_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned int cfg;/** Use RPLL for pixel clock* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]* ==================* 111: SCLK_RPLL*/cfg = readl(&clk->src_disp10) | (7 << 4);writel(cfg, &clk->src_disp10);/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/cfg = readl(&clk->div_disp10);cfg &= ~(0xf << 0);cfg |= (0 << 0);it looks meaningless.
Why not? I agree that the calculation can be skipped, and directly FIMD clock divider can be set to 0. But, I prefer to keep the readability. In fact, similar "meaningless" code is already part of the tree:
http://git.denx.de/?p=u-boot/u-boot-samsung.git;a=blob;f=arch/arm/cpu/armv7/...
Well perhaps a #define for the shift value? Then it would mean something.
Also this can probably use clrsetbits_le32().
Regards, Simon
Hi Ajay,
On 8 December 2014 at 15:40, Simon Glass sjg@google.com wrote:
Hi Ajay,
On 7 December 2014 at 22:43, Ajay kumar ajaynumb@gmail.com wrote:
Hi Minkyu,
On Mon, Dec 8, 2014 at 11:07 AM, Ajay kumar ajaynumb@gmail.com wrote:
On Fri, Dec 5, 2014 at 9:02 PM, Minkyu Kang promsoft@gmail.com wrote:
Dear Ajay Kumar,
On 5 December 2014 at 23:13, Ajay Kumar ajaykumar.rs@samsung.com wrote:
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
arch/arm/cpu/armv7/exynos/clock.c | 63 +++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ 2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 8fab135..1a34ad6 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1066,6 +1066,36 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; }
+static unsigned long exynos5800_get_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned long sclk;unsigned sel;just unsigned? why don't you specify in detail?
I will fix this.
unsigned ratio;sel = (readl(&clk->src_disp10) >> 4) & 7;please add comment how you get "sel" from disp10. and if 7 means mask then please use 0x7. it looks more clearly.
Ok.
/** Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into* PLLs. The first element is a placeholder to bypass the* default settig.*/const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL,IPLL, EPLL, RPLL};please don't define local variable at middle of function. you can move it to top of the function or it seems to use sel is true then you can move it into the if statement.
I will move this to the top of the function.
if (sel)sclk = get_pll_clk(reg_map[sel]);elsesclk = 24000000;please define this value.
Ok.
/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/ratio = readl(&clk->div_disp10) & 0xf;return sclk / (ratio + 1);+}
void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); }
+void exynos5800_set_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned int cfg;/** Use RPLL for pixel clock* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]* ==================* 111: SCLK_RPLL*/cfg = readl(&clk->src_disp10) | (7 << 4);writel(cfg, &clk->src_disp10);/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/cfg = readl(&clk->div_disp10);cfg &= ~(0xf << 0);cfg |= (0 << 0);it looks meaningless.
Why not? I agree that the calculation can be skipped, and directly FIMD clock divider can be set to 0. But, I prefer to keep the readability. In fact, similar "meaningless" code is already part of the tree:
http://git.denx.de/?p=u-boot/u-boot-samsung.git;a=blob;f=arch/arm/cpu/armv7/...
Well perhaps a #define for the shift value? Then it would mean something.
Also this can probably use clrsetbits_le32().
This is one of four patches that I think were never applied and need a respin. Are you able to do that? Then Pi LCD will work OK I think.
http://patchwork.ozlabs.org/patch/418116/ http://patchwork.ozlabs.org/patch/418117/ http://patchwork.ozlabs.org/patch/418118/ http://patchwork.ozlabs.org/patch/418119/
Regards. Simon
Hi Simon,
On Mon, Mar 2, 2015 at 7:53 AM, Simon Glass sjg@google.com wrote:
Hi Ajay,
On 8 December 2014 at 15:40, Simon Glass sjg@google.com wrote:
Hi Ajay,
On 7 December 2014 at 22:43, Ajay kumar ajaynumb@gmail.com wrote:
Hi Minkyu,
On Mon, Dec 8, 2014 at 11:07 AM, Ajay kumar ajaynumb@gmail.com wrote:
On Fri, Dec 5, 2014 at 9:02 PM, Minkyu Kang promsoft@gmail.com wrote:
Dear Ajay Kumar,
On 5 December 2014 at 23:13, Ajay Kumar ajaykumar.rs@samsung.com wrote:
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
arch/arm/cpu/armv7/exynos/clock.c | 63 +++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ 2 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 8fab135..1a34ad6 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -1066,6 +1066,36 @@ static unsigned long exynos5420_get_lcd_clk(void) return pclk; }
+static unsigned long exynos5800_get_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned long sclk;unsigned sel;just unsigned? why don't you specify in detail?
I will fix this.
unsigned ratio;sel = (readl(&clk->src_disp10) >> 4) & 7;please add comment how you get "sel" from disp10. and if 7 means mask then please use 0x7. it looks more clearly.
Ok.
/** Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into* PLLs. The first element is a placeholder to bypass the* default settig.*/const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL,IPLL, EPLL, RPLL};please don't define local variable at middle of function. you can move it to top of the function or it seems to use sel is true then you can move it into the if statement.
I will move this to the top of the function.
if (sel)sclk = get_pll_clk(reg_map[sel]);elsesclk = 24000000;please define this value.
Ok.
/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/ratio = readl(&clk->div_disp10) & 0xf;return sclk / (ratio + 1);+}
void exynos4_set_lcd_clk(void) { struct exynos4_clock *clk = @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void) writel(cfg, &clk->div_disp10); }
+void exynos5800_set_lcd_clk(void) +{
struct exynos5420_clock *clk =(struct exynos5420_clock *)samsung_get_base_clock();unsigned int cfg;/** Use RPLL for pixel clock* CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4]* ==================* 111: SCLK_RPLL*/cfg = readl(&clk->src_disp10) | (7 << 4);writel(cfg, &clk->src_disp10);/** CLK_DIV_DISP10* FIMD1_RATIO [3:0]*/cfg = readl(&clk->div_disp10);cfg &= ~(0xf << 0);cfg |= (0 << 0);it looks meaningless.
Why not? I agree that the calculation can be skipped, and directly FIMD clock divider can be set to 0. But, I prefer to keep the readability. In fact, similar "meaningless" code is already part of the tree:
http://git.denx.de/?p=u-boot/u-boot-samsung.git;a=blob;f=arch/arm/cpu/armv7/...
Well perhaps a #define for the shift value? Then it would mean something.
Also this can probably use clrsetbits_le32().
This is one of four patches that I think were never applied and need a respin. Are you able to do that? Then Pi LCD will work OK I think.
Yes, I am respinning this patch. Also, trying to move out GPIOs from smdk5420.c. Will be posting them tomorrow.
Ajay
http://patchwork.ozlabs.org/patch/418116/ http://patchwork.ozlabs.org/patch/418117/ http://patchwork.ozlabs.org/patch/418118/ http://patchwork.ozlabs.org/patch/418119/
Regards. Simon
Hi Ajay,
On 2 March 2015 at 09:07, Ajay kumar ajaynumb@gmail.com wrote:
Hi Simon,
On Mon, Mar 2, 2015 at 7:53 AM, Simon Glass sjg@google.com wrote:
Hi Ajay,
On 8 December 2014 at 15:40, Simon Glass sjg@google.com wrote:
Hi Ajay,
On 7 December 2014 at 22:43, Ajay kumar ajaynumb@gmail.com wrote:
Hi Minkyu,
On Mon, Dec 8, 2014 at 11:07 AM, Ajay kumar ajaynumb@gmail.com wrote:
On Fri, Dec 5, 2014 at 9:02 PM, Minkyu Kang promsoft@gmail.com wrote:
Dear Ajay Kumar,
On 5 December 2014 at 23:13, Ajay Kumar ajaykumar.rs@samsung.com wrote:
> Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by > exynos video driver. > > Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com > --- > arch/arm/cpu/armv7/exynos/clock.c | 63 > +++++++++++++++++++++++++++++++- > arch/arm/include/asm/arch-exynos/clk.h | 3 ++ > 2 files changed, 64 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c > b/arch/arm/cpu/armv7/exynos/clock.c > index 8fab135..1a34ad6 100644 > --- a/arch/arm/cpu/armv7/exynos/clock.c > +++ b/arch/arm/cpu/armv7/exynos/clock.c > @@ -1066,6 +1066,36 @@ static unsigned long > exynos5420_get_lcd_clk(void) > return pclk; > } > > +static unsigned long exynos5800_get_lcd_clk(void) > +{ > + struct exynos5420_clock *clk = > + (struct exynos5420_clock *)samsung_get_base_clock(); > + unsigned long sclk; > + unsigned sel; >
just unsigned? why don't you specify in detail?
I will fix this.
> + unsigned ratio; > + > + sel = (readl(&clk->src_disp10) >> 4) & 7; >
please add comment how you get "sel" from disp10. and if 7 means mask then please use 0x7. it looks more clearly.
Ok.
> + /* > + * Mapping of CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] values into > + * PLLs. The first element is a placeholder to bypass the > + * default settig. > + */ > + const int reg_map[] = {0, CPLL, DPLL, MPLL, SPLL, > + IPLL, EPLL, RPLL}; >
please don't define local variable at middle of function. you can move it to top of the function or it seems to use sel is true then you can move it into the if statement.
I will move this to the top of the function.
> + if (sel) > + sclk = get_pll_clk(reg_map[sel]); > + else > + sclk = 24000000; >
please define this value.
Ok.
> + /* > + * CLK_DIV_DISP10 > + * FIMD1_RATIO [3:0] > + */ > + ratio = readl(&clk->div_disp10) & 0xf; > + > + return sclk / (ratio + 1); > +} > + > void exynos4_set_lcd_clk(void) > { > struct exynos4_clock *clk = > @@ -1197,6 +1227,31 @@ void exynos5420_set_lcd_clk(void) > writel(cfg, &clk->div_disp10); > } > > +void exynos5800_set_lcd_clk(void) > +{ > + struct exynos5420_clock *clk = > + (struct exynos5420_clock *)samsung_get_base_clock(); > + unsigned int cfg; > + > + /* > + * Use RPLL for pixel clock > + * CLK_SRC_DISP10 CLKMUX_FIMD1 [6:4] > + * ================== > + * 111: SCLK_RPLL > + */ > + cfg = readl(&clk->src_disp10) | (7 << 4); > + writel(cfg, &clk->src_disp10); > + > + /* > + * CLK_DIV_DISP10 > + * FIMD1_RATIO [3:0] > + */ > + cfg = readl(&clk->div_disp10); > + cfg &= ~(0xf << 0); > + cfg |= (0 << 0); >
it looks meaningless.
Why not? I agree that the calculation can be skipped, and directly FIMD clock divider can be set to 0. But, I prefer to keep the readability. In fact, similar "meaningless" code is already part of the tree:
http://git.denx.de/?p=u-boot/u-boot-samsung.git;a=blob;f=arch/arm/cpu/armv7/...
Well perhaps a #define for the shift value? Then it would mean something.
Also this can probably use clrsetbits_le32().
This is one of four patches that I think were never applied and need a respin. Are you able to do that? Then Pi LCD will work OK I think.
Yes, I am respinning this patch. Also, trying to move out GPIOs from smdk5420.c. Will be posting them tomorrow.
OK great. You might find gpio_request_by_name() useful, and gpio_request_by_name_nodev() where the thing requesting the GPIOs does not use driver model yet.
Regards, Simon
The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit.
This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD.
This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index 0aff3d0..0200fd1 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2, - /* RPLL @70.5Mhz */ + /* RPLL @141Mhz */ .rpll_mdiv = 0x5E, .rpll_pdiv = 0x2, - .rpll_sdiv = 0x4, + .rpll_sdiv = 0x3,
.direct_cmd_msr = { 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
Add code to support powerup sequence for peach-pi LCD.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- board/samsung/smdk5420/smdk5420.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index a691222..915125e 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -73,19 +73,24 @@ void exynos_lcd_power_on(void)
mdelay(5);
- /* TODO(ajaykumar.rs@samsung.com): Use device tree */ - gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#"); - gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */ - mdelay(10); - gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#"); - gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */ - gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd"); - gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */ - gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE); - - if (has_edp_bridge()) + if (has_edp_bridge()) { + /* TODO(ajaykumar.rs@samsung.com): Use device tree */ + gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#"); + gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */ + mdelay(10); + gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#"); + gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */ + gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd"); + gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */ + gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE); + if (parade_init(gd->fdt_blob)) printf("%s: ps8625_init() failed\n", __func__); + } else { + gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd"); + gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */ + gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE); + } }
void exynos_backlight_on(unsigned int onoff) @@ -98,6 +103,11 @@ void exynos_backlight_on(unsigned int onoff) #ifdef CONFIG_POWER_TPS65090 tps65090_fet_enable(1); #endif + + if (!has_edp_bridge()) { + gpio_request(EXYNOS5420_GPIO_X22, "bl_en"); + gpio_direction_output(EXYNOS5420_GPIO_X22, 1); + } } #endif
On Fri, 2014-12-05 at 19:43 +0530, Ajay Kumar wrote:
Add code to support powerup sequence for peach-pi LCD.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
board/samsung/smdk5420/smdk5420.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index a691222..915125e 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -73,19 +73,24 @@ void exynos_lcd_power_on(void)
mdelay(5);
- /* TODO(ajaykumar.rs@samsung.com): Use device tree */
- gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");
- gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */
- mdelay(10);
- gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");
- gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */
- gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");
- gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */
- gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);
- if (has_edp_bridge())
- if (has_edp_bridge()) {
/* TODO(ajaykumar.rs@samsung.com): Use device tree */gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */mdelay(10);gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);- if (parade_init(gd->fdt_blob)) printf("%s: ps8625_init() failed\n", __func__);
- } else {
gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);- }
Any chance you could switch to using device-tree while changing this area. On SMDK5420 and XU3 EXYNOS5420_GPIO_X26 is used for USB so there is a bit of a potentially nastly clash there.
Hi,
On 5 December 2014 at 08:42, Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
On Fri, 2014-12-05 at 19:43 +0530, Ajay Kumar wrote:
Add code to support powerup sequence for peach-pi LCD.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
board/samsung/smdk5420/smdk5420.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index a691222..915125e 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -73,19 +73,24 @@ void exynos_lcd_power_on(void)
mdelay(5);
/* TODO(ajaykumar.rs@samsung.com): Use device tree */gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */mdelay(10);gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);if (has_edp_bridge())
if (has_edp_bridge()) {/* TODO(ajaykumar.rs@samsung.com): Use device tree */gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */mdelay(10);gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);if (parade_init(gd->fdt_blob)) printf("%s: ps8625_init() failed\n", __func__);} else {gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);}Any chance you could switch to using device-tree while changing this area. On SMDK5420 and XU3 EXYNOS5420_GPIO_X26 is used for USB so there is a bit of a potentially nastly clash there.
Yes we should really do that.
Regards, Simon
Hi,
On Fri, Dec 5, 2014 at 10:12 PM, Simon Glass sjg@google.com wrote:
Hi,
On 5 December 2014 at 08:42, Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
On Fri, 2014-12-05 at 19:43 +0530, Ajay Kumar wrote:
Add code to support powerup sequence for peach-pi LCD.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
board/samsung/smdk5420/smdk5420.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index a691222..915125e 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -73,19 +73,24 @@ void exynos_lcd_power_on(void)
mdelay(5);
/* TODO(ajaykumar.rs@samsung.com): Use device tree */gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */mdelay(10);gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);if (has_edp_bridge())
if (has_edp_bridge()) {/* TODO(ajaykumar.rs@samsung.com): Use device tree */gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */mdelay(10);gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);if (parade_init(gd->fdt_blob)) printf("%s: ps8625_init() failed\n", __func__);} else {gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);}Any chance you could switch to using device-tree while changing this area. On SMDK5420 and XU3 EXYNOS5420_GPIO_X26 is used for USB so there is a bit of a potentially nastly clash there.
Yes we should really do that.
I am trying to consolidate what all needs to be done for Exynos5250 and Exynos5420, in order to remove LCD routines from the board files. Here are my observations: 1) A separate driver for ptn3460 should be created. 2) Need a place holder for tps65090 FET settings. 3) I am planning to move all the LCD_EN/BACKLIGHT_EN GPIOs to the "weak function definitions" in exynos_fb.c. In that case, we have a limitation. All boards under a specific SOC should conform to use only device tree or use only define board level LCD routines. ex: smdk5250 and snow - both need to use device tree to specify LCD details, or both need to define LCD powerup routines. It cannot be like snow uses device tree, and smdk5250 defines LCD routines in smdk5250 board file.
Ajay
Hi Ajay,
On 7 December 2014 at 23:45, Ajay kumar ajaynumb@gmail.com wrote:
Hi,
On Fri, Dec 5, 2014 at 10:12 PM, Simon Glass sjg@google.com wrote:
Hi,
On 5 December 2014 at 08:42, Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
On Fri, 2014-12-05 at 19:43 +0530, Ajay Kumar wrote:
Add code to support powerup sequence for peach-pi LCD.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
board/samsung/smdk5420/smdk5420.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index a691222..915125e 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -73,19 +73,24 @@ void exynos_lcd_power_on(void)
mdelay(5);
/* TODO(ajaykumar.rs@samsung.com): Use device tree */gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */mdelay(10);gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);if (has_edp_bridge())
if (has_edp_bridge()) {/* TODO(ajaykumar.rs@samsung.com): Use device tree */gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */mdelay(10);gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);if (parade_init(gd->fdt_blob)) printf("%s: ps8625_init() failed\n", __func__);} else {gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);}Any chance you could switch to using device-tree while changing this area. On SMDK5420 and XU3 EXYNOS5420_GPIO_X26 is used for USB so there is a bit of a potentially nastly clash there.
Yes we should really do that.
I am trying to consolidate what all needs to be done for Exynos5250 and Exynos5420, in order to remove LCD routines from the board files. Here are my observations:
- A separate driver for ptn3460 should be created.
- Need a place holder for tps65090 FET settings.
- I am planning to move all the LCD_EN/BACKLIGHT_EN GPIOs to the "weak function definitions" in exynos_fb.c. In that case, we have a limitation. All boards under a specific
SOC should conform to use only device tree or use only define board level LCD routines. ex: smdk5250 and snow - both need to use device tree to specify LCD details, or both need to define LCD powerup routines. It cannot be like snow uses device tree, and smdk5250 defines LCD routines in smdk5250 board file.
Do any boards exist which don't use device tree? I think we can drop that old support.
For a recent Tegra series I used the kernel device tree binding and just picked out information about the regulators. It might be possible to do the same on Exynos. See for example get_backlight_info() in this patch: http://patchwork.ozlabs.org/patch/416675/
Regards, Simon
Hi Ajay,
(resending sorry)
On 7 December 2014 at 23:45, Ajay kumar ajaynumb@gmail.com wrote:
Hi,
On Fri, Dec 5, 2014 at 10:12 PM, Simon Glass sjg@google.com wrote:
Hi,
On 5 December 2014 at 08:42, Sjoerd Simons sjoerd.simons@collabora.co.uk wrote:
On Fri, 2014-12-05 at 19:43 +0530, Ajay Kumar wrote:
Add code to support powerup sequence for peach-pi LCD.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com
board/samsung/smdk5420/smdk5420.c | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/board/samsung/smdk5420/smdk5420.c b/board/samsung/smdk5420/smdk5420.c index a691222..915125e 100644 --- a/board/samsung/smdk5420/smdk5420.c +++ b/board/samsung/smdk5420/smdk5420.c @@ -73,19 +73,24 @@ void exynos_lcd_power_on(void)
mdelay(5);
/* TODO(ajaykumar.rs@samsung.com): Use device tree */gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */mdelay(10);gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);if (has_edp_bridge())
if (has_edp_bridge()) {/* TODO(ajaykumar.rs@samsung.com): Use device tree */gpio_request(EXYNOS5420_GPIO_X35, "edp_slp#");gpio_direction_output(EXYNOS5420_GPIO_X35, 1); /* EDP_SLP# */mdelay(10);gpio_request(EXYNOS5420_GPIO_Y77, "edp_rst#");gpio_direction_output(EXYNOS5420_GPIO_Y77, 1); /* EDP_RST# */gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);if (parade_init(gd->fdt_blob)) printf("%s: ps8625_init() failed\n", __func__);} else {gpio_request(EXYNOS5420_GPIO_X26, "edp_hpd");gpio_direction_input(EXYNOS5420_GPIO_X26); /* EDP_HPD */gpio_set_pull(EXYNOS5420_GPIO_X26, S5P_GPIO_PULL_NONE);}Any chance you could switch to using device-tree while changing this area. On SMDK5420 and XU3 EXYNOS5420_GPIO_X26 is used for USB so there is a bit of a potentially nastly clash there.
Yes we should really do that.
I am trying to consolidate what all needs to be done for Exynos5250 and Exynos5420, in order to remove LCD routines from the board files. Here are my observations:
- A separate driver for ptn3460 should be created.
- Need a place holder for tps65090 FET settings.
- I am planning to move all the LCD_EN/BACKLIGHT_EN GPIOs to the "weak function definitions" in exynos_fb.c. In that case, we have a limitation. All boards under a specific
SOC should conform to use only device tree or use only define board level LCD routines. ex: smdk5250 and snow - both need to use device tree to specify LCD details, or both need to define LCD powerup routines. It cannot be like snow uses device tree, and smdk5250 defines LCD routines in smdk5250 board file.
Do any boards exist which don't use device tree? I think we can drop that old support.
For a recent Tegra series I used the kernel device tree binding and just picked out information about the regulators. It might be possible to do the same on Exynos. See for example get_backlight_info() in this patch: http://patchwork.ozlabs.org/patch/416675/
Regards, Simon
Add some delay after powering up the peach_pi eDP panel, to make sure the panel is ready for link training.
Signed-off-by: Ajay Kumar ajaykumar.rs@samsung.com --- arch/arm/dts/exynos5800-peach-pi.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 2f9d2db..109dab5 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -144,6 +144,7 @@ samsung,vl-vfpd = <10>; samsung,vl-cmd-allow-len = <0xf>;
+ samsung,power-on-delay = <30000>; samsung,winid = <3>; samsung,interface-mode = <1>; samsung,dp-enabled = <1>;
Hi Ajay,
On 5 December 2014 at 07:13, Ajay Kumar ajaykumar.rs@samsung.com wrote:
Add support for the eDP panel supported on peach_pi.
Sjoerd Simons(1): [PATCH 1/5] Exynos5800: The Peach-Pi board does not have a Parade video bridge
Ajay Kumar (4): [PATCH 2/5] arm: exynos: add display clocks for Exynos5800 [PATCH 3/5] Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels [PATCH 4/5] exynos5420: Add LCD and LED powerup settings for peach-pi [PATCH 5/5] peach_pi: dts: Add lcd poweron delay
arch/arm/cpu/armv7/exynos/clock.c | 63 +++++++++++++++++++++++- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 4 +- arch/arm/dts/exynos5800-peach-pi.dts | 6 +-- arch/arm/include/asm/arch-exynos/clk.h | 3 ++ board/samsung/smdk5420/smdk5420.c | 32 +++++++----- 5 files changed, 88 insertions(+), 20 deletions(-)
Are you planning to respin this series? It looks like two of the patches need adjustments.
Regards, Simon
participants (6)
-
Ajay Kumar -
Ajay kumar -
Minkyu Kang -
Simon Glass -
Simon Glass -
Sjoerd Simons