[PATCH v4 0/5] imx93: Conver to OF_UPSTREAM

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Armada 3720 alike Board - no PHY...

Peng Fan (OSS)

28 Mar 2024 28 Mar '24

6:05 a.m.

A few nodes were added to soc and board u-boot.dtsi(lpi2c, usbotg), those nodes could be dropped after upstream linux supports them.

To support OF_UPSTREAM, a few driver changes are included. For TMU, still use U-Boot node, I will prepare a kernel update, then back to U-Boot support.

Mathieu: please help test the boards you maintain when you have time.

Thanks, Peng.

To: Sébastien Szymanski sebastien.szymanski@armadeus.com To: Stefano Babic sbabic@denx.de To: Fabio Estevam festevam@gmail.com To: "NXP i.MX U-Boot Team" uboot-imx@nxp.com To: Mathieu Othacehe m.othacehe@gmail.com Cc: u-boot@lists.denx.de Signed-off-by: Peng Fan peng.fan@nxp.com

Changes in v4: - Convert all i.MX93 boards - Link to v3: https://lore.kernel.org/r/20240328-imx93-of-v3-0-4e7f341ed7ea@nxp.com

Changes in v3: - Update patch 5, to drop the imx8mp-evk changes which are wrongly included - Link to v2: https://lore.kernel.org/r/20240328-imx93-of-v2-0-909f5d37da87@nxp.com

Changes in v2: - Add a new patch to sync clock header to avoid breaking - Drop the Makefile change which change including order - Link to v1: https://lore.kernel.org/r/20240327-imx93-of-v1-0-afab6b31422a@nxp.com

--- Peng Fan (5): gpio: imx_rgpio2p: support one address serial: lpuart: use ipg clk for i.MX7ULP cpu: drop imx9_cpu clk: imx93: fix anatop base imx93: convert to OF_UPSTREAM

arch/arm/dts/Makefile | 5 - arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 119 ++++ arch/arm/dts/imx93-11x11-evk.dts | 322 --------- arch/arm/dts/imx93-phyboard-segin.dts | 117 --- arch/arm/dts/imx93-phycore-som.dtsi | 126 ---- arch/arm/dts/imx93-pinfunc.h | 623 ---------------- arch/arm/dts/imx93-u-boot.dtsi | 80 +++ arch/arm/dts/imx93-var-som-symphony-u-boot.dtsi | 22 + arch/arm/dts/imx93-var-som-symphony.dts | 323 --------- arch/arm/dts/imx93-var-som.dtsi | 111 --- arch/arm/dts/imx93.dtsi | 906 ------------------------ arch/arm/mach-imx/imx9/Kconfig | 1 + configs/imx93-phyboard-segin_defconfig | 2 +- configs/imx93_11x11_evk_defconfig | 2 +- configs/imx93_11x11_evk_ld_defconfig | 2 +- configs/imx93_var_som_defconfig | 2 +- drivers/clk/imx/clk-imx93.c | 2 +- drivers/cpu/imx9_cpu.c | 224 ------ drivers/gpio/imx_rgpio2p.c | 42 +- drivers/serial/serial_lpuart.c | 9 +- include/dt-bindings/clock/imx93-clock.h | 208 ------ include/dt-bindings/power/fsl,imx93-power.h | 15 - 22 files changed, 273 insertions(+), 2990 deletions(-) --- base-commit: 280f34ba7d68bb50c0b8eaa040322c1f3b37d46e change-id: 20240328-imx93-of-v2-f879efef737d

Best regards,

-- Peng Fan peng.fan@nxp.com

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Peng Fan (OSS)

28 Mar 28 Mar

6:05 a.m.

New subject: [PATCH v4 1/5] gpio: imx_rgpio2p: support one address

From: Peng Fan peng.fan@nxp.com

The i.MX8ULP/93 gpio dt-schema have been updated to only have one address entry, update the driver to support it.

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/gpio/imx_rgpio2p.c | 42 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-)

diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index 175e460aff5..3227a8d5b57 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -21,6 +21,12 @@ enum imx_rgpio2p_direction {

#define GPIO_PER_BANK 32

+struct imx_rgpio2p_soc_data { + bool have_dual_base; +}; + +#define IMX8ULP_GPIO_BASE_OFF 0x40 + struct imx_rgpio2p_data { struct gpio_regs *regs; }; @@ -165,6 +171,9 @@ static int imx_rgpio2p_probe(struct udevice *dev) static int imx_rgpio2p_bind(struct udevice *dev) { struct imx_rgpio2p_plat *plat = dev_get_plat(dev); + struct imx_rgpio2p_soc_data *data = + (struct imx_rgpio2p_soc_data *)dev_get_driver_data(dev); + bool dual_base = data->have_dual_base; fdt_addr_t addr;

/* @@ -176,9 +185,26 @@ static int imx_rgpio2p_bind(struct udevice *dev) if (plat) return 0;

- addr = devfdt_get_addr_index(dev, 1); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; + /* + * Handle legacy compatible combinations which used two reg values + * for the i.MX8ULP and i.MX93. + */ + if (device_is_compatible(dev, "fsl,imx7ulp-gpio") && + (device_is_compatible(dev, "fsl,imx93-gpio") || + (device_is_compatible(dev, "fsl,imx8ulp-gpio")))) + dual_base = true; + + if (dual_base) { + addr = devfdt_get_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + } else { + addr = devfdt_get_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + addr += IMX8ULP_GPIO_BASE_OFF; + }

/* * TODO: @@ -202,9 +228,17 @@ static int imx_rgpio2p_bind(struct udevice *dev) return 0; }

+static struct imx_rgpio2p_soc_data imx7ulp_data = { + .have_dual_base = true, +}; + +static struct imx_rgpio2p_soc_data imx8ulp_data = { + .have_dual_base = false, +};

static const struct udevice_id imx_rgpio2p_ids[] = { - { .compatible = "fsl,imx7ulp-gpio" }, + { .compatible = "fsl,imx7ulp-gpio", .data = (ulong)&imx7ulp_data }, + { .compatible = "fsl,imx8ulp-gpio", .data = (ulong)&imx8ulp_data }, { } };

-- 2.35.3

Peng Fan (OSS)

6:05 a.m.

New subject: [PATCH v4 2/5] serial: lpuart: use ipg clk for i.MX7ULP

From: Peng Fan peng.fan@nxp.com

To i.MX7ULP compatible lpuart, there is only ipg clk, no per clk. So add a devtype check for i.MX7ULP.

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/serial/serial_lpuart.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index ce08a6b4486..653ff99e67b 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -111,11 +111,18 @@ u32 __weak get_lpuart_clk(void) #if CONFIG_IS_ENABLED(CLK) static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk) { + struct lpuart_serial_plat *plat = dev_get_plat(dev); struct clk per_clk; ulong rate; int ret; + char *name;

- ret = clk_get_by_name(dev, "per", &per_clk); + if (plat->devtype == DEV_MX7ULP) + name = "ipg"; + else + name = "per"; + + ret = clk_get_by_name(dev, name, &per_clk); if (ret) { dev_err(dev, "Failed to get per clk: %d\n", ret); return ret;

-- 2.35.3

Peng Fan (OSS)

6:05 a.m.

New subject: [PATCH v4 3/5] cpu: drop imx9_cpu

From: Peng Fan peng.fan@nxp.com

This was wrongly committed, no user, remove it.

Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/cpu/imx9_cpu.c | 224 ------------------------------------------------- 1 file changed, 224 deletions(-)

diff --git a/drivers/cpu/imx9_cpu.c b/drivers/cpu/imx9_cpu.c deleted file mode 100644 index 66534fe6d17..00000000000 --- a/drivers/cpu/imx9_cpu.c +++ /dev/null @@ -1,224 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - */ - -#include <common.h> -#include <cpu.h> -#include <dm.h> -#include <thermal.h> -#include <asm/global_data.h> -#include <asm/system.h> -#include <firmware/linux/imx/sci/sci.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch-imx/cpu.h> -#include <asm/armv8/cpu.h> -#include <linux/bitops.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct cpu_imx_plat { - const char *name; - const char *rev; - const char *type; - u32 cpu_rsrc; - u32 cpurev; - u32 freq_mhz; - u32 mpidr; -}; - -const char *get_imx9_type(u32 imxtype) -{ - switch (imxtype) { - case MXC_CPU_IMX93: - return "93"; - default: - return "??"; - } -} - -const char *get_imx9_rev(u32 rev) -{ - switch (rev) { - case CHIP_REV_1_0: - return "1."; - case CHIP_REV_B: - return "B"; - case CHIP_REV_C: - return "C"; - default: - return "?"; - } -} - -static void set_core_data(struct udevice *dev) -{ - struct cpu_imx_plat *plat = dev_get_plat(dev); - - if (device_is_compatible(dev, "arm,cortex-a35")) - plat->name = "A35"; - else - plat->name = "?"; -} - -#if IS_ENABLED(CONFIG_IMX_SCU_THERMAL) -static int cpu_imx_get_temp(struct cpu_imx_plat *plat) -{ - struct udevice *thermal_dev; - int cpu_tmp, ret; - int idx = 1; /* use "cpu-thermal0" device */ - - if (plat->cpu_rsrc == SC_R_A72) - idx = 2; /* use "cpu-thermal1" device */ - - ret = uclass_get_device(UCLASS_THERMAL, idx, &thermal_dev); - if (!ret) { - ret = thermal_get_temp(thermal_dev, &cpu_tmp); - if (ret) - return 0xdeadbeef; - } else { - return 0xdeadbeef; - } - - return cpu_tmp; -} -#else -static int cpu_imx_get_temp(struct cpu_imx_plat *plat) -{ - return 0; -} -#endif - -int cpu_imx_get_desc(const struct udevice *dev, char *buf, int size) -{ - struct cpu_imx_plat *plat = dev_get_plat(dev); - int ret, temp; - - if (size < 100) - return -ENOSPC; - - ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz", - plat->type, plat->rev, plat->name, plat->freq_mhz); - - if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) { - temp = cpu_imx_get_temp(plat); - buf = buf + ret; - size = size - ret; - if (temp != 0xdeadbeef) - ret = snprintf(buf, size, " at %dC", temp); - else - ret = snprintf(buf, size, " - invalid sensor data"); - } - - snprintf(buf + ret, size - ret, "\n"); - - return 0; -} - -static int cpu_imx_get_info(const struct udevice *dev, struct cpu_info *info) -{ - struct cpu_imx_plat *plat = dev_get_plat(dev); - - info->cpu_freq = plat->freq_mhz * 1000; - info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU); - return 0; -} - -static int cpu_imx_get_count(const struct udevice *dev) -{ - ofnode node; - int num = 0; - - ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { - const char *device_type; - - if (!ofnode_is_enabled(node)) - continue; - - device_type = ofnode_read_string(node, "device_type"); - if (!device_type) - continue; - - if (!strcmp(device_type, "cpu")) - num++; - } - - return num; -} - -static int cpu_imx_get_vendor(const struct udevice *dev, char *buf, int size) -{ - snprintf(buf, size, "NXP"); - return 0; -} - -static int cpu_imx_is_current(struct udevice *dev) -{ - struct cpu_imx_plat *plat = dev_get_plat(dev); - - if (plat->mpidr == (read_mpidr() & 0xffff)) - return 1; - - return 0; -} - -static const struct cpu_ops cpu_imx9_ops = { - .get_desc = cpu_imx_get_desc, - .get_info = cpu_imx_get_info, - .get_count = cpu_imx_get_count, - .get_vendor = cpu_imx_get_vendor, - .is_current = cpu_imx_is_current, -}; - -static const struct udevice_id cpu_imx9_ids[] = { - { .compatible = "arm,cortex-a35" }, - { .compatible = "arm,cortex-a53" }, - { .compatible = "arm,cortex-a72" }, - { } -}; - -static ulong imx9_get_cpu_rate(struct udevice *dev) -{ - struct cpu_imx_plat *plat = dev_get_plat(dev); - ulong rate; - int ret; - - ret = sc_pm_get_clock_rate(-1, plat->cpu_rsrc, SC_PM_CLK_CPU, - (sc_pm_clock_rate_t *)&rate); - if (ret) { - printf("Could not read CPU frequency: %d\n", ret); - return 0; - } - - return rate; -} - -static int imx9_cpu_probe(struct udevice *dev) -{ - struct cpu_imx_plat *plat = dev_get_plat(dev); - u32 cpurev; - - set_core_data(dev); - cpurev = get_cpu_rev(); - plat->cpurev = cpurev; - plat->rev = get_imx9_rev(cpurev & 0xFFF); - plat->type = get_imx9_type((cpurev & 0xFF000) >> 12); - plat->freq_mhz = imx9_get_cpu_rate(dev) / 1000000; - plat->mpidr = dev_read_addr(dev); - if (plat->mpidr == FDT_ADDR_T_NONE) { - printf("%s: Failed to get CPU reg property\n", __func__); - return -EINVAL; - } - - return 0; -} - -U_BOOT_DRIVER(cpu_imx9_drv) = { - .name = "imx9x_cpu", - .id = UCLASS_CPU, - .of_match = cpu_imx9_ids, - .ops = &cpu_imx9_ops, - .probe = imx9_cpu_probe, - .plat_auto = sizeof(struct cpu_imx_plat), - .flags = DM_FLAG_PRE_RELOC, -};

-- 2.35.3

Peng Fan (OSS)

6:05 a.m.

New subject: [PATCH v4 4/5] clk: imx93: fix anatop base

From: Peng Fan peng.fan@nxp.com

The PLL clk needs use anatop base, otherwise wrong PLL address will be used.

Fixes: 9c153e46661b ("clk: imx: add i.MX93 CCF driver") Signed-off-by: Peng Fan peng.fan@nxp.com --- drivers/clk/imx/clk-imx93.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index ce10d795316..f0cb797d975 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -289,7 +289,7 @@ static int imx93_clk_probe(struct udevice *dev) clk_dm(IMX93_CLK_SYS_PLL_PFD2_DIV2, imx_clk_fixed_factor("sys_pll_pfd2_div2", "sys_pll_pfd2", 1, 2));

- base = (void *)ANATOP_BASE_ADDR; + anatop_base = (void *)ANATOP_BASE_ADDR;

clk_dm(IMX93_CLK_ARM_PLL, imx_clk_fracn_gppll_integer("arm_pll", "clock-osc-24m",

-- 2.35.3

Peng Fan (OSS)

6:05 a.m.

New subject: [PATCH v4 5/5] imx93: convert to OF_UPSTREAM

From: Peng Fan peng.fan@nxp.com

Convert all i.MX93 boards to OF_UPSTREAM.

Add lpi2c2 nodes for imx93-11x11-evk-u-boot.dtsi. Add usbotg1 nodes in imx93-u-boot.dtsi and board u-boot.dtsi. The nodes could be removed after upstream linux supports them.

Signed-off-by: Peng Fan peng.fan@nxp.com --- arch/arm/dts/Makefile | 5 - arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 119 ++++ arch/arm/dts/imx93-11x11-evk.dts | 322 --------- arch/arm/dts/imx93-phyboard-segin.dts | 117 --- arch/arm/dts/imx93-phycore-som.dtsi | 126 ---- arch/arm/dts/imx93-pinfunc.h | 623 ---------------- arch/arm/dts/imx93-u-boot.dtsi | 80 +++ arch/arm/dts/imx93-var-som-symphony-u-boot.dtsi | 22 + arch/arm/dts/imx93-var-som-symphony.dts | 323 --------- arch/arm/dts/imx93-var-som.dtsi | 111 --- arch/arm/dts/imx93.dtsi | 906 ------------------------ arch/arm/mach-imx/imx9/Kconfig | 1 + configs/imx93-phyboard-segin_defconfig | 2 +- configs/imx93_11x11_evk_defconfig | 2 +- configs/imx93_11x11_evk_ld_defconfig | 2 +- configs/imx93_var_som_defconfig | 2 +- include/dt-bindings/clock/imx93-clock.h | 208 ------ include/dt-bindings/power/fsl,imx93-power.h | 15 - 18 files changed, 226 insertions(+), 2760 deletions(-)

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d85a33055c9..75d9ee06bbf 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1114,11 +1114,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-kontron-pitx-imx8m.dtb \ imx8mq-librem5-r4.dtb

-dtb-$(CONFIG_ARCH_IMX9) += \ - imx93-11x11-evk.dtb \ - imx93-var-som-symphony.dtb \ - imx93-phyboard-segin.dtb - dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb \ imxrt1170-evk.dtb \ diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi index a99ba99bfb4..4a834ded44c 100644 --- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi +++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi @@ -26,6 +26,112 @@ bootph-pre-ram; };

+/* The node should be removed after upstream supports it */ +&lpi2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9451a"; + reg = <0x25>; + interrupt-parent = <&pcal6524>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcal6524>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; + }; + + adp5585gpio: gpio@34 { + compatible = "adp5585"; + reg = <0x34>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + &aips1 { bootph-pre-ram; bootph-all; @@ -44,6 +150,19 @@ &iomuxc { bootph-pre-ram; bootph-some-ram; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e + >; + }; };

&reg_usdhc2_vmmc { diff --git a/arch/arm/dts/imx93-11x11-evk.dts deleted file mode 100644 index 4322cc3e11b..00000000000 --- a/arch/arm/dts/imx93-11x11-evk.dts +++ /dev/null @@ -1,322 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ -/* - * Copyright 2022 NXP - */ - -/dts-v1/; - -#include "imx93.dtsi" - -/ { - model = "NXP i.MX93 11X11 - compatible = "fsl,imx93-11x11-evk", - - chosen { - stdout-path = &lpuart1; - }; - - reg_vref_1v8: regulator-adc-vref { - compatible = "regulator-fixed&quo - regulator-name = "vref_1v8"; - regulator-min-microvolt = <1800000& - regulator-max-microvolt = <1800000& - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed&quo - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000& - regulator-max-microvolt = <3300000& - gpio = <&gpio3 7 GPIO_ACTIVE_HI - enable-active-high; - }; -}; - -&adc1 { - vref-supply = <&reg_vref_1v8> - status = "okay"; -}; - -&mu1 { - status = "okay"; -}; - -&mu2 { - status = "okay"; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <&ethphy1>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio&quo - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy1: ethernet-phy@1 { - reg = <1>; - eee-broken-1000t; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <&ethphy2>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <5000000>; - - ethphy2: ethernet-phy@2 { - reg = <2>; - eee-broken-1000t; - }; - }; -}; - -&lpi2c2 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <400000>; - pinctrl-names = "default", - pinctrl-0 = <&pinctrl_lpi2c2> - pinctrl-1 = <&pinctrl_lpi2c2> - status = "okay"; - - pmic@25 { - compatible = "nxp,pca9451a"; - reg = <0x25>; - interrupt-parent = <&pcal6524&g - interrupts = <11 IRQ_TYPE_LEVEL_LOW - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <650000 - regulator-max-microvolt = <223750 - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000 - regulator-max-microvolt = <218750 - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck4: BUCK4{ - regulator-name = "BUCK4"; - regulator-min-microvolt = <600000 - regulator-max-microvolt = <340000 - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5{ - regulator-name = "BUCK5"; - regulator-min-microvolt = <600000 - regulator-max-microvolt = <340000 - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000 - regulator-max-microvolt = <340000 - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <160000 - regulator-max-microvolt = <330000 - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000 - regulator-max-microvolt = <330000 - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <180000 - regulator-max-microvolt = <330000 - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - pcal6524: gpio@22 { - compatible = "nxp,pcal6524"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcal6524& - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&gpio3>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW - }; - - adp5585gpio: gpio@34 { - compatible = "adp5585"; - reg = <0x34>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&lpuart1 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", - pinctrl-0 = <&pinctrl_usdhc1> - pinctrl-1 = <&pinctrl_usdhc1> - pinctrl-2 = <&pinctrl_usdhc1> - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", - pinctrl-0 = <&pinctrl_usdhc2>, - pinctrl-1 = <&pinctrl_usdhc2>, - pinctrl-2 = <&pinctrl_usdhc2>, - cd-gpios = <&gpio3 00 GPIO_ACTIV - vmmc-supply = <&reg_usdhc2_vmmc& - bus-width = <4>; - status = "okay"; - no-sdio; - no-mmc; -}; - -&iomuxc { - pinctrl_lpi2c2: lpi2c2grp { - fsl,pins = < - MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x400 - MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x400 - >; - }; - - pinctrl_pcal6524: pcal6524grp { - fsl,pins = < - MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31 - >; - }; - - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO - MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD - MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD - MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD - MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD - MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOC - MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII - MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD - MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD - MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD - MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD - MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOC - MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII - >; - }; - - pinctrl_fec: fecgrp { - fsl,pins = < - MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e - MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x5 - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 - MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 - MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 - MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 - MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 - MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 - MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31 - MX93_PAD_UART1_TXD__LPUART1_TX 0x31 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13 - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13 - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13 - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13 - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13 - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13 - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13 - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13 - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp - fsl,pins = < - MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31 - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13 - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13 - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13 - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13 - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT - >; - }; -}; diff --git a/arch/arm/dts/imx93-phyboard-segin.dts deleted file mode 100644 index 85fb188b057..00000000000 --- a/arch/arm/dts/imx93-phyboard-segin.d +++ /dev/null @@ -1,117 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ -/* - * Copyright (C) 2023 PHYTEC Messtechnik - * Author: Wadim Egorov w.egorov@phytec.de, Christoph Stoidner c.stoidner@phytec.de m.othacehe@gmail.com is reused for the i.MX93 design. phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6ul/">https://www.phytec.eu/en/produkte/single-board-computer/phyboard-segin-imx6u... ot; X93"; d-segin", "phytec,imx93-phycore-som", t;; GH>; 2_vmmc>; gt;; gt;; "state_100mhz", "state_200mhz"; <&pinctrl_usdhc2_cd>; <&pinctrl_usdhc2_cd>; <&pinctrl_usdhc2_cd>; _LOW>; gt;; { e 8e 8e 8e 9e 0x51e 0x179e 0x139e 0x138e 0x138e 0x139e 0x139e 0x51e 0x178e 0x139e 0x139e 0x139e 0x139e 0x139e 0x51e b/arch/arm/dts/imx93-phycore-som.dtsi OR MIT) GmbH href="mailto:w.egorov@phytec.de">w.egorov@phytec.de, Christoph Stoidner c.stoidner@phytec.de m.othacehe@gmail.com phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/">https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ t; t;; "fsl,imx93"; ot;; 0 0x40000000>; HIGH>; at"; IMX93_CLK_ENET_TIMER1>, , >; IMX93_CLK_SYS_PLL_PFD1_DIV2>, _DIV2>, _DIV2>; <50000000>, <50000000>; 02.3-c22"; ; 02 0x57e 0x57e fe _CTL 0x57e 0x50e 0x50e _CTL 0x50e 000050e 8e 86 8e 86 86 86 86 86 179e b/arch/arm/dts/imx93-pinfunc.h OR MIT) */ mux_mode input_val> 0x0000 0x01B0 0x03D8 0x0 0x0 0x0000 0x01B0 0x0000 0x1 0x0 0x0000 0x01B0 0x0000 0x3 0x0 0x0000 0x01B0 0x0000 0x4 0x0 0x0000 0x01B0 0x0000 0x5 0x0 0x0000 0x01B0 0x0430 0x6 0x0 0x0004 0x01B4 0x03DC 0x0 0x0 0x0004 0x01B4 0x0000 0x4 0x0 0x0004 0x01B4 0x0000 0x5 0x0 0x0004 0x01B4 0x0000 0x6 0x0 0x0008 0x01B8 0x03D4 0x0 0x0 0x0008 0x01B8 0x0000 0x4 0x0 0x0008 0x01B8 0x0000 0x5 0x0 0x0008 0x01B8 0x042C 0x6 0x0 0x000C 0x01BC 0x0000 0x0 0x0 0x000C 0x01BC 0x0000 0x1 0x0 0x000C 0x01BC 0x0364 0x3 0x0 0x000C 0x01BC 0x0000 0x4 0x0 0x000C 0x01BC 0x0000 0x5 0x0 0x000C 0x01BC 0x0434 0x6 0x0 0x0010 0x01C0 0x0000 0x0 0x0 0x0010 0x01C0 0x03E4 0x11 0x0 0x0010 0x01C0 0x0000 0x2 0x0 0x0010 0x01C0 0x0000 0x3 0x0 0x0010 0x01C0 0x0000 0x4 0x0 0x0010 0x01C0 0x0434 0x5 0x1 0x0010 0x01C0 0x03EC 0x16 0x0 0x0010 0x01C0 0x036C 0x7 0x0 0x0014 0x01C4 0x0000 0x0 0x0 0x0014 0x01C4 0x03E0 0x11 0x0 0x0014 0x01C4 0x0000 0x2 0x0 0x0014 0x01C4 0x0000 0x3 0x0 0x0014 0x01C4 0x0000 0x4 0x0 0x0014 0x01C4 0x0430 0x5 0x1 0x0014 0x01C4 0x03E8 0x16 0x0 0x0014 0x01C4 0x0370 0x7 0x0 0x0018 0x01C8 0x0000 0x0 0x0 0x0018 0x01C8 0x0000 0x11 0x0 0x0018 0x01C8 0x0000 0x2 0x0 0x0018 0x01C8 0x0000 0x3 0x0 0x0018 0x01C8 0x0000 0x4 0x0 0x0018 0x01C8 0x042C 0x5 0x1 0x0018 0x01C8 0x03F4 0x16 0x0 0x0018 0x01C8 0x0374 0x7 0x0 0x001C 0x01CC 0x0000 0x0 0x0 0x001C 0x01CC 0x0000 0x11 0x0 0x001C 0x01CC 0x0000 0x2 0x0 0x001C 0x01CC 0x0000 0x3 0x0 0x001C 0x01CC 0x0000 0x4 0x0 0x001C 0x01CC 0x0000 0x5 0x0 0x001C 0x01CC 0x03F0 0x16 0x0 0x001C 0x01CC 0x0378 0x7 0x0 0x0020 0x01D0 0x0000 0x0 0x0 0x0020 0x01D0 0x0000 0x1 0x0 0x0020 0x01D0 0x0000 0x2 0x0 0x0020 0x01D0 0x0000 0x3 0x0 0x0020 0x01D0 0x0000 0x4 0x0 0x0020 0x01D0 0x0000 0x5 0x0 0x0020 0x01D0 0x03F4 0x16 0x1 0x0020 0x01D0 0x037C 0x7 0x0 0x0024 0x01D4 0x0000 0x0 0x0 0x0024 0x01D4 0x0000 0x1 0x0 0x0024 0x01D4 0x0438 0x2 0x0 0x0024 0x01D4 0x0000 0x3 0x0 0x0024 0x01D4 0x0000 0x4 0x0 0x0024 0x01D4 0x0000 0x5 0x0 0x0024 0x01D4 0x03F0 0x16 0x1 0x0024 0x01D4 0x0380 0x7 0x0 0x0028 0x01D8 0x0000 0x0 0x0 0x0028 0x01D8 0x0000 0x1 0x0 0x0028 0x01D8 0x043C 0x2 0x0 0x0028 0x01D8 0x0000 0x3 0x0 0x0028 0x01D8 0x0000 0x4 0x0 0x0028 0x01D8 0x0000 0x5 0x0 0x0028 0x01D8 0x03FC 0x16 0x0 0x0028 0x01D8 0x0384 0x7 0x0 0x002C 0x01DC 0x0000 0x0 0x0 0x002C 0x01DC 0x0000 0x1 0x0 0x002C 0x01DC 0x0000 0x2 0x0 0x002C 0x01DC 0x0000 0x3 0x0 0x002C 0x01DC 0x0000 0x4 0x0 0x002C 0x01DC 0x0000 0x5 0x0 0x002C 0x01DC 0x03F8 0x16 0x0 0x002C 0x01DC 0x0388 0x7 0x0 0x0030 0x01E0 0x0000 0x0 0x0 0x0030 0x01E0 0x0000 0x1 0x0 0x0030 0x01E0 0x0000 0x2 0x0 0x0030 0x01E0 0x0000 0x3 0x0 0x0030 0x01E0 0x0000 0x4 0x0 0x0030 0x01E0 0x0000 0x5 0x0 0x0030 0x01E0 0x03FC 0x16 0x1 0x0030 0x01E0 0x038C 0x7 0x0 0x0034 0x01E4 0x0000 0x0 0x0 0x0034 0x01E4 0x0000 0x1 0x0 0x0034 0x01E4 0x0000 0x2 0x0 0x0034 0x01E4 0x0000 0x3 0x0 0x0034 0x01E4 0x0000 0x4 0x0 0x0034 0x01E4 0x0000 0x5 0x0 0x0034 0x01E4 0x03F8 0x16 0x1 0x0034 0x01E4 0x0390 0x7 0x0 0x0038 0x01E8 0x0000 0x0 0x0 0x0038 0x01E8 0x0000 0x1 0x0 0x0038 0x01E8 0x0000 0x2 0x0 0x0038 0x01E8 0x0000 0x3 0x0 0x0038 0x01E8 0x0000 0x4 0x0 0x0038 0x01E8 0x0000 0x5 0x0 0x0038 0x01E8 0x0404 0x16 0x0 0x0038 0x01E8 0x0394 0x7 0x0 0x003C 0x01EC 0x0000 0x0 0x0 0x003C 0x01EC 0x0000 0x1 0x0 0x003C 0x01EC 0x0000 0x2 0x0 0x003C 0x01EC 0x0000 0x3 0x0 0x003C 0x01EC 0x0000 0x4 0x0 0x003C 0x01EC 0x0000 0x5 0x0 0x003C 0x01EC 0x0400 0x16 0x0 0x003C 0x01EC 0x0398 0x7 0x0 0x0040 0x01F0 0x0000 0x0 0x0 0x0040 0x01F0 0x0000 0x1 0x0 0x0040 0x01F0 0x0440 0x2 0x0 0x0040 0x01F0 0x0000 0x3 0x0 0x0040 0x01F0 0x0000 0x4 0x0 0x0040 0x01F0 0x0000 0x5 0x0 0x0040 0x01F0 0x0404 0x16 0x1 0x0040 0x01F0 0x0450 0x7 0x0 0x0044 0x01F4 0x0000 0x0 0x0 0x0044 0x01F4 0x0000 0x1 0x0 0x0044 0x01F4 0x0444 0x2 0x0 0x0044 0x01F4 0x0000 0x3 0x0 0x0044 0x01F4 0x0000 0x4 0x0 0x0044 0x01F4 0x0000 0x5 0x0 0x0044 0x01F4 0x0400 0x16 0x1 0x0044 0x01F4 0x039C 0x7 0x0 0x0048 0x01F8 0x0000 0x0 0x0 0x0048 0x01F8 0x041C 0x1 0x0 0x0048 0x01F8 0x0000 0x2 0x0 0x0048 0x01F8 0x0000 0x3 0x0 0x0048 0x01F8 0x0000 0x4 0x0 0x0048 0x01F8 0x0000 0x5 0x0 0x0048 0x01F8 0x0428 0x6 0x0 0x0048 0x01F8 0x03A0 0x7 0x0 0x004C 0x01FC 0x0000 0x0 0x0 0x004C 0x01FC 0x0418 0x1 0x0 0x004C 0x01FC 0x0000 0x2 0x0 0x004C 0x01FC 0x0000 0x3 0x0 0x004C 0x01FC 0x0000 0x4 0x0 0x004C 0x01FC 0x0000 0x5 0x0 0x004C 0x01FC 0x0424 0x6 0x0 0x004C 0x01FC 0x03A4 0x7 0x0 0x0050 0x0200 0x0000 0x0 0x0 0x0050 0x0200 0x0000 0x1 0x0 0x0050 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0x01A0 0x0350 0x0000 0x5 0x0 0x01A4 0x0354 0x0000 0x0 0x0 0x01A4 0x0354 0x0000 0x1 0x0 0x01A4 0x0354 0x0000 0x2 0x0 0x01A4 0x0354 0x0000 0x3 0x0 0x01A4 0x0354 0x0000 0x4 0x0 0x01A4 0x0354 0x0000 0x5 0x0 0x01A8 0x0358 0x0000 0x0 0x0 0x01A8 0x0358 0x0448 0x1 0x1 0x01A8 0x0358 0x0000 0x2 0x0 0x01A8 0x0358 0x0000 0x3 0x0 0x01A8 0x0358 0x0000 0x4 0x0 0x01A8 0x0358 0x0000 0x5 0x0 0x01AC 0x035C 0x0000 0x0 0x0 0x01AC 0x035C 0x0000 0x5 0x0 b/arch/arm/dts/imx93-u-boot.dtsi E>; 0x800000da deleted after upstream support ; Y_BURUNIN>; ; Y_BURUNIN>; "fsl,imx7d-usb", "fsl,imx27-usb"; IRQ_TYPE_LEVEL_HIGH>; NTROLLER_GATE>, >; "usb_wakeup"; IMX93_CLK_HSIO>; IMX93_CLK_SYS_PLL_PFD1_DIV2>; t;; "fsl,imx7d-usbmisc", "fsl,imx7d-usb", "fsl,imx27-usb"; IRQ_TYPE_LEVEL_HIGH>; NTROLLER_GATE>, >; "usb_wakeup"; IMX93_CLK_HSIO>; IMX93_CLK_SYS_PLL_PFD1_DIV2>; t;; "fsl,imx7d-usbmisc", ymphony-u-boot.dtsi b/arch/arm/dts/imx93-var-som-symphony-u-boot.dtsi -u-boot.dtsi -u-boot.dtsi

+/* + * The two nodes below won't be needed once support is added + * to the Linux kernel. + */ +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + hnp-disable; + srp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + /* * The two nodes below won't be needed once nxp,pca9451a * support is added to the Linux kernel. diff --git a/arch/arm/dts/imx93-var-som-symphony.dts b/arch/arm/dts/imx93-var-som-symphony.dts deleted file mode 100644 index 1bc61942716..00000000000 --- a/arch/arm/dts/imx93-var-som-symphony.dts +++ /dev/null @@ -1,323 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2021 NXP - * Copyright 2023 Variscite Ltd. - */ - -/dts-v1/; - -#include "imx93-var-som.dtsi" - -/{ - model = "Variscite VAR-SOM-MX93 on Symphony evaluation board"; - compatible = "variscite,var-som-mx93-symphony", - "variscite,var-som-mx93", "fsl,imx93"; - - aliases { - ethernet0 = &eqos; - ethernet1 = &fec; - }; - - chosen { - stdout-path = &lpuart1; - }; - - /* - * Needed only for Symphony <= v1.5 - */ - reg_fec_phy: regulator-fec-phy { - compatible = "regulator-fixed"; - regulator-name = "fec-phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-enable-ramp-delay = <20000>; - gpio = <&pca9534 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>; - off-on-delay-us = <20000>; - enable-active-high; - }; - - reg_vref_1v8: regulator-adc-vref { - compatible = "regulator-fixed"; - regulator-name = "vref_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ethosu_mem: ethosu-region@88000000 { - compatible = "shared-dma-pool"; - reusable; - reg = <0x0 0x88000000 0x0 0x8000000>; - }; - - vdev0vring0: vdev0vring0@87ee0000 { - reg = <0 0x87ee0000 0 0x8000>; - no-map; - }; - - vdev0vring1: vdev0vring1@87ee8000 { - reg = <0 0x87ee8000 0 0x8000>; - no-map; - }; - - vdev1vring0: vdev1vring0@87ef0000 { - reg = <0 0x87ef0000 0 0x8000>; - no-map; - }; - - vdev1vring1: vdev1vring1@87ef8000 { - reg = <0 0x87ef8000 0 0x8000>; - no-map; - }; - - rsc_table: rsc-table@2021f000 { - reg = <0 0x2021f000 0 0x1000>; - no-map; - }; - - vdevbuffer: vdevbuffer@87f00000 { - compatible = "shared-dma-pool"; - reg = <0 0x87f00000 0 0x100000>; - no-map; - }; - - ele_reserved: ele-reserved@87de0000 { - compatible = "shared-dma-pool"; - reg = <0 0x87de0000 0 0x100000>; - no-map; - }; - }; -}; - -/* Use external instead of internal RTC*/ -&bbnsm_rtc { - status = "disabled"; -}; - -&eqos { - mdio { - ethphy1: ethernet-phy@5 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <5>; - qca,disable-smarteee; - eee-broken-1000t; - reset-gpios = <&pca9534 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <10000>; - reset-deassert-us = <20000>; - vddio-supply = <&vddio1>; - - vddio1: vddio-regulator { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; -}; - -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii"; - phy-handle = <&ethphy1>; - phy-supply = <&reg_fec_phy>; - status = "okay"; -}; - -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&iomuxc { - pinctrl_fec: fecgrp { - fsl,pins = < - MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e - MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e - MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e - MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e - MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe - MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e - MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e - MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e - MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e - MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e - MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x5fe - MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX93_PAD_PDM_CLK__CAN1_TX 0x139e - MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e - >; - }; - - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e - MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c1_gpio: lpi2c1gpiogrp { - fsl,pins = < - MX93_PAD_I2C1_SCL__GPIO1_IO00 0x31e - MX93_PAD_I2C1_SDA__GPIO1_IO01 0x31e - >; - }; - - pinctrl_lpi2c5: lpi2c5grp { - fsl,pins = < - MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e - MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e - >; - }; - - pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { - fsl,pins = < - MX93_PAD_GPIO_IO23__GPIO2_IO23 0x31e - MX93_PAD_GPIO_IO22__GPIO2_IO22 0x31e - >; - }; - - pinctrl_pca9534: pca9534grp { - fsl,pins = < - MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX93_PAD_UART1_RXD__LPUART1_RX 0x31e - MX93_PAD_UART1_TXD__LPUART1_TX 0x31e - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { - fsl,pins = < - MX93_PAD_GPIO_IO18__GPIO2_IO18 0x31e - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e - >; - }; - - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e - >; - }; -}; - -&lpi2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "sleep", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c1>; - pinctrl-1 = <&pinctrl_lpi2c1_gpio>; - pinctrl-2 = <&pinctrl_lpi2c1_gpio>; - scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; - status = "okay"; - - /* DS1337 RTC module */ - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; -}; - -&lpi2c5 { - clock-frequency = <400000>; - pinctrl-names = "default", "sleep", "gpio"; - pinctrl-0 = <&pinctrl_lpi2c5>; - pinctrl-1 = <&pinctrl_lpi2c5_gpio>; - pinctrl-2 = <&pinctrl_lpi2c5_gpio>; - scl-gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; - status = "okay"; - - pca9534: gpio@20 { - compatible = "nxp,pca9534"; - reg = <0x20>; - gpio-controller; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pca9534>; - interrupt-parent = <&gpio3>; - interrupts = <26 IRQ_TYPE_EDGE_FALLING>; - #gpio-cells = <2>; - wakeup-source; - }; -}; - -/* Console */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; - clock-names = "ipg", "per"; - status = "okay"; -}; - -&usbotg1 { - dr_mode = "otg"; - hnp-disable; - srp-disable; - adp-disable; - disable-over-current; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - hnp-disable; - srp-disable; - adp-disable; - disable-over-current; - status = "okay"; -}; - -/* SD */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; - vmmc-supply = <&reg_usdhc2_vmmc>; - bus-width = <4>; - status = "okay"; - no-sdio; - no-mmc; -}; - -/* Watchdog */ -&wdog3 { - status = "okay"; -}; diff --git a/arch/arm/dts/imx93-var-som.dtsi b/arch/arm/dts/imx93-var-som.dtsi deleted file mode 100644 index 6c77b886666..00000000000 --- a/arch/arm/dts/imx93-var-som.dtsi +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 NXP - * Copyright 2023 Variscite Ltd. - */ - -/dts-v1/; - -#include "imx93.dtsi" - -/{ - model = "Variscite VAR-SOM-MX93 module"; - compatible = "variscite,var-som-mx93", "fsl,imx93"; - - mmc_pwrseq: mmc-pwrseq { - compatible = "mmc-pwrseq-simple"; - post-power-on-delay-ms = <100>; - power-off-delay-us = <10000>; - reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ - <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ - }; - - reg_eqos_phy: regulator-eqos-phy { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_eqos_phy>; - regulator-name = "eth_phy_pwr"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100000>; - regulator-always-on; - }; -}; - -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii"; - phy-handle = <&ethphy0>; - phy-supply = <&reg_eqos_phy>; - status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <1000000>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - eee-broken-1000t; - }; - }; -}; - -&iomuxc { - pinctrl_eqos: eqosgrp { - fsl,pins = < - MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e - MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e - MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e - MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e - MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e - MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e - MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe - MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e - MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e - MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e - MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e - MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e - MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe - MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e - >; - }; - - pinctrl_reg_eqos_phy: regeqosgrp { - fsl,pins = < - MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe - MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe - >; - }; -}; - -/* eMMC */ -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1>; - pinctrl-2 = <&pinctrl_usdhc1>; - bus-width = <8>; - non-removable; - status = "okay"; -}; diff --git a/arch/arm/dts/imx93.dtsi b/arch/arm/dts/imx93.dtsi deleted file mode 100644 index d6964714ea0..00000000000 --- a/arch/arm/dts/imx93.dtsi +++ /dev/null @@ -1,906 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright 2022 NXP - */ - -#include <dt-bindings/clock/imx93-clock.h> -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/power/fsl,imx93-power.h> -#include <dt-bindings/thermal/thermal.h> - -#include "imx93-pinfunc.h" - -/ { - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - i2c0 = &lpi2c1; - i2c1 = &lpi2c2; - i2c2 = &lpi2c3; - i2c3 = &lpi2c4; - i2c4 = &lpi2c5; - i2c5 = &lpi2c6; - i2c6 = &lpi2c7; - i2c7 = &lpi2c8; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - serial0 = &lpuart1; - serial1 = &lpuart2; - serial2 = &lpuart3; - serial3 = &lpuart4; - serial4 = &lpuart5; - serial5 = &lpuart6; - serial6 = &lpuart7; - serial7 = &lpuart8; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - A55_0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x0>; - enable-method = "psci"; - #cooling-cells = <2>; - }; - - A55_1: cpu@100 { - device_type = "cpu"; - compatible = "arm,cortex-a55"; - reg = <0x100>; - enable-method = "psci"; - #cooling-cells = <2>; - }; - - }; - - osc_32k: clock-osc-32k { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - clock-output-names = "osc_32k"; - }; - - osc_24m: clock-osc-24m { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "osc_24m"; - }; - - clk_ext1: clock-ext1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133000000>; - clock-output-names = "clk_ext1"; - }; - - pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - }; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; - clock-frequency = <24000000>; - arm,no-tick-in-suspend; - interrupt-parent = <&gic>; - }; - - gic: interrupt-controller@48000000 { - compatible = "arm,gic-v3"; - reg = <0 0x48000000 0 0x10000>, - <0 0x48040000 0 0xc0000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&gic>; - }; - - thermal-zones { - cpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_crit: cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - #phy-cells = <0>; - clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; - clock-names = "main_clk"; - }; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x80000000>, - <0x28000000 0x0 0x28000000 0x10000000>; - - aips1: bus@44000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x44000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - anomix_ns_gpr: syscon@44210000 { - compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; - reg = <0x44210000 0x1000>; - }; - - mu1: mailbox@44230000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x44230000 0x10000>; - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_MU1_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - - system_counter: timer@44290000 { - compatible = "nxp,sysctr-timer"; - reg = <0x44290000 0x30000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc_24m>; - clock-names = "per"; - nxp,no-divider; - }; - - tpm1: pwm@44310000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x44310000 0x1000>; - clocks = <&clk IMX93_CLK_TPM1_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm2: pwm@44320000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x44320000 0x10000>; - clocks = <&clk IMX93_CLK_TPM2_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - lpi2c1: i2c@44340000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x44340000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C1_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpi2c2: i2c@44350000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x44350000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C2_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi1: spi@44360000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x44360000 0x10000>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI1_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi2: spi@44370000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x44370000 0x10000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI2_GATE>, - <&clk IMX93_CLK_BUS_AON>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpuart1: serial@44380000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x44380000 0x1000>; - interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - lpuart2: serial@44390000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x44390000 0x1000>; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART2_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - flexcan1: can@443a0000 { - compatible = "fsl,imx93-flexcan"; - reg = <0x443a0000 0x10000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_AON>, - <&clk IMX93_CLK_CAN1_GATE>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX93_CLK_CAN1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - status = "disabled"; - }; - - iomuxc: pinctrl@443c0000 { - compatible = "fsl,imx93-iomuxc"; - reg = <0x443c0000 0x10000>; - status = "okay"; - }; - - bbnsm: bbnsm@44440000 { - compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; - reg = <0x44440000 0x10000>; - - bbnsm_rtc: rtc { - compatible = "nxp,imx93-bbnsm-rtc"; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - }; - - bbnsm_pwrkey: pwrkey { - compatible = "nxp,imx93-bbnsm-pwrkey"; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - linux,code = <KEY_POWER>; - }; - }; - - clk: clock-controller@44450000 { - compatible = "fsl,imx93-ccm"; - reg = <0x44450000 0x10000>; - #clock-cells = <1>; - clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; - clock-names = "osc_32k", "osc_24m", "clk_ext1"; - status = "okay"; - }; - - src: system-controller@44460000 { - compatible = "fsl,imx93-src", "syscon"; - reg = <0x44460000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mediamix: power-domain@44462400 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44462400 0x400>, <0x44465800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_MEDIA_AXI>, - <&clk IMX93_CLK_MEDIA_APB>; - }; - - mlmix: power-domain@44461800 { - compatible = "fsl,imx93-src-slice"; - reg = <0x44461800 0x400>, <0x44464800 0x400>; - #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_ML_APB>, - <&clk IMX93_CLK_ML>; - }; - }; - - anatop: anatop@44480000 { - compatible = "fsl,imx93-anatop", "syscon"; - reg = <0x44480000 0x10000>; - }; - - tmu: tmu@44482000 { - compatible = "fsl,imx93-tmu"; - reg = <0x44482000 0x1000>; - clocks = <&clk IMX93_CLK_TMC_GATE>; - little-endian; - fsl,tmu-calibration = <0x0000000e 0x800000da - 0x00000029 0x800000e9 - 0x00000056 0x80000102 - 0x000000a2 0x8000012a - 0x00000116 0x80000166 - 0x00000195 0x800001a7 - 0x000001b2 0x800001b6>; - #thermal-sensor-cells = <1>; - }; - - adc1: adc@44530000 { - compatible = "nxp,imx93-adc"; - reg = <0x44530000 0x10000>; - interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_ADC1_GATE>; - clock-names = "ipg"; - #io-channel-cells = <1>; - status = "disabled"; - }; - }; - - aips2: bus@42000000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x42000000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - wakeupmix_gpr: syscon@42420000 { - compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; - reg = <0x42420000 0x1000>; - }; - - mu2: mailbox@42440000 { - compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu"; - reg = <0x42440000 0x10000>; - interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_MU2_B_GATE>; - #mbox-cells = <2>; - status = "disabled"; - }; - - wdog3: wdog@42490000 { - compatible = "fsl,imx93-wdt"; - reg = <0x42490000 0x10000>; - interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_WDOG3_GATE>; - timeout-sec = <40>; - }; - - tpm3: pwm@424e0000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x424e0000 0x1000>; - clocks = <&clk IMX93_CLK_TPM3_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm4: pwm@424f0000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x424f0000 0x10000>; - clocks = <&clk IMX93_CLK_TPM4_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm5: pwm@42500000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x42500000 0x10000>; - clocks = <&clk IMX93_CLK_TPM5_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - tpm6: pwm@42510000 { - compatible = "fsl,imx7ulp-pwm"; - reg = <0x42510000 0x10000>; - clocks = <&clk IMX93_CLK_TPM6_GATE>; - #pwm-cells = <3>; - status = "disabled"; - }; - - lpi2c3: i2c@42530000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x42530000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C3_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpi2c4: i2c@42540000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x42540000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C4_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi3: spi@42550000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42550000 0x10000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI3_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi4: spi@42560000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42560000 0x10000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI4_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpuart3: serial@42570000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42570000 0x1000>; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART3_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart4: serial@42580000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42580000 0x1000>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART4_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart5: serial@42590000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42590000 0x1000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART5_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart6: serial@425a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x425a0000 0x1000>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART6_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - flexcan2: can@425b0000 { - compatible = "fsl,imx93-flexcan"; - reg = <0x425b0000 0x10000>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_CAN2_GATE>; - clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX93_CLK_CAN2>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - status = "disabled"; - }; - - flexspi1: spi@425e0000 { - compatible = "nxp,imx8mm-fspi"; - reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, - <&clk IMX93_CLK_FLEXSPI1_GATE>; - clock-names = "fspi_en", "fspi"; - assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; - status = "disabled"; - }; - - lpuart7: serial@42690000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x42690000 0x1000>; - interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART7_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpuart8: serial@426a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; - reg = <0x426a0000 0x1000>; - interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPUART8_GATE>; - clock-names = "ipg"; - status = "disabled"; - }; - - lpi2c5: i2c@426b0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426b0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C5_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpi2c6: i2c@426c0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426c0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C6_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpi2c7: i2c@426d0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426d0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C7_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpi2c8: i2c@426e0000 { - compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x426e0000 0x10000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPI2C8_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi5: spi@426f0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x426f0000 0x10000>; - interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI5_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi6: spi@42700000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42700000 0x10000>; - interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI6_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi7: spi@42710000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42710000 0x10000>; - interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI7_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - lpspi8: spi@42720000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; - reg = <0x42720000 0x10000>; - interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_LPSPI8_GATE>, - <&clk IMX93_CLK_BUS_WAKEUP>; - clock-names = "per", "ipg"; - status = "disabled"; - }; - - }; - - aips3: bus@42800000 { - compatible = "fsl,aips-bus", "simple-bus"; - reg = <0x42800000 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usdhc1: mmc@42850000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x42850000 0x10000>; - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC1_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <8>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - usdhc2: mmc@42860000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x42860000 0x10000>; - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC2_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - - eqos: ethernet@428a0000 { - compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; - reg = <0x428a0000 0x10000>; - interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq", "eth_wake_irq"; - clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_QOS_GATE>, - <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>, - <&clk IMX93_CLK_ENET_QOS_GATE>; - clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, - <&clk IMX93_CLK_ENET>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; - assigned-clock-rates = <100000000>, <250000000>; - intf_mode = <&wakeupmix_gpr 0x28>; - snps,clk-csr = <0>; - status = "disabled"; - }; - - fec: ethernet@42890000 { - compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; - reg = <0x42890000 0x10000>; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_ENET1_GATE>, - <&clk IMX93_CLK_ENET1_GATE>, - <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - clock-names = "ipg", "ahb", "ptp", - "enet_clk_ref", "enet_out"; - assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, - <&clk IMX93_CLK_ENET_REF>, - <&clk IMX93_CLK_ENET_REF_PHY>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, - <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <100000000>, <250000000>, <50000000>; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; - status = "disabled"; - }; - - usdhc3: mmc@428b0000 { - compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; - reg = <0x428b0000 0x10000>; - interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_BUS_WAKEUP>, - <&clk IMX93_CLK_WAKEUP_AXI>, - <&clk IMX93_CLK_USDHC3_GATE>; - clock-names = "ipg", "ahb", "per"; - bus-width = <4>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; - }; - - gpio2: gpio@43810080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43810080 0x1000>, <0x43810040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO2_GATE>, - <&clk IMX93_CLK_GPIO2_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 4 30>; - }; - - gpio3: gpio@43820080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43820080 0x1000>, <0x43820040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO3_GATE>, - <&clk IMX93_CLK_GPIO3_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, - <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; - }; - - gpio4: gpio@43830080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43830080 0x1000>, <0x43830040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO4_GATE>, - <&clk IMX93_CLK_GPIO4_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; - }; - - gpio1: gpio@47400080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x47400080 0x1000>, <0x47400040 0x40>; - gpio-controller; - #gpio-cells = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&clk IMX93_CLK_GPIO1_GATE>, - <&clk IMX93_CLK_GPIO1_GATE>; - clock-names = "gpio", "port"; - gpio-ranges = <&iomuxc 0 92 16>; - }; - - s4muap: mailbox@47520000 { - compatible = "fsl,imx93-mu-s4"; - reg = <0x47520000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "tx", "rx"; - #mbox-cells = <2>; - }; - - media_blk_ctrl: system-controller@4ac10000 { - compatible = "fsl,imx93-media-blk-ctrl", "syscon"; - reg = <0x4ac10000 0x10000>; - power-domains = <&mediamix>; - clocks = <&clk IMX93_CLK_MEDIA_APB>, - <&clk IMX93_CLK_MEDIA_AXI>, - <&clk IMX93_CLK_NIC_MEDIA_GATE>, - <&clk IMX93_CLK_MEDIA_DISP_PIX>, - <&clk IMX93_CLK_CAM_PIX>, - <&clk IMX93_CLK_PXP_GATE>, - <&clk IMX93_CLK_LCDIF_GATE>, - <&clk IMX93_CLK_ISI_GATE>, - <&clk IMX93_CLK_MIPI_CSI_GATE>, - <&clk IMX93_CLK_MIPI_DSI_GATE>; - clock-names = "apb", "axi", "nic", "disp", "cam", - "pxp", "lcdif", "isi", "csi", "dsi"; - #power-domain-cells = <1>; - status = "disabled"; - }; - - usbotg1: usb@4c100000 { - compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x4c100000 0x200>; - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, - <&clk IMX93_CLK_HSIO_32K_GATE>; - clock-names = "usb_ctrl_root_clk", "usb_wakeup"; - assigned-clocks = <&clk IMX93_CLK_HSIO>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <133000000>; - phys = <&usbphynop1>; - fsl,usbmisc = <&usbmisc1 0>; - status = "disabled"; - }; - - usbmisc1: usbmisc@4c100200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x4c100200 0x200>; - #index-cells = <1>; - }; - - usbotg2: usb@4c200000 { - compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; - reg = <0x4c200000 0x200>; - interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, - <&clk IMX93_CLK_HSIO_32K_GATE>; - clock-names = "usb_ctrl_root_clk", "usb_wakeup"; - assigned-clocks = <&clk IMX93_CLK_HSIO>; - assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; - assigned-clock-rates = <133000000>; - phys = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - status = "disabled"; - }; - - usbmisc2: usbmisc@4c200200 { - compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", - "fsl,imx6q-usbmisc"; - reg = <0x4c200200 0x200>; - #index-cells = <1>; - }; - }; -}; diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index b79485f1f75..ea42c4980ed 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -15,6 +15,7 @@ config IMX9 select BINMAN select HAS_CAAM select ROM_UNIFIED_SECTIONS + imply OF_UPSTREAM

config IMX93 bool diff --git a/configs/imx93-phyboard-segin_defconfig b/configs/imx93-phyboard-segin_defconfig index 54215c51c08..2db19d6f1cd 100644 --- a/configs/imx93-phyboard-segin_defconfig +++ b/configs/imx93-phyboard-segin_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x700000 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx93-phyboard-segin" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-phyboard-segin" CONFIG_SPL_TEXT_BASE=0x2049A000 CONFIG_AHAB_BOOT=y CONFIG_TARGET_PHYCORE_IMX93=y diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 63613477c7f..a671de7ca40 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x700000 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-11x11-evk" CONFIG_SPL_TEXT_BASE=0x2049A000 CONFIG_TARGET_IMX93_11X11_EVK=y CONFIG_SYS_MONITOR_LEN=524288 diff --git a/configs/imx93_11x11_evk_ld_defconfig b/configs/imx93_11x11_evk_ld_defconfig index 4e3bbdd0cf5..4e1f162e35a 100644 --- a/configs/imx93_11x11_evk_ld_defconfig +++ b/configs/imx93_11x11_evk_ld_defconfig @@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x400000 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx93-11x11-evk" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-11x11-evk" CONFIG_SPL_TEXT_BASE=0x2049A000 CONFIG_IMX9_LOW_DRIVE_MODE=y CONFIG_TARGET_IMX93_11X11_EVK=y diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig index 996cad4854a..15896a68efe 100644 --- a/configs/imx93_var_som_defconfig +++ b/configs/imx93_var_som_defconfig @@ -10,7 +10,7 @@ CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x700000 CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="imx93-var-som-symphony" +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx93-var-som-symphony" CONFIG_SPL_TEXT_BASE=0x2049A000 CONFIG_AHAB_BOOT=y CONFIG_TARGET_IMX93_VAR_SOM=y diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h deleted file mode 100644 index 35a1f62053a..00000000000 --- a/include/dt-bindings/clock/imx93-clock.h +++ /dev/null @@ -1,208 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * Copyright 2022 NXP - */ - -#ifndef __DT_BINDINGS_CLOCK_IMX93_CLK_H -#define __DT_BINDINGS_CLOCK_IMX93_CLK_H - -#define IMX93_CLK_DUMMY 0 -#define IMX93_CLK_24M 1 -#define IMX93_CLK_EXT1 2 -#define IMX93_CLK_SYS_PLL_PFD0 3 -#define IMX93_CLK_SYS_PLL_PFD0_DIV2 4 -#define IMX93_CLK_SYS_PLL_PFD1 5 -#define IMX93_CLK_SYS_PLL_PFD1_DIV2 6 -#define IMX93_CLK_SYS_PLL_PFD2 7 -#define IMX93_CLK_SYS_PLL_PFD2_DIV2 8 -#define IMX93_CLK_AUDIO_PLL 9 -#define IMX93_CLK_VIDEO_PLL 10 -#define IMX93_CLK_A55_PERIPH 11 -#define IMX93_CLK_A55_MTR_BUS 12 -#define IMX93_CLK_A55 13 -#define IMX93_CLK_M33 14 -#define IMX93_CLK_BUS_WAKEUP 15 -#define IMX93_CLK_BUS_AON 16 -#define IMX93_CLK_WAKEUP_AXI 17 -#define IMX93_CLK_SWO_TRACE 18 -#define IMX93_CLK_M33_SYSTICK 19 -#define IMX93_CLK_FLEXIO1 20 -#define IMX93_CLK_FLEXIO2 21 -#define IMX93_CLK_LPTMR1 24 -#define IMX93_CLK_LPTMR2 25 -#define IMX93_CLK_TPM2 27 -#define IMX93_CLK_TPM4 29 -#define IMX93_CLK_TPM5 30 -#define IMX93_CLK_TPM6 31 -#define IMX93_CLK_FLEXSPI1 32 -#define IMX93_CLK_CAN1 33 -#define IMX93_CLK_CAN2 34 -#define IMX93_CLK_LPUART1 35 -#define IMX93_CLK_LPUART2 36 -#define IMX93_CLK_LPUART3 37 -#define IMX93_CLK_LPUART4 38 -#define IMX93_CLK_LPUART5 39 -#define IMX93_CLK_LPUART6 40 -#define IMX93_CLK_LPUART7 41 -#define IMX93_CLK_LPUART8 42 -#define IMX93_CLK_LPI2C1 43 -#define IMX93_CLK_LPI2C2 44 -#define IMX93_CLK_LPI2C3 45 -#define IMX93_CLK_LPI2C4 46 -#define IMX93_CLK_LPI2C5 47 -#define IMX93_CLK_LPI2C6 48 -#define IMX93_CLK_LPI2C7 49 -#define IMX93_CLK_LPI2C8 50 -#define IMX93_CLK_LPSPI1 51 -#define IMX93_CLK_LPSPI2 52 -#define IMX93_CLK_LPSPI3 53 -#define IMX93_CLK_LPSPI4 54 -#define IMX93_CLK_LPSPI5 55 -#define IMX93_CLK_LPSPI6 56 -#define IMX93_CLK_LPSPI7 57 -#define IMX93_CLK_LPSPI8 58 -#define IMX93_CLK_I3C1 59 -#define IMX93_CLK_I3C2 60 -#define IMX93_CLK_USDHC1 61 -#define IMX93_CLK_USDHC2 62 -#define IMX93_CLK_USDHC3 63 -#define IMX93_CLK_SAI1 64 -#define IMX93_CLK_SAI2 65 -#define IMX93_CLK_SAI3 66 -#define IMX93_CLK_CCM_CKO1 67 -#define IMX93_CLK_CCM_CKO2 68 -#define IMX93_CLK_CCM_CKO3 69 -#define IMX93_CLK_CCM_CKO4 70 -#define IMX93_CLK_HSIO 71 -#define IMX93_CLK_HSIO_USB_TEST_60M 72 -#define IMX93_CLK_HSIO_ACSCAN_80M 73 -#define IMX93_CLK_HSIO_ACSCAN_480M 74 -#define IMX93_CLK_ML_APB 75 -#define IMX93_CLK_ML 76 -#define IMX93_CLK_MEDIA_AXI 77 -#define IMX93_CLK_MEDIA_APB 78 -#define IMX93_CLK_MEDIA_LDB 79 -#define IMX93_CLK_MEDIA_DISP_PIX 80 -#define IMX93_CLK_CAM_PIX 81 -#define IMX93_CLK_MIPI_TEST_BYTE 82 -#define IMX93_CLK_MIPI_PHY_CFG 83 -#define IMX93_CLK_ADC 84 -#define IMX93_CLK_PDM 85 -#define IMX93_CLK_TSTMR1 86 -#define IMX93_CLK_TSTMR2 87 -#define IMX93_CLK_MQS1 88 -#define IMX93_CLK_MQS2 89 -#define IMX93_CLK_AUDIO_XCVR 90 -#define IMX93_CLK_SPDIF 91 -#define IMX93_CLK_ENET 92 -#define IMX93_CLK_ENET_TIMER1 93 -#define IMX93_CLK_ENET_TIMER2 94 -#define IMX93_CLK_ENET_REF 95 -#define IMX93_CLK_ENET_REF_PHY 96 -#define IMX93_CLK_I3C1_SLOW 97 -#define IMX93_CLK_I3C2_SLOW 98 -#define IMX93_CLK_USB_PHY_BURUNIN 99 -#define IMX93_CLK_PAL_CAME_SCAN 100 -#define IMX93_CLK_A55_GATE 101 -#define IMX93_CLK_CM33_GATE 102 -#define IMX93_CLK_ADC1_GATE 103 -#define IMX93_CLK_WDOG1_GATE 104 -#define IMX93_CLK_WDOG2_GATE 105 -#define IMX93_CLK_WDOG3_GATE 106 -#define IMX93_CLK_WDOG4_GATE 107 -#define IMX93_CLK_WDOG5_GATE 108 -#define IMX93_CLK_SEMA1_GATE 109 -#define IMX93_CLK_SEMA2_GATE 110 -#define IMX93_CLK_MU_A_GATE 111 -#define IMX93_CLK_MU_B_GATE 112 -#define IMX93_CLK_EDMA1_GATE 113 -#define IMX93_CLK_EDMA2_GATE 114 -#define IMX93_CLK_FLEXSPI1_GATE 115 -#define IMX93_CLK_GPIO1_GATE 116 -#define IMX93_CLK_GPIO2_GATE 117 -#define IMX93_CLK_GPIO3_GATE 118 -#define IMX93_CLK_GPIO4_GATE 119 -#define IMX93_CLK_FLEXIO1_GATE 120 -#define IMX93_CLK_FLEXIO2_GATE 121 -#define IMX93_CLK_LPIT1_GATE 122 -#define IMX93_CLK_LPIT2_GATE 123 -#define IMX93_CLK_LPTMR1_GATE 124 -#define IMX93_CLK_LPTMR2_GATE 125 -#define IMX93_CLK_TPM1_GATE 126 -#define IMX93_CLK_TPM2_GATE 127 -#define IMX93_CLK_TPM3_GATE 128 -#define IMX93_CLK_TPM4_GATE 129 -#define IMX93_CLK_TPM5_GATE 130 -#define IMX93_CLK_TPM6_GATE 131 -#define IMX93_CLK_CAN1_GATE 132 -#define IMX93_CLK_CAN2_GATE 133 -#define IMX93_CLK_LPUART1_GATE 134 -#define IMX93_CLK_LPUART2_GATE 135 -#define IMX93_CLK_LPUART3_GATE 136 -#define IMX93_CLK_LPUART4_GATE 137 -#define IMX93_CLK_LPUART5_GATE 138 -#define IMX93_CLK_LPUART6_GATE 139 -#define IMX93_CLK_LPUART7_GATE 140 -#define IMX93_CLK_LPUART8_GATE 141 -#define IMX93_CLK_LPI2C1_GATE 142 -#define IMX93_CLK_LPI2C2_GATE 143 -#define IMX93_CLK_LPI2C3_GATE 144 -#define IMX93_CLK_LPI2C4_GATE 145 -#define IMX93_CLK_LPI2C5_GATE 146 -#define IMX93_CLK_LPI2C6_GATE 147 -#define IMX93_CLK_LPI2C7_GATE 148 -#define IMX93_CLK_LPI2C8_GATE 149 -#define IMX93_CLK_LPSPI1_GATE 150 -#define IMX93_CLK_LPSPI2_GATE 151 -#define IMX93_CLK_LPSPI3_GATE 152 -#define IMX93_CLK_LPSPI4_GATE 153 -#define IMX93_CLK_LPSPI5_GATE 154 -#define IMX93_CLK_LPSPI6_GATE 155 -#define IMX93_CLK_LPSPI7_GATE 156 -#define IMX93_CLK_LPSPI8_GATE 157 -#define IMX93_CLK_I3C1_GATE 158 -#define IMX93_CLK_I3C2_GATE 159 -#define IMX93_CLK_USDHC1_GATE 160 -#define IMX93_CLK_USDHC2_GATE 161 -#define IMX93_CLK_USDHC3_GATE 162 -#define IMX93_CLK_SAI1_GATE 163 -#define IMX93_CLK_SAI2_GATE 164 -#define IMX93_CLK_SAI3_GATE 165 -#define IMX93_CLK_MIPI_CSI_GATE 166 -#define IMX93_CLK_MIPI_DSI_GATE 167 -#define IMX93_CLK_LVDS_GATE 168 -#define IMX93_CLK_LCDIF_GATE 169 -#define IMX93_CLK_PXP_GATE 170 -#define IMX93_CLK_ISI_GATE 171 -#define IMX93_CLK_NIC_MEDIA_GATE 172 -#define IMX93_CLK_USB_CONTROLLER_GATE 173 -#define IMX93_CLK_USB_TEST_60M_GATE 174 -#define IMX93_CLK_HSIO_TROUT_24M_GATE 175 -#define IMX93_CLK_PDM_GATE 176 -#define IMX93_CLK_MQS1_GATE 177 -#define IMX93_CLK_MQS2_GATE 178 -#define IMX93_CLK_AUD_XCVR_GATE 179 -#define IMX93_CLK_SPDIF_GATE 180 -#define IMX93_CLK_HSIO_32K_GATE 181 -#define IMX93_CLK_ENET1_GATE 182 -#define IMX93_CLK_ENET_QOS_GATE 183 -#define IMX93_CLK_SYS_CNT_GATE 184 -#define IMX93_CLK_TSTMR1_GATE 185 -#define IMX93_CLK_TSTMR2_GATE 186 -#define IMX93_CLK_TMC_GATE 187 -#define IMX93_CLK_PMRO_GATE 188 -#define IMX93_CLK_32K 189 -#define IMX93_CLK_SAI1_IPG 190 -#define IMX93_CLK_SAI2_IPG 191 -#define IMX93_CLK_SAI3_IPG 192 -#define IMX93_CLK_MU1_A_GATE 193 -#define IMX93_CLK_MU1_B_GATE 194 -#define IMX93_CLK_MU2_A_GATE 195 -#define IMX93_CLK_MU2_B_GATE 196 -#define IMX93_CLK_NIC_AXI 197 -#define IMX93_CLK_ARM_PLL 198 -#define IMX93_CLK_A55_SEL 199 -#define IMX93_CLK_A55_CORE 200 -#define IMX93_CLK_END 201 - -#endif diff --git a/include/dt-bindings/power/fsl,imx93-power.h b/include/dt-bindings/power/fsl,imx93-power.h deleted file mode 100644 index 17f9f015bf7..00000000000 --- a/include/dt-bindings/power/fsl,imx93-power.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright 2022 NXP - */ - -#ifndef __DT_BINDINGS_IMX93_POWER_H__ -#define __DT_BINDINGS_IMX93_POWER_H__ - -#define IMX93_MEDIABLK_PD_MIPI_DSI 0 -#define IMX93_MEDIABLK_PD_MIPI_CSI 1 -#define IMX93_MEDIABLK_PD_PXP 2 -#define IMX93_MEDIABLK_PD_LCDIF 3 -#define IMX93_MEDIABLK_PD_ISI 4 - -#endif

-- 2.35.3

Mathieu Othacehe

2:43 p.m.

Hello,

...

Mathieu: please help test the boards you maintain when you have time.

I have tried both imx93_var_som and imx93-phyboard-segin configurations. Compilation works but I only get garbage on the UART on those two different boards.

I will try to conduct further investigations later on, but the booting test is KO here.

Thanks,

Mathieu

Peng Fan

7 Apr 7 Apr

12:26 p.m.

Any comments?

Thanks, Peng.

...

Subject: [PATCH v4 0/5] imx93: Conver to OF_UPSTREAM

A few nodes were added to soc and board u-boot.dtsi(lpi2c, usbotg), those nodes could be dropped after upstream linux supports them.

To support OF_UPSTREAM, a few driver changes are included. For TMU, still use U-Boot node, I will prepare a kernel update, then back to U- Boot support.

Mathieu: please help test the boards you maintain when you have time.

Thanks, Peng.

To: Sébastien Szymanski sebastien.szymanski@armadeus.com To: Stefano Babic sbabic@denx.de To: Fabio Estevam festevam@gmail.com To: "NXP i.MX U-Boot Team" uboot-imx@nxp.com To: Mathieu Othacehe m.othacehe@gmail.com Cc: u-boot@lists.denx.de Signed-off-by: Peng Fan peng.fan@nxp.com

Changes in v4:

Convert all i.MX93 boards

Link to v3: https://lore.kernel.org/r/20240328-imx93-of-v3-0-

4e7f341ed7ea@nxp.com

Changes in v3:

Update patch 5, to drop the imx8mp-evk changes which are wrongly included

Link to v2: https://lore.kernel.org/r/20240328-imx93-of-v2-0-

909f5d37da87@nxp.com

Changes in v2:

Add a new patch to sync clock header to avoid breaking

Drop the Makefile change which change including order

Link to v1: https://lore.kernel.org/r/20240327-imx93-of-v1-0-

afab6b31422a@nxp.com

Peng Fan (5): gpio: imx_rgpio2p: support one address serial: lpuart: use ipg clk for i.MX7ULP cpu: drop imx9_cpu clk: imx93: fix anatop base imx93: convert to OF_UPSTREAM

arch/arm/dts/Makefile | 5 - arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 119 ++++ arch/arm/dts/imx93-11x11-evk.dts | 322 --------- arch/arm/dts/imx93-phyboard-segin.dts | 117 --- arch/arm/dts/imx93-phycore-som.dtsi | 126 ---- arch/arm/dts/imx93-pinfunc.h | 623 ---------------- arch/arm/dts/imx93-u-boot.dtsi | 80 +++ arch/arm/dts/imx93-var-som-symphony-u-boot.dtsi | 22 + arch/arm/dts/imx93-var-som-symphony.dts | 323 --------- arch/arm/dts/imx93-var-som.dtsi | 111 --- arch/arm/dts/imx93.dtsi | 906 ------------------------ arch/arm/mach-imx/imx9/Kconfig | 1 + configs/imx93-phyboard-segin_defconfig | 2 +- configs/imx93_11x11_evk_defconfig | 2 +- configs/imx93_11x11_evk_ld_defconfig | 2 +- configs/imx93_var_som_defconfig | 2 +- drivers/clk/imx/clk-imx93.c | 2 +- drivers/cpu/imx9_cpu.c | 224 ------ drivers/gpio/imx_rgpio2p.c | 42 +- drivers/serial/serial_lpuart.c | 9 +- include/dt-bindings/clock/imx93-clock.h | 208 ------ include/dt-bindings/power/fsl,imx93-power.h | 15 - 22 files changed, 273 insertions(+), 2990 deletions(-)

base-commit: 280f34ba7d68bb50c0b8eaa040322c1f3b37d46e change-id: 20240328-imx93-of-v2-f879efef737d

Best regards,

Peng Fan peng.fan@nxp.com

Mathieu Othacehe

12:29 p.m.

...

Any comments?

Yes, see: https://lists.denx.de/pipermail/u-boot/2024-March/549531.html

Thanks,

Mathieu

Peng Fan

12:35 p.m.

Hi Mathieu,

...

Subject: Re: [PATCH v4 0/5] imx93: Conver to OF_UPSTREAM

...
Any comments?

Yes, see:

Sorry, I missed your comment.

...

From my test just now, log below. For your uart not work proper, I think it is

the uart clk not setup

U-Boot SPL 2024.04-rc5-00388-g351988e2dce (Apr 07 2024 - 19:29:56 +0800) SOC: 0xa1009300 LC: 0x2040010 M33 prepare ok Normal Boot Trying to boot from BOOTROM Boot Stage: Primary boot image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x49800 by ROM_API NOTICE: BL31: v2.8(release):lf-6.6.3-1.0.0-10-gf12d90141 NOTICE: BL31: Built : 09:34:44, Mar 27 2024

U-Boot 2024.04-rc5-00388-g351988e2dce (Apr 07 2024 - 19:29:56 +0800)

Reset Status: POR

Could not read CPU frequency: -2 CPU: NXP i.MX93(52) Rev1.1 A55 at 0 MHz CPU: Industrial temperature grade (-40C to 105C) at 26C

Model: NXP i.MX93 11X11 EVK board DRAM: 2 GiB Core: 188 devices, 24 uclasses, devicetree: separate WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment

In: serial@44380000 Out: serial@44380000 Err: serial@44380000 switch to partitions #0, OK mmc1 is current device Net: Warning: ethernet@428a0000 (eth1) using random MAC address - 6a:c2:96:d2:68:a6 eth0: ethernet@42890000 [PRIME], eth1: ethernet@428a0000 Hit any key to stop autoboot: 0

I see you have: &lpuart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; clock-names = "ipg", "per"; status = "okay"; };

Could you please help give a look on your uart settings which not work with: https://lore.kernel.org/all/20240328-imx93-of-v2-v4-2-338d15a65c36@nxp.com/

Thanks, Peng.

...

https://lists.d/ enx.de%2Fpipermail%2Fu-boot%2F2024- March%2F549531.html&data=05%7C02%7Cpeng.fan%40nxp.com%7C46ad4 24ef2cb4c09f8b908dc56edad0a%7C686ea1d3bc2b4c6fa92cd99c5c301635% 7C0%7C0%7C638480826025692986%7CUnknown%7CTWFpbGZsb3d8eyJWI joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C 0%7C%7C%7C&sdata=9oXIZF8Ihp1OfaDx3C%2Bcq9nstWJVhN8u3U7xQAhX2 2o%3D&reserved=0

Thanks,

Mathieu

Peng Fan

1:48 p.m.

Hi Mathieu,

...

Subject: RE: [PATCH v4 0/5] imx93: Conver to OF_UPSTREAM

Hi Mathieu,

...
Subject: Re: [PATCH v4 0/5] imx93: Conver to OF_UPSTREAM

...
Any comments?

Yes, see:

Sorry, I missed your comment.

Could you please help try this on top of this patchset? Seems this is the only point I could think of, that would impact uart.

diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 653ff99e67b..891352293f9 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -486,19 +486,22 @@ static int lpuart_serial_pending(struct udevice *dev, bool input) static int lpuart_serial_probe(struct udevice *dev) { #if CONFIG_IS_ENABLED(CLK) + struct lpuart_serial_plat *plat = dev_get_plat(dev); struct clk per_clk; struct clk ipg_clk; int ret;

- ret = clk_get_by_name(dev, "per", &per_clk); - if (!ret) { - ret = clk_enable(&per_clk); - if (ret) { - dev_err(dev, "Failed to enable per clk: %d\n", ret); - return ret; + if (plat->devtype != DEV_MX7ULP) { + ret = clk_get_by_name(dev, "per", &per_clk); + if (!ret) { + ret = clk_enable(&per_clk); + if (ret) { + dev_err(dev, "Failed to enable per clk: %d\n", ret); + return ret; + } + } else { + debug("%s: Failed to get per clk: %d\n", __func__, ret); } - } else { - debug("%s: Failed to get per clk: %d\n", __func__, ret); }

ret = clk_get_by_name(dev, "ipg", &ipg_clk);

Thanks, Peng.

...

From my test just now, log below. For your uart not work proper, I think it is the uart clk not setup

U-Boot SPL 2024.04-rc5-00388-g351988e2dce (Apr 07 2024 - 19:29:56 +0800) SOC: 0xa1009300 LC: 0x2040010 M33 prepare ok Normal Boot Trying to boot from BOOTROM Boot Stage: Primary boot image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x49800 by ROM_API NOTICE: BL31: v2.8(release):lf-6.6.3-1.0.0-10-gf12d90141 NOTICE: BL31: Built : 09:34:44, Mar 27 2024

U-Boot 2024.04-rc5-00388-g351988e2dce (Apr 07 2024 - 19:29:56 +0800)

Reset Status: POR

Could not read CPU frequency: -2 CPU: NXP i.MX93(52) Rev1.1 A55 at 0 MHz CPU: Industrial temperature grade (-40C to 105C) at 26C

Model: NXP i.MX93 11X11 EVK board DRAM: 2 GiB Core: 188 devices, 24 uclasses, devicetree: separate WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment

In: serial@44380000 Out: serial@44380000 Err: serial@44380000 switch to partitions #0, OK mmc1 is current device Net: Warning: ethernet@428a0000 (eth1) using random MAC address - 6a:c2:96:d2:68:a6 eth0: ethernet@42890000 [PRIME], eth1: ethernet@428a0000 Hit any key to stop autoboot: 0

I see you have: &lpuart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; clocks = <&clk IMX93_CLK_LPUART1_GATE>, <&clk IMX93_CLK_LPUART1_GATE>; clock-names = "ipg", "per"; status = "okay"; };

Could you please help give a look on your uart settings which not work with: https://lore.kernel.org/all/20240328-imx93-of-v2-v4-2- 338d15a65c36@nxp.com/

Thanks, Peng.

...
https://lists.d/ enx.de%2Fpipermail%2Fu-boot%2F2024-

March%2F549531.html&data=05%7C02%7Cpeng.fan%40nxp.com%7C46ad4

...
24ef2cb4c09f8b908dc56edad0a%7C686ea1d3bc2b4c6fa92cd99c5c301635%

7C0%7C0%7C638480826025692986%7CUnknown%7CTWFpbGZsb3d8eyJWI

...
joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C

...
0%7C%7C%7C&sdata=9oXIZF8Ihp1OfaDx3C%2Bcq9nstWJVhN8u3U7xQAhX2

...
2o%3D&reserved=0

Thanks,

Mathieu

Fabio Estevam

6:54 p.m.

Hi Peng,

Here are some comments unrelated to the UART issue.

On Sun, Apr 7, 2024 at 7:35 AM Peng Fan peng.fan@nxp.com wrote:

...

SOC: 0xa1009300 LC: 0x2040010 M33 prepare ok

Could you remove these three lines?

They are not very helpful and add noise to the boot log.

...

Normal Boot Trying to boot from BOOTROM Boot Stage: Primary boot image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x49800 by ROM_API NOTICE: BL31: v2.8(release):lf-6.6.3-1.0.0-10-gf12d90141 NOTICE: BL31: Built : 09:34:44, Mar 27 2024

U-Boot 2024.04-rc5-00388-g351988e2dce (Apr 07 2024 - 19:29:56 +0800)

Reset Status: POR

Could not read CPU frequency: -2 CPU: NXP i.MX93(52) Rev1.1 A55 at 0 MHz

Please fix this. I am sure the CPU is not running at 0 MHz :-)

...

CPU: Industrial temperature grade (-40C to 105C) at 26C

Model: NXP i.MX93 11X11 EVK board DRAM: 2 GiB Core: 188 devices, 24 uclasses, devicetree: separate WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment

In: serial@44380000 Out: serial@44380000 Err: serial@44380000 switch to partitions #0, OK mmc1 is current device Net: Warning: ethernet@428a0000 (eth1) using random MAC address - 6a:c2:96:d2:68:a6 eth0: ethernet@42890000 [PRIME], eth1: ethernet@428a0000

Aren't the MAC address fuses programmed? Or are they not being read correctly?

Peng Fan

8 Apr 8 Apr

1:51 a.m.

...

Subject: Re: [PATCH v4 0/5] imx93: Conver to OF_UPSTREAM

Hi Peng,

Here are some comments unrelated to the UART issue.

On Sun, Apr 7, 2024 at 7:35 AM Peng Fan peng.fan@nxp.com wrote:

...
SOC: 0xa1009300 LC: 0x2040010 M33 prepare ok

Could you remove these three lines?

Ok. But these should not be related to this patchset.

...

They are not very helpful and add noise to the boot log.

...
Normal Boot Trying to boot from BOOTROM Boot Stage: Primary boot image offset 0x8000, pagesize 0x200, ivt offset 0x0 Load image from 0x49800 by ROM_API NOTICE: BL31: v2.8(release):lf-6.6.3-1.0.0-10-gf12d90141 NOTICE: BL31: Built : 09:34:44, Mar 27 2024

U-Boot 2024.04-rc5-00388-g351988e2dce (Apr 07 2024 - 19:29:56 +0800)

Reset Status: POR

Could not read CPU frequency: -2 CPU: NXP i.MX93(52) Rev1.1 A55 at 0 MHz

Please fix this. I am sure the CPU is not running at 0 MHz :-)

Yes, I will fix . Also not related to this patchset.

...

...
CPU: Industrial temperature grade (-40C to 105C) at 26C

Model: NXP i.MX93 11X11 EVK board DRAM: 2 GiB Core: 188 devices, 24 uclasses, devicetree: separate WDT: Started watchdog@42490000 with servicing every 1000ms (40s

timeout)

...
MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... *** Warning - bad CRC, using default environment

In: serial@44380000 Out: serial@44380000 Err: serial@44380000 switch to partitions #0, OK mmc1 is current device Net: Warning: ethernet@428a0000 (eth1) using random MAC address - 6a:c2:96:d2:68:a6 eth0: ethernet@42890000 [PRIME], eth1: ethernet@428a0000

Aren't the MAC address fuses programmed? Or are they not being read correctly?

I will check, but I think not related to this patchset.

Thanks, Peng.

Fabio Estevam

3:22 a.m.

On Sun, Apr 7, 2024 at 8:51 PM Peng Fan peng.fan@nxp.com wrote:

...

Ok. But these should not be related to this patchset.

Yes, that's why my first sentence was:

"Here are some comments unrelated to the UART issue."

Thanks for taking a look at these issues.

Dragan Simic

7 Apr 7 Apr

7:02 p.m.

Hello Peng,

Some minor nitpicks... s/Conver to/Convert to/ in the patch subject, and a couple more below.

On 2024-03-28 06:05, Peng Fan (OSS) wrote:

...

A few nodes were added to soc and board u-boot.dtsi(lpi2c, usbotg), those nodes

s/soc/SoC/

...

could be dropped after upstream linux supports them.

s/linux/Linux/

...

To support OF_UPSTREAM, a few driver changes are included. For TMU, still use U-Boot node, I will prepare a kernel update, then back to U-Boot support.

Mathieu: please help test the boards you maintain when you have time.

Thanks, Peng.

To: Sébastien Szymanski sebastien.szymanski@armadeus.com To: Stefano Babic sbabic@denx.de To: Fabio Estevam festevam@gmail.com To: "NXP i.MX U-Boot Team" uboot-imx@nxp.com To: Mathieu Othacehe m.othacehe@gmail.com Cc: u-boot@lists.denx.de Signed-off-by: Peng Fan peng.fan@nxp.com

Changes in v4:

Convert all i.MX93 boards

Link to v3:

https://lore.kernel.org/r/20240328-imx93-of-v3-0-4e7f341ed7ea@nxp.com

Changes in v3:

Update patch 5, to drop the imx8mp-evk changes which are wrongly included

Link to v2:

https://lore.kernel.org/r/20240328-imx93-of-v2-0-909f5d37da87@nxp.com

Changes in v2:

Add a new patch to sync clock header to avoid breaking

Drop the Makefile change which change including order

Link to v1:

https://lore.kernel.org/r/20240327-imx93-of-v1-0-afab6b31422a@nxp.com

Peng Fan (5): gpio: imx_rgpio2p: support one address serial: lpuart: use ipg clk for i.MX7ULP cpu: drop imx9_cpu clk: imx93: fix anatop base imx93: convert to OF_UPSTREAM

arch/arm/dts/Makefile | 5 - arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 119 ++++ arch/arm/dts/imx93-11x11-evk.dts | 322 --------- arch/arm/dts/imx93-phyboard-segin.dts | 117 --- arch/arm/dts/imx93-phycore-som.dtsi | 126 ---- arch/arm/dts/imx93-pinfunc.h | 623 ---------------- arch/arm/dts/imx93-u-boot.dtsi | 80 +++ arch/arm/dts/imx93-var-som-symphony-u-boot.dtsi | 22 + arch/arm/dts/imx93-var-som-symphony.dts | 323 --------- arch/arm/dts/imx93-var-som.dtsi | 111 --- arch/arm/dts/imx93.dtsi | 906

arch/arm/mach-imx/imx9/Kconfig | 1 + configs/imx93-phyboard-segin_defconfig | 2 +- configs/imx93_11x11_evk_defconfig | 2 +- configs/imx93_11x11_evk_ld_defconfig | 2 +- configs/imx93_var_som_defconfig | 2 +- drivers/clk/imx/clk-imx93.c | 2 +- drivers/cpu/imx9_cpu.c | 224 ------ drivers/gpio/imx_rgpio2p.c | 42 +- drivers/serial/serial_lpuart.c | 9 +- include/dt-bindings/clock/imx93-clock.h | 208 ------ include/dt-bindings/power/fsl,imx93-power.h | 15 - 22 files changed, 273 insertions(+), 2990 deletions(-)

base-commit: 280f34ba7d68bb50c0b8eaa040322c1f3b37d46e change-id: 20240328-imx93-of-v2-f879efef737d

Best regards,

Peng Fan

8 Apr 8 Apr

1:52 a.m.

...

Subject: Re: [PATCH v4 0/5] imx93: Conver to OF_UPSTREAM

Hello Peng,

Some minor nitpicks... s/Conver to/Convert to/ in the patch subject, and a couple more below.

On 2024-03-28 06:05, Peng Fan (OSS) wrote:

...
A few nodes were added to soc and board u-boot.dtsi(lpi2c, usbotg), those nodes

s/soc/SoC/

...
could be dropped after upstream linux supports them.

s/linux/Linux/

Will fix all the typos in V5.

Thanks, Peng.

...

...
To support OF_UPSTREAM, a few driver changes are included. For TMU, still use U-Boot node, I will prepare a kernel update, then back to U-Boot support.

Mathieu: please help test the boards you maintain when you have time.

Thanks, Peng.

To: Sébastien Szymanski sebastien.szymanski@armadeus.com To: Stefano Babic sbabic@denx.de To: Fabio Estevam festevam@gmail.com To: "NXP i.MX U-Boot Team" uboot-imx@nxp.com To: Mathieu Othacehe m.othacehe@gmail.com Cc: u-boot@lists.denx.de Signed-off-by: Peng Fan peng.fan@nxp.com

Changes in v4:

Convert all i.MX93 boards

Link to v3:

https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore .kernel.org%2Fr%2F20240328-imx93-of-v3-0-

4e7f341ed7ea%40nxp.com&data=0

...
5%7C02%7Cpeng.fan%40nxp.com%7Cfb4cf5cd6eb048f7004508dc5724921f %7C686ea

...
1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638481061784727166%7CU nknown%7CT

...
WFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLC JXVCI

...
6Mn0%3D%7C0%7C%7C%7C&sdata=m3eUSDFipFRBJlujTzNovsgusVTRp8lekD guNKKGlq8

...
%3D&reserved=0

Changes in v3:

Update patch 5, to drop the imx8mp-evk changes which are wrongly included

Link to v2:

https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore .kernel.org%2Fr%2F20240328-imx93-of-v2-0-

909f5d37da87%40nxp.com&data=0

...
5%7C02%7Cpeng.fan%40nxp.com%7Cfb4cf5cd6eb048f7004508dc5724921f %7C686ea

...
1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638481061784740481%7CU nknown%7CT

...
WFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLC JXVCI

...
6Mn0%3D%7C0%7C%7C%7C&sdata=dOltsehRiqbWFgRABoeC1nUqbU5CTz2 OOt6Yq7u9sj0

...
%3D&reserved=0

Changes in v2:

Add a new patch to sync clock header to avoid breaking

Drop the Makefile change which change including order

Link to v1:

https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore .kernel.org%2Fr%2F20240327-imx93-of-v1-0-

afab6b31422a%40nxp.com&data=0

...
5%7C02%7Cpeng.fan%40nxp.com%7Cfb4cf5cd6eb048f7004508dc5724921f %7C686ea

...
1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638481061784750001%7CU nknown%7CT

...
WFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLC JXVCI

...
6Mn0%3D%7C0%7C%7C%7C&sdata=x4s291DNECLAyKaOdMRse2CLfFwaSx8Z %2BCdLZZrYV

...
mY%3D&reserved=0

Peng Fan (5): gpio: imx_rgpio2p: support one address serial: lpuart: use ipg clk for i.MX7ULP cpu: drop imx9_cpu clk: imx93: fix anatop base imx93: convert to OF_UPSTREAM

arch/arm/dts/Makefile | 5 - arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 119 ++++ arch/arm/dts/imx93-11x11-evk.dts | 322 --------- arch/arm/dts/imx93-phyboard-segin.dts | 117 --- arch/arm/dts/imx93-phycore-som.dtsi | 126 ---- arch/arm/dts/imx93-pinfunc.h | 623 ---------------- arch/arm/dts/imx93-u-boot.dtsi | 80 +++ arch/arm/dts/imx93-var-som-symphony-u-boot.dtsi | 22 + arch/arm/dts/imx93-var-som-symphony.dts | 323 --------- arch/arm/dts/imx93-var-som.dtsi | 111 --- arch/arm/dts/imx93.dtsi | 906

arch/arm/mach-imx/imx9/Kconfig | 1 + configs/imx93-phyboard-segin_defconfig | 2 +- configs/imx93_11x11_evk_defconfig | 2 +- configs/imx93_11x11_evk_ld_defconfig | 2 +- configs/imx93_var_som_defconfig | 2 +- drivers/clk/imx/clk-imx93.c | 2 +- drivers/cpu/imx9_cpu.c | 224 ------ drivers/gpio/imx_rgpio2p.c | 42 +- drivers/serial/serial_lpuart.c | 9 +- include/dt-bindings/clock/imx93-clock.h | 208 ------ include/dt-bindings/power/fsl,imx93-power.h | 15 - 22 files changed, 273 insertions(+), 2990 deletions(-)

base-commit: 280f34ba7d68bb50c0b8eaa040322c1f3b37d46e change-id: 20240328-imx93-of-v2-f879efef737d

Best regards,

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participants (5)

Dragan Simic
Fabio Estevam
Mathieu Othacehe
Peng Fan
Peng Fan (OSS)