[U-Boot] [PATCH 2/2] KB9202: Add NAND support
KB9202: Add NAND support
This is a forward port of the patch submitted by Christian from Kwikbyte in 06/2007 (http://lists.denx.de/pipermail/u-boot/2007-June/022068.html)
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
--
--- u-boot-2009.03.org/board/kb9202/Makefile 2009-03-21 22:04:41.000000000 +0100 +++ u-boot-2009.03/board/kb9202/Makefile 2009-05-15 23:30:11.000000000 +0200 @@ -28,7 +28,7 @@
LIB = $(obj)lib$(BOARD).a
-COBJS := kb9202.o +COBJS := kb9202.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) --- /dev/null 2009-05-14 23:36:38.280017984 +0200 +++ u-boot-2009.03/board/kb9202/nand.c 2009-05-15 23:30:11.000000000 +0200 @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2006 KwikByte kb9200_dev@kwikbyte.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/AT91RM9200.h> +#include <asm/arch/hardware.h> + +#ifdef CONFIG_CMD_NAND + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ + +#define MASK_ALE (1 << 22) /* our ALE is A22 */ +#define MASK_CLE (1 << 21) /* our CLE is A21 */ + +#ifndef CONFIG_KB9202B_ATL +#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ +#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ +#else +#define KB9202_NAND_NCE (1 << 26) /* EN* on PB26 */ +#define KB9202_NAND_BUSY (1 << 27) /* RB* on PB27 */ +#endif + +/* + * Board-specific function to access device control signals + */ +static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + /* clear ALE and CLE bits */ + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (ctrl & NAND_NCE) + AT91C_BASE_PIOC->PIO_CODR = KB9202_NAND_NCE; + else + AT91C_BASE_PIOC->PIO_SODR = KB9202_NAND_NCE; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + + +/* + * Board-specific function to access the device ready signal. + */ +static int kb9202_nand_ready(struct mtd_info *mtd) +{ + return (((AT91C_BASE_PIOC->PIO_PDSR) & KB9202_NAND_BUSY) != 0); +} + + +/* + * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference. + * + * struct nand_chip - NAND Private Flash Chip Data + * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device + * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device + * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line + * If set to NULL no access to ready/busy is available and the ready/busy information + * is read from the chip status register + * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only + * be provided if a hardware ECC is available + * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines + * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) + * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about + * special functionality. See the defines for further explanation +*/ +/* + * This routine initializes controller and GPIOs. + */ +int board_nand_init(struct nand_chip *nand) +{ + unsigned value; + + nand->ecc.mode = NAND_ECC_SOFT; + nand->options &= ~(NAND_BUSWIDTH_16); + nand->cmd_ctrl = kb9202_nand_hwcontrol; + nand->dev_ready = kb9202_nand_ready; + + /* in case running outside of bootloader */ + AT91C_BASE_PMC->PMC_PCER = ((unsigned) 1 << AT91C_ID_PIOC); +#ifdef CONFIG_KB9202B_ATL + AT91C_BASE_PMC->PMC_PCER = ((unsigned) 1 << AT91C_ID_PIOB); +#endif + + /* setup nand flash access (allow ample margin) */ + /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */ + ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[3] = + AT91C_SMC2_WSEN | + (4 & AT91C_SMC2_NWS) | + ((1 << 8) & AT91C_SMC2_TDF) | + AT91C_SMC2_DBW_8 | + ((1 << 24) & AT91C_SMC2_RWSETUP) | + ((1 << 29) & AT91C_SMC2_RWHOLD); + + /* enable internal NAND controller */ + value = *(AT91C_EBI_CSA); + value |= AT91C_EBI_CS3A_SMC_SmartMedia; + *(AT91C_EBI_CSA) = value; + + /* enable SMOE/SMWE */ + AT91C_BASE_PIOC->PIO_ASR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE; + AT91C_BASE_PIOC->PIO_PDR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE; + AT91C_BASE_PIOC->PIO_OER = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE; + + /* set NCE to high */ + AT91C_BASE_PIOC->PIO_SODR = KB9202_NAND_NCE; + + /* disable output on pin connected to the busy line of the NAND */ + AT91C_BASE_PIOC->PIO_ODR = KB9202_NAND_BUSY; + + /* enable the PIO to control NCE and BUSY */ + AT91C_BASE_PIOC->PIO_PER = KB9202_NAND_NCE | KB9202_NAND_BUSY; + + /* enable output for NCE */ + AT91C_BASE_PIOC->PIO_OER = KB9202_NAND_NCE; + + return (0); +} + +#endif /* CONFIG_CMD_NAND */ --- u-boot-2009.03.org/include/configs/kb9202.h 2009-05-15 23:31:55.000000000 +0200 +++ u-boot-2009.03/include/configs/kb9202.h 2009-05-15 23:30:11.000000000 +0200 @@ -62,6 +62,11 @@ #ifdef CONFIG_KB9202B #define CONFIG_BOOTARGS "console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M" #define CONFIG_BOOTCOMMAND "bootm 0x10000000" +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_CMDLINE #endif
@@ -71,7 +76,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_MALLOC_LEN (1024*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200 @@ -111,6 +116,9 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP +#ifdef CONFIG_KB9202B +#define CONFIG_CMD_NAND +#endif #define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_BDI @@ -140,7 +148,11 @@ #define PHYS_FLASH_SIZE 0x200000 #endif
+#ifdef CONFIG_KB9202B_ATL +#define CFG_MAX_FLASH_BANKS 0 +#else #define CONFIG_SYS_MAX_FLASH_BANKS 1 +#endif #define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_HARD_I2C
Matthias Kaehlcke wrote:
+/*
- Board-specific function to access the device ready signal.
- */
+static int kb9202_nand_ready(struct mtd_info *mtd) +{
- return (((AT91C_BASE_PIOC->PIO_PDSR) & KB9202_NAND_BUSY) != 0);
+}
Use I/O accessors.
+int board_nand_init(struct nand_chip *nand) +{
- unsigned value;
[snip]
- /* enable internal NAND controller */
- value = *(AT91C_EBI_CSA);
- value |= AT91C_EBI_CS3A_SMC_SmartMedia;
- *(AT91C_EBI_CSA) = value;
This is a hardware register. Surely it has a defined width?
- /* setup nand flash access (allow ample margin) */
- /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
- ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[3] =
AT91C_SMC2_WSEN |(4 & AT91C_SMC2_NWS) |((1 << 8) & AT91C_SMC2_TDF) |AT91C_SMC2_DBW_8 |((1 << 24) & AT91C_SMC2_RWSETUP) |((1 << 29) & AT91C_SMC2_RWHOLD);
What is AT91PS_SMC2? Please don't hide pointers inside typedefs. Please define symbols to have the proper type in the first place, rather than casting at the point of use.
+#ifdef CONFIG_KB9202B_ATL +#define CFG_MAX_FLASH_BANKS 0 +#else
Is this really the recommended way of turning off flash support?
-Scott
Hi Scott
El Fri, May 15, 2009 at 05:30:48PM -0500 Scott Wood ha dit:
Matthias Kaehlcke wrote:
+/*
- Board-specific function to access the device ready signal.
- */
+static int kb9202_nand_ready(struct mtd_info *mtd) +{
- return (((AT91C_BASE_PIOC->PIO_PDSR) & KB9202_NAND_BUSY) != 0);
+}
Use I/O accessors.
+int board_nand_init(struct nand_chip *nand) +{
- unsigned value;
[snip]
- /* enable internal NAND controller */
- value = *(AT91C_EBI_CSA);
- value |= AT91C_EBI_CS3A_SMC_SmartMedia;
- *(AT91C_EBI_CSA) = value;
This is a hardware register. Surely it has a defined width?
- /* setup nand flash access (allow ample margin) */
- /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
- ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[3] =
AT91C_SMC2_WSEN |(4 & AT91C_SMC2_NWS) |((1 << 8) & AT91C_SMC2_TDF) |AT91C_SMC2_DBW_8 |((1 << 24) & AT91C_SMC2_RWSETUP) |((1 << 29) & AT91C_SMC2_RWHOLD);What is AT91PS_SMC2? Please don't hide pointers inside typedefs. Please define symbols to have the proper type in the first place, rather than casting at the point of use.
+#ifdef CONFIG_KB9202B_ATL +#define CFG_MAX_FLASH_BANKS 0 +#else
Is this really the recommended way of turning off flash support?
thanks for your review and your comments.
i'm new to u-boot development, could you point me to the correct way of turning of flash support? i found this in the original patch provided by kwikbyte and just ported it to the current u-boot version.
Matthias Kaehlcke wrote:
+#ifdef CONFIG_KB9202B_ATL +#define CFG_MAX_FLASH_BANKS 0 +#else
Is this really the recommended way of turning off flash support?
thanks for your review and your comments.
i'm new to u-boot development, could you point me to the correct way of turning of flash support? i found this in the original patch provided by kwikbyte and just ported it to the current u-boot version.
To disable NOR flash support, do not define CONFIG_FLASH_CFI_* or CONFIG_CMD_FLASH, and do define CONFIG_SYS_NO_FLASH.
-Scott
El Mon, May 18, 2009 at 12:38:35PM -0500 Scott Wood ha dit:
Matthias Kaehlcke wrote:
+#ifdef CONFIG_KB9202B_ATL +#define CFG_MAX_FLASH_BANKS 0 +#else
Is this really the recommended way of turning off flash support?
thanks for your review and your comments.
i'm new to u-boot development, could you point me to the correct way of turning of flash support? i found this in the original patch provided by kwikbyte and just ported it to the current u-boot version.
To disable NOR flash support, do not define CONFIG_FLASH_CFI_* or CONFIG_CMD_FLASH, and do define CONFIG_SYS_NO_FLASH.
thanks for the pointer! actually i made an attempt with CONFIG_SYS_NO_FLASH, but this seems disable flash support at all (NOR and NAND), the linker complained about unresolved symbols in the JFFS code.
at the moment my development system is down due to some hardware fault. as soon as i recover it i'll prepare a patch that addresses the concerns you have raised
hi,
El Fri, May 15, 2009 at 05:30:48PM -0500 Scott Wood ha dit:
Matthias Kaehlcke wrote:
+/*
- Board-specific function to access the device ready signal.
- */
+static int kb9202_nand_ready(struct mtd_info *mtd) +{
- return (((AT91C_BASE_PIOC->PIO_PDSR) & KB9202_NAND_BUSY) != 0);
+}
Use I/O accessors.
+int board_nand_init(struct nand_chip *nand) +{
- unsigned value;
[snip]
- /* enable internal NAND controller */
- value = *(AT91C_EBI_CSA);
- value |= AT91C_EBI_CS3A_SMC_SmartMedia;
- *(AT91C_EBI_CSA) = value;
This is a hardware register. Surely it has a defined width?
- /* setup nand flash access (allow ample margin) */
- /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
- ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[3] =
AT91C_SMC2_WSEN |(4 & AT91C_SMC2_NWS) |((1 << 8) & AT91C_SMC2_TDF) |AT91C_SMC2_DBW_8 |((1 << 24) & AT91C_SMC2_RWSETUP) |((1 << 29) & AT91C_SMC2_RWHOLD);What is AT91PS_SMC2? Please don't hide pointers inside typedefs. Please define symbols to have the proper type in the first place, rather than casting at the point of use.
here is a version of the patch that addresses the issues you pointed out. sorry for the late response, my development system died and i needed some time to get a new machine and restore the setup
--
This is a forward port of the patch submitted by Christian from Kwikbyte in 06/2007 (http://lists.denx.de/pipermail/u-boot/2007-June/022068.html)
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net --- board/kb9202/Makefile | 2 +- board/kb9202/nand.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/kb9202.h | 10 +++- 3 files changed, 163 insertions(+), 2 deletions(-) create mode 100644 board/kb9202/nand.c
diff --git a/board/kb9202/Makefile b/board/kb9202/Makefile index 363f665..0ba4fcc 100644 --- a/board/kb9202/Makefile +++ b/board/kb9202/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := kb9202.o +COBJS := kb9202.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/kb9202/nand.c b/board/kb9202/nand.c new file mode 100644 index 0000000..fa63aa1 --- /dev/null +++ b/board/kb9202/nand.c @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2006 KwikByte kb9200_dev@kwikbyte.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/AT91RM9200.h> +#include <asm/arch/hardware.h> + +#ifdef CONFIG_CMD_NAND + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ + +#define MASK_ALE (1 << 22) /* our ALE is A22 */ +#define MASK_CLE (1 << 21) /* our CLE is A21 */ + +#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ +#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ + +/* + * Board-specific function to access device control signals + */ +static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + /* clear ALE and CLE bits */ + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (ctrl & NAND_NCE) + AT91C_BASE_PIOC->PIO_CODR = KB9202_NAND_NCE; + else + AT91C_BASE_PIOC->PIO_SODR = KB9202_NAND_NCE; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + + +/* + * Board-specific function to access the device ready signal. + */ +static int kb9202_nand_ready(struct mtd_info *mtd) +{ + const unsigned int value = readl(AT91C_PIOC_PDSR); + + return ((value & KB9202_NAND_BUSY) != 0); +} + + +/* + * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference. + * + * struct nand_chip - NAND Private Flash Chip Data + * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device + * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device + * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line + * If set to NULL no access to ready/busy is available and the ready/busy information + * is read from the chip status register + * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only + * be provided if a hardware ECC is available + * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines + * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) + * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about + * special functionality. See the defines for further explanation +*/ +/* + * This routine initializes controller and GPIOs. + */ +int board_nand_init(struct nand_chip *nand) +{ + unsigned int value; + struct _AT91S_SMC2 *at91s_smc2 = AT91C_BASE_SMC2; + + nand->ecc.mode = NAND_ECC_SOFT; + nand->options &= ~(NAND_BUSWIDTH_16); + nand->cmd_ctrl = kb9202_nand_hwcontrol; + nand->dev_ready = kb9202_nand_ready; + + /* in case running outside of bootloader */ + AT91C_BASE_PMC->PMC_PCER = ((unsigned) 1 << AT91C_ID_PIOC); + + /* setup nand flash access (allow ample margin) */ + /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */ + at91s_smc2->SMC2_CSR[3] = + AT91C_SMC2_WSEN | + (4 & AT91C_SMC2_NWS) | + ((1 << 8) & AT91C_SMC2_TDF) | + AT91C_SMC2_DBW_8 | + ((1 << 24) & AT91C_SMC2_RWSETUP) | + ((1 << 29) & AT91C_SMC2_RWHOLD); + + /* enable internal NAND controller */ + value = *(AT91C_EBI_CSA); + value |= AT91C_EBI_CS3A_SMC_SmartMedia; + *(AT91C_EBI_CSA) = value; + + /* enable SMOE/SMWE */ + AT91C_BASE_PIOC->PIO_ASR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE; + AT91C_BASE_PIOC->PIO_PDR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE; + AT91C_BASE_PIOC->PIO_OER = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE; + + /* set NCE to high */ + AT91C_BASE_PIOC->PIO_SODR = KB9202_NAND_NCE; + + /* disable output on pin connected to the busy line of the NAND */ + AT91C_BASE_PIOC->PIO_ODR = KB9202_NAND_BUSY; + + /* enable the PIO to control NCE and BUSY */ + AT91C_BASE_PIOC->PIO_PER = KB9202_NAND_NCE | KB9202_NAND_BUSY; + + /* enable output for NCE */ + AT91C_BASE_PIOC->PIO_OER = KB9202_NAND_NCE; + + return (0); +} + +#endif /* CONFIG_CMD_NAND */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 8651e53..cd4c577 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -62,6 +62,11 @@ #ifdef CONFIG_KB9202B #define CONFIG_BOOTARGS "console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M" #define CONFIG_BOOTCOMMAND "bootm 0x10000000" +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_CMDLINE #endif
@@ -71,7 +76,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_MALLOC_LEN (1024*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200 @@ -112,6 +117,9 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP +#ifdef CONFIG_KB9202B +#define CONFIG_CMD_NAND +#endif #define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_BDI
Matthias Kaehlcke wrote:
hi,
El Fri, May 15, 2009 at 05:30:48PM -0500 Scott Wood ha dit:
Matthias Kaehlcke wrote:
+/*
- Board-specific function to access the device ready signal.
- */
+static int kb9202_nand_ready(struct mtd_info *mtd) +{
- return (((AT91C_BASE_PIOC->PIO_PDSR) & KB9202_NAND_BUSY) != 0);
+}
Use I/O accessors.
[snip]
if (ctrl & NAND_NCE)AT91C_BASE_PIOC->PIO_CODR = KB9202_NAND_NCE;elseAT91C_BASE_PIOC->PIO_SODR = KB9202_NAND_NCE;
You're still not using I/O accessors in many places.
+#ifdef CONFIG_CMD_NAND
Put this in the makefile instead.
+static int kb9202_nand_ready(struct mtd_info *mtd) +{
- const unsigned int value = readl(AT91C_PIOC_PDSR);
- return ((value & KB9202_NAND_BUSY) != 0);
+}
static int kb9202_nand_ready(struct mtd_info *mtd) { return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY; }
+int board_nand_init(struct nand_chip *nand) +{
- unsigned int value;
- struct _AT91S_SMC2 *at91s_smc2 = AT91C_BASE_SMC2;
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->options &= ~(NAND_BUSWIDTH_16);
Unnecessary parens.
- nand->cmd_ctrl = kb9202_nand_hwcontrol;
- nand->dev_ready = kb9202_nand_ready;
- /* in case running outside of bootloader */
- AT91C_BASE_PMC->PMC_PCER = ((unsigned) 1 << AT91C_ID_PIOC);
Unnecessary cast and parens.
- at91s_smc2->SMC2_CSR[3] =
AT91C_SMC2_WSEN |(4 & AT91C_SMC2_NWS) |((1 << 8) & AT91C_SMC2_TDF) |AT91C_SMC2_DBW_8 |((1 << 24) & AT91C_SMC2_RWSETUP) |((1 << 29) & AT91C_SMC2_RWHOLD);
Are those instances of (constant1 & constant2) ever going to evaluate to anything but constant1? Can we get rid of the magic numbers?
Otherwise, ACK.
-Scott
El Wed, Jun 03, 2009 at 02:50:40PM -0500 Scott Wood ha dit:
Matthias Kaehlcke wrote:
hi,
El Fri, May 15, 2009 at 05:30:48PM -0500 Scott Wood ha dit:
Matthias Kaehlcke wrote:
+/*
- Board-specific function to access the device ready signal.
- */
+static int kb9202_nand_ready(struct mtd_info *mtd) +{
- return (((AT91C_BASE_PIOC->PIO_PDSR) & KB9202_NAND_BUSY) != 0);
+}
Use I/O accessors.
[snip]
if (ctrl & NAND_NCE)AT91C_BASE_PIOC->PIO_CODR = KB9202_NAND_NCE;elseAT91C_BASE_PIOC->PIO_SODR = KB9202_NAND_NCE;You're still not using I/O accessors in many places.
+#ifdef CONFIG_CMD_NAND
Put this in the makefile instead.
+static int kb9202_nand_ready(struct mtd_info *mtd) +{
- const unsigned int value = readl(AT91C_PIOC_PDSR);
- return ((value & KB9202_NAND_BUSY) != 0);
+}
static int kb9202_nand_ready(struct mtd_info *mtd) { return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY; }
+int board_nand_init(struct nand_chip *nand) +{
- unsigned int value;
- struct _AT91S_SMC2 *at91s_smc2 = AT91C_BASE_SMC2;
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->options &= ~(NAND_BUSWIDTH_16);
Unnecessary parens.
- nand->cmd_ctrl = kb9202_nand_hwcontrol;
- nand->dev_ready = kb9202_nand_ready;
- /* in case running outside of bootloader */
- AT91C_BASE_PMC->PMC_PCER = ((unsigned) 1 << AT91C_ID_PIOC);
Unnecessary cast and parens.
- at91s_smc2->SMC2_CSR[3] =
AT91C_SMC2_WSEN |(4 & AT91C_SMC2_NWS) |((1 << 8) & AT91C_SMC2_TDF) |AT91C_SMC2_DBW_8 |((1 << 24) & AT91C_SMC2_RWSETUP) |((1 << 29) & AT91C_SMC2_RWHOLD);Are those instances of (constant1 & constant2) ever going to evaluate to anything but constant1? Can we get rid of the magic numbers?
Otherwise, ACK.
thanks for your comments!
i hope this version of the patch addresses all your concerns
--
This is a forward port of the patch submitted by Christian from Kwikbyte in 06/2007 (http://lists.denx.de/pipermail/u-boot/2007-June/022068.html)
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net --- board/kb9202/Makefile | 1 + board/kb9202/nand.c | 151 ++++++++++++++++++++++++++ include/asm-arm/arch-at91rm9200/AT91RM9200.h | 2 + include/configs/kb9202.h | 10 ++- 4 files changed, 163 insertions(+), 1 deletions(-) create mode 100644 board/kb9202/nand.c
diff --git a/board/kb9202/Makefile b/board/kb9202/Makefile index 363f665..d78454d 100644 --- a/board/kb9202/Makefile +++ b/board/kb9202/Makefile @@ -29,6 +29,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a
COBJS := kb9202.o +COBJS-$(CONFIG_CMD_NAND) += nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/kb9202/nand.c b/board/kb9202/nand.c new file mode 100644 index 0000000..7db8d7c --- /dev/null +++ b/board/kb9202/nand.c @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2006 + * KwikByte kb9200_dev@kwikbyte.com + * + * (C) Copyright 2009 + * Matthias Kaehlcke matthias@kaehlcke.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/AT91RM9200.h> +#include <asm/arch/hardware.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ + +#define MASK_ALE (1 << 22) /* our ALE is A22 */ +#define MASK_CLE (1 << 21) /* our CLE is A21 */ + +#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ +#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ + +#define KB9202_SMC2_NWS (1 << 2) +#define KB9202_SMC2_TDF (1 << 8) +#define KB9202_SMC2_RWSETUP (1 << 24) +#define KB9202_SMC2_RWHOLD (1 << 29) + +/* + * Board-specific function to access device control signals + */ +static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + /* clear ALE and CLE bits */ + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (ctrl & NAND_NCE) + writel(KB9202_NAND_NCE, AT91C_PIOC_CODR); + else + writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + + +/* + * Board-specific function to access the device ready signal. + */ +static int kb9202_nand_ready(struct mtd_info *mtd) +{ + return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY; +} + + +/* + * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference. + * + * struct nand_chip - NAND Private Flash Chip Data + * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device + * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device + * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line + * If set to NULL no access to ready/busy is available and the ready/busy information + * is read from the chip status register + * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only + * be provided if a hardware ECC is available + * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines + * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) + * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about + * special functionality. See the defines for further explanation +*/ +/* + * This routine initializes controller and GPIOs. + */ +int board_nand_init(struct nand_chip *nand) +{ + unsigned int value; + + nand->ecc.mode = NAND_ECC_SOFT; + nand->options &= ~NAND_BUSWIDTH_16; + nand->cmd_ctrl = kb9202_nand_hwcontrol; + nand->dev_ready = kb9202_nand_ready; + + /* in case running outside of bootloader */ + writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER); + + /* setup nand flash access (allow ample margin) */ + /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */ + writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF | + AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD, + AT91C_SMC_CSR3); + + /* enable internal NAND controller */ + value = readl(AT91C_EBI_CSA); + value |= AT91C_EBI_CS3A_SMC_SmartMedia; + writel(value, AT91C_EBI_CSA); + + /* enable SMOE/SMWE */ + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR); + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR); + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER); + + /* set NCE to high */ + writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); + + /* disable output on pin connected to the busy line of the NAND */ + writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR); + + /* enable the PIO to control NCE and BUSY */ + writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER); + + /* enable output for NCE */ + writel(KB9202_NAND_NCE, AT91C_PIOC_OER); + + return (0); +} diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 00bae1c..2e40565 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -737,6 +737,7 @@ typedef struct _AT91S_PDC #define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ #define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) /* (PIOC) PIO Output Enable Register */ #define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ #define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ #define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ @@ -790,6 +791,7 @@ typedef struct _AT91S_PDC #define AT91C_MC_AASR 0xFFFFFF08 #define AT91C_EBI_CFGR 0xFFFFFF64 #define AT91C_SMC_CSR0 0xFFFFFF70 +#define AT91C_SMC_CSR3 0xFFFFFF7C
/* clocks */ #define AT91C_PLLAR 0xFFFFFC28 diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 8651e53..cd4c577 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -62,6 +62,11 @@ #ifdef CONFIG_KB9202B #define CONFIG_BOOTARGS "console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M" #define CONFIG_BOOTCOMMAND "bootm 0x10000000" +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_CMDLINE #endif
@@ -71,7 +76,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_MALLOC_LEN (1024*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200 @@ -112,6 +117,9 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP +#ifdef CONFIG_KB9202B +#define CONFIG_CMD_NAND +#endif #define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_BDI
On Wednesday 03 June 2009 19:42:00 Matthias Kaehlcke wrote:
<snip>
here is a version of the patch that addresses the issues you pointed out. sorry for the late response, my development system died and i needed some time to get a new machine and restore the setup
--
This is a forward port of the patch submitted by Christian from Kwikbyte in 06/2007 (http://lists.denx.de/pipermail/u-boot/2007-June/022068.html)
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
board/kb9202/Makefile | 2 +- board/kb9202/nand.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/kb9202.h | 10 +++- 3 files changed, 163 insertions(+), 2 deletions(-) create mode 100644 board/kb9202/nand.c
I suggest to move this driver to drivers/mtd/nand instead.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
El Thu, Jun 04, 2009 at 08:53:10AM +0200 Stefan Roese ha dit:
On Wednesday 03 June 2009 19:42:00 Matthias Kaehlcke wrote:
<snip>
here is a version of the patch that addresses the issues you pointed out. sorry for the late response, my development system died and i needed some time to get a new machine and restore the setup
--
This is a forward port of the patch submitted by Christian from Kwikbyte in 06/2007 (http://lists.denx.de/pipermail/u-boot/2007-June/022068.html)
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
board/kb9202/Makefile | 2 +- board/kb9202/nand.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/kb9202.h | 10 +++- 3 files changed, 163 insertions(+), 2 deletions(-) create mode 100644 board/kb9202/nand.c
I suggest to move this driver to drivers/mtd/nand instead.
i thought drivers/mtd/nand is for generic nand drivers, mine - at least atm - is kb9202 specific. if it's really preferred to have board specific drivers in drivers/mtd/nand i'll the adapt the patch happily.
On Thursday 04 June 2009 19:49:25 Matthias Kaehlcke wrote:
This is a forward port of the patch submitted by Christian from Kwikbyte in 06/2007 (http://lists.denx.de/pipermail/u-boot/2007-June/022068.html)
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
board/kb9202/Makefile | 2 +- board/kb9202/nand.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/kb9202.h | 10 +++- 3 files changed, 163 insertions(+), 2 deletions(-) create mode 100644 board/kb9202/nand.c
I suggest to move this driver to drivers/mtd/nand instead.
i thought drivers/mtd/nand is for generic nand drivers,
No, it's for all NAND driver using the common NAND MTD infrastructure. Same as in Linux.
mine - at least atm - is kb9202 specific. if it's really preferred to have board specific drivers in drivers/mtd/nand i'll the adapt the patch happily.
Yes, please move it. It's better to collect all NAND related drivers in one place.
Thanks.
Best regards, Stefan
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office@denx.de =====================================================================
El Thu, Jun 04, 2009 at 08:08:04PM +0200 Stefan Roese ha dit:
On Thursday 04 June 2009 19:49:25 Matthias Kaehlcke wrote:
This is a forward port of the patch submitted by Christian from Kwikbyte in 06/2007 (http://lists.denx.de/pipermail/u-boot/2007-June/022068.html)
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
board/kb9202/Makefile | 2 +- board/kb9202/nand.c | 153 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/kb9202.h | 10 +++- 3 files changed, 163 insertions(+), 2 deletions(-) create mode 100644 board/kb9202/nand.c
I suggest to move this driver to drivers/mtd/nand instead.
i thought drivers/mtd/nand is for generic nand drivers,
No, it's for all NAND driver using the common NAND MTD infrastructure. Same as in Linux.
mine - at least atm - is kb9202 specific. if it's really preferred to have board specific drivers in drivers/mtd/nand i'll the adapt the patch happily.
Yes, please move it. It's better to collect all NAND related drivers in one place.
thanks for your explication, below is the driver in the corresponding directory
--
Add NAND support for the KwikByte KB9202
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/kb9202_nand.c | 151 ++++++++++++++++++++++++++ include/asm-arm/arch-at91rm9200/AT91RM9200.h | 2 + include/configs/kb9202.h | 11 ++- 4 files changed, 164 insertions(+), 1 deletions(-) create mode 100644 drivers/mtd/nand/kb9202_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 471cd6b..d2f3e61 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -44,6 +44,7 @@ COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o endif
COBJS := $(COBJS-y) diff --git a/drivers/mtd/nand/kb9202_nand.c b/drivers/mtd/nand/kb9202_nand.c new file mode 100644 index 0000000..7db8d7c --- /dev/null +++ b/drivers/mtd/nand/kb9202_nand.c @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2006 + * KwikByte kb9200_dev@kwikbyte.com + * + * (C) Copyright 2009 + * Matthias Kaehlcke matthias@kaehlcke.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/AT91RM9200.h> +#include <asm/arch/hardware.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ + +#define MASK_ALE (1 << 22) /* our ALE is A22 */ +#define MASK_CLE (1 << 21) /* our CLE is A21 */ + +#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ +#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ + +#define KB9202_SMC2_NWS (1 << 2) +#define KB9202_SMC2_TDF (1 << 8) +#define KB9202_SMC2_RWSETUP (1 << 24) +#define KB9202_SMC2_RWHOLD (1 << 29) + +/* + * Board-specific function to access device control signals + */ +static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + /* clear ALE and CLE bits */ + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (ctrl & NAND_NCE) + writel(KB9202_NAND_NCE, AT91C_PIOC_CODR); + else + writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + + +/* + * Board-specific function to access the device ready signal. + */ +static int kb9202_nand_ready(struct mtd_info *mtd) +{ + return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY; +} + + +/* + * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference. + * + * struct nand_chip - NAND Private Flash Chip Data + * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device + * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device + * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line + * If set to NULL no access to ready/busy is available and the ready/busy information + * is read from the chip status register + * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only + * be provided if a hardware ECC is available + * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines + * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) + * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about + * special functionality. See the defines for further explanation +*/ +/* + * This routine initializes controller and GPIOs. + */ +int board_nand_init(struct nand_chip *nand) +{ + unsigned int value; + + nand->ecc.mode = NAND_ECC_SOFT; + nand->options &= ~NAND_BUSWIDTH_16; + nand->cmd_ctrl = kb9202_nand_hwcontrol; + nand->dev_ready = kb9202_nand_ready; + + /* in case running outside of bootloader */ + writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER); + + /* setup nand flash access (allow ample margin) */ + /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */ + writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF | + AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD, + AT91C_SMC_CSR3); + + /* enable internal NAND controller */ + value = readl(AT91C_EBI_CSA); + value |= AT91C_EBI_CS3A_SMC_SmartMedia; + writel(value, AT91C_EBI_CSA); + + /* enable SMOE/SMWE */ + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR); + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR); + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER); + + /* set NCE to high */ + writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); + + /* disable output on pin connected to the busy line of the NAND */ + writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR); + + /* enable the PIO to control NCE and BUSY */ + writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER); + + /* enable output for NCE */ + writel(KB9202_NAND_NCE, AT91C_PIOC_OER); + + return (0); +} diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 00bae1c..aaab2c2 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -737,6 +737,7 @@ typedef struct _AT91S_PDC #define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ #define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) /* (PIOC) PIO Output Enable Register */ #define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ #define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ #define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ @@ -780,6 +781,7 @@ typedef struct _AT91S_PDC #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ +#define AT91C_SMC_CSR3 ((AT91_REG *) 0xFFFFFF7C) /* (SMC) Chip Select Register 3 */
#else /* flash */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 8651e53..c51845e 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -62,6 +62,12 @@ #ifdef CONFIG_KB9202B #define CONFIG_BOOTARGS "console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M" #define CONFIG_BOOTCOMMAND "bootm 0x10000000" +#define CONFIG_NAND_KB9202 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_CMDLINE #endif
@@ -71,7 +77,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_MALLOC_LEN (1024*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200 @@ -112,6 +118,9 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP +#ifdef CONFIG_KB9202B +#define CONFIG_CMD_NAND +#endif #define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_BDI
Dear Matthias Kaehlcke,
In message 20090604185024.GB4398@darwin you wrote:
thanks for your explication, below is the driver in the corresponding directory
--
Suchg comment is supposed to go *below* the "--" line, not above.
Add NAND support for the KwikByte KB9202
And such a commit message must go *above* the "--" line, not below.
Also, it would be nice if you added some version information (like "[PATCH 2/2 v3]" in the Subject: line, and summarize the changes between versions below the "--" line.
Thanks.
Best regards,
Wolfgang Denk
Add NAND support for the KwikByte KB9202
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
--
Changes:
- moved driver to drivers/mtd/nand/ - use i/o accessors - don't check for ATL custom board - removed unnecessary cast - don't use magic numbers
drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/kb9202_nand.c | 151 ++++++++++++++++++++++++++ include/asm-arm/arch-at91rm9200/AT91RM9200.h | 2 + include/configs/kb9202.h | 11 ++- 4 files changed, 164 insertions(+), 1 deletions(-) create mode 100644 drivers/mtd/nand/kb9202_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 471cd6b..d2f3e61 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -44,6 +44,7 @@ COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o endif
COBJS := $(COBJS-y) diff --git a/drivers/mtd/nand/kb9202_nand.c b/drivers/mtd/nand/kb9202_nand.c new file mode 100644 index 0000000..7db8d7c --- /dev/null +++ b/drivers/mtd/nand/kb9202_nand.c @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2006 + * KwikByte kb9200_dev@kwikbyte.com + * + * (C) Copyright 2009 + * Matthias Kaehlcke matthias@kaehlcke.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/AT91RM9200.h> +#include <asm/arch/hardware.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ + +#define MASK_ALE (1 << 22) /* our ALE is A22 */ +#define MASK_CLE (1 << 21) /* our CLE is A21 */ + +#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ +#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ + +#define KB9202_SMC2_NWS (1 << 2) +#define KB9202_SMC2_TDF (1 << 8) +#define KB9202_SMC2_RWSETUP (1 << 24) +#define KB9202_SMC2_RWHOLD (1 << 29) + +/* + * Board-specific function to access device control signals + */ +static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + /* clear ALE and CLE bits */ + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (ctrl & NAND_NCE) + writel(KB9202_NAND_NCE, AT91C_PIOC_CODR); + else + writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + + +/* + * Board-specific function to access the device ready signal. + */ +static int kb9202_nand_ready(struct mtd_info *mtd) +{ + return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY; +} + + +/* + * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference. + * + * struct nand_chip - NAND Private Flash Chip Data + * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device + * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device + * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line + * If set to NULL no access to ready/busy is available and the ready/busy information + * is read from the chip status register + * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only + * be provided if a hardware ECC is available + * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines + * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) + * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about + * special functionality. See the defines for further explanation +*/ +/* + * This routine initializes controller and GPIOs. + */ +int board_nand_init(struct nand_chip *nand) +{ + unsigned int value; + + nand->ecc.mode = NAND_ECC_SOFT; + nand->options &= ~NAND_BUSWIDTH_16; + nand->cmd_ctrl = kb9202_nand_hwcontrol; + nand->dev_ready = kb9202_nand_ready; + + /* in case running outside of bootloader */ + writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER); + + /* setup nand flash access (allow ample margin) */ + /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */ + writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF | + AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD, + AT91C_SMC_CSR3); + + /* enable internal NAND controller */ + value = readl(AT91C_EBI_CSA); + value |= AT91C_EBI_CS3A_SMC_SmartMedia; + writel(value, AT91C_EBI_CSA); + + /* enable SMOE/SMWE */ + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR); + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR); + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER); + + /* set NCE to high */ + writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); + + /* disable output on pin connected to the busy line of the NAND */ + writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR); + + /* enable the PIO to control NCE and BUSY */ + writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER); + + /* enable output for NCE */ + writel(KB9202_NAND_NCE, AT91C_PIOC_OER); + + return (0); +} diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 00bae1c..aaab2c2 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -737,6 +737,7 @@ typedef struct _AT91S_PDC #define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ #define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) /* (PIOC) PIO Output Enable Register */ #define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ #define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ #define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ @@ -780,6 +781,7 @@ typedef struct _AT91S_PDC #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ +#define AT91C_SMC_CSR3 ((AT91_REG *) 0xFFFFFF7C) /* (SMC) Chip Select Register 3 */
#else /* flash */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 8651e53..c51845e 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -62,6 +62,12 @@ #ifdef CONFIG_KB9202B #define CONFIG_BOOTARGS "console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M" #define CONFIG_BOOTCOMMAND "bootm 0x10000000" +#define CONFIG_NAND_KB9202 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_CMDLINE #endif
@@ -71,7 +77,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_MALLOC_LEN (1024*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200 @@ -112,6 +118,9 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP +#ifdef CONFIG_KB9202B +#define CONFIG_CMD_NAND +#endif #define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_BDI
On Thu, Jun 11, 2009 at 08:46:54PM +0200, Matthias Kaehlcke wrote:
Add NAND support for the KwikByte KB9202
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
--
The git separator is three dashes, not two.
Changes:
- moved driver to drivers/mtd/nand/
- use i/o accessors
- don't check for ATL custom board
- removed unnecessary cast
- don't use magic numbers
drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/kb9202_nand.c | 151 ++++++++++++++++++++++++++ include/asm-arm/arch-at91rm9200/AT91RM9200.h | 2 + include/configs/kb9202.h | 11 ++-
I get conflicts in kb9202.h. Is this against an arch tree, or does it need to be respun?
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 471cd6b..d2f3e61 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -44,6 +44,7 @@ COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o +COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
Wolfgang likes these things kept in alphabetical order.
+int board_nand_init(struct nand_chip *nand) +{
- unsigned int value;
- nand->ecc.mode = NAND_ECC_SOFT;
- nand->options &= ~NAND_BUSWIDTH_16;
Why would you need to clear this? It's the board driver that sets it in the first place (if applicable).
- /* setup nand flash access (allow ample margin) */
- /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
- writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF |
AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD,AT91C_SMC_CSR3);
Line length. Did you perhaps use a tab size other than 8?
Otherwise, ACK.
-Scott
Add NAND support for the KwikByte KB9202
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
---
El Tue, Jun 23, 2009 at 04:19:40PM -0500 Scott Wood ha dit:
I get conflicts in kb9202.h. Is this against an arch tree, or does it need to be respun?
The previous patches were against v2009-03, as i had problems building the current git head for the kb9202 when i started working on the patch. Did you apply the first patch of this series when you got the conflict? This patch is based on the current HEAD.
Changes regarding v4: * put KB9202 entry in the Makefile at the correct position (alphabetical order) * removed superfluous clear of NAND_BUSWIDTH_16 flag * fixed line length/broken indentation
drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/kb9202_nand.c | 150 ++++++++++++++++++++++++++ include/asm-arm/arch-at91rm9200/AT91RM9200.h | 2 + include/configs/kb9202.h | 11 ++- 4 files changed, 163 insertions(+), 1 deletions(-) create mode 100644 drivers/mtd/nand/kb9202_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 71dd5b9..d2bd558 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o +COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c diff --git a/drivers/mtd/nand/kb9202_nand.c b/drivers/mtd/nand/kb9202_nand.c new file mode 100644 index 0000000..b8f46fa --- /dev/null +++ b/drivers/mtd/nand/kb9202_nand.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2006 + * KwikByte kb9200_dev@kwikbyte.com + * + * (C) Copyright 2009 + * Matthias Kaehlcke matthias@kaehlcke.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/AT91RM9200.h> +#include <asm/arch/hardware.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ + +#define MASK_ALE (1 << 22) /* our ALE is A22 */ +#define MASK_CLE (1 << 21) /* our CLE is A21 */ + +#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ +#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ + +#define KB9202_SMC2_NWS (1 << 2) +#define KB9202_SMC2_TDF (1 << 8) +#define KB9202_SMC2_RWSETUP (1 << 24) +#define KB9202_SMC2_RWHOLD (1 << 29) + +/* + * Board-specific function to access device control signals + */ +static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + /* clear ALE and CLE bits */ + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (ctrl & NAND_NCE) + writel(KB9202_NAND_NCE, AT91C_PIOC_CODR); + else + writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + + +/* + * Board-specific function to access the device ready signal. + */ +static int kb9202_nand_ready(struct mtd_info *mtd) +{ + return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY; +} + + +/* + * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference. + * + * struct nand_chip - NAND Private Flash Chip Data + * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device + * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device + * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line + * If set to NULL no access to ready/busy is available and the ready/busy information + * is read from the chip status register + * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only + * be provided if a hardware ECC is available + * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines + * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) + * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about + * special functionality. See the defines for further explanation +*/ +/* + * This routine initializes controller and GPIOs. + */ +int board_nand_init(struct nand_chip *nand) +{ + unsigned int value; + + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = kb9202_nand_hwcontrol; + nand->dev_ready = kb9202_nand_ready; + + /* in case running outside of bootloader */ + writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER); + + /* setup nand flash access (allow ample margin) */ + /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */ + writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF | + AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD, + AT91C_SMC_CSR3); + + /* enable internal NAND controller */ + value = readl(AT91C_EBI_CSA); + value |= AT91C_EBI_CS3A_SMC_SmartMedia; + writel(value, AT91C_EBI_CSA); + + /* enable SMOE/SMWE */ + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR); + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR); + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER); + + /* set NCE to high */ + writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); + + /* disable output on pin connected to the busy line of the NAND */ + writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR); + + /* enable the PIO to control NCE and BUSY */ + writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER); + + /* enable output for NCE */ + writel(KB9202_NAND_NCE, AT91C_PIOC_OER); + + return (0); +} diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 00bae1c..aaab2c2 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -737,6 +737,7 @@ typedef struct _AT91S_PDC #define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ #define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ #define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ +#define AT91C_PIOC_OER ((AT91_REG *) 0xFFFFF810) /* (PIOC) PIO Output Enable Register */ #define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ #define AT91C_PIOC_SODR ((AT91_REG *) 0xFFFFF830) /* (PIOC) Set Output Data Register */ #define AT91C_PIOC_CODR ((AT91_REG *) 0xFFFFF834) /* (PIOC) Clear Output Data Register */ @@ -780,6 +781,7 @@ typedef struct _AT91S_PDC #define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ +#define AT91C_SMC_CSR3 ((AT91_REG *) 0xFFFFFF7C) /* (SMC) Chip Select Register 3 */
#else /* flash */ diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 8651e53..c51845e 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -62,6 +62,12 @@ #ifdef CONFIG_KB9202B #define CONFIG_BOOTARGS "console=ttyS0,115200 noinitrd root=/dev/mtdblock0 rootfstype=jffs2 mem=64M" #define CONFIG_BOOTCOMMAND "bootm 0x10000000" +#define CONFIG_NAND_KB9202 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_CMDLINE #endif
@@ -71,7 +77,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_MALLOC_LEN (1024*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CONFIG_BAUDRATE 115200 @@ -112,6 +118,9 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP +#ifdef CONFIG_KB9202B +#define CONFIG_CMD_NAND +#endif #define CONFIG_CMD_JFFS2
#undef CONFIG_CMD_BDI
On Wed, Jun 24, 2009 at 05:23:05PM +0200, Matthias Kaehlcke wrote:
Add NAND support for the KwikByte KB9202
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
El Tue, Jun 23, 2009 at 04:19:40PM -0500 Scott Wood ha dit:
I get conflicts in kb9202.h. Is this against an arch tree, or does it need to be respun?
The previous patches were against v2009-03, as i had problems building the current git head for the kb9202 when i started working on the patch. Did you apply the first patch of this series when you got the conflict? This patch is based on the current HEAD.
No - if it depends on other patches that go through an arch tree, then this patch should go through that tree as well.
Acked-by: Scott Wood scottwood@freescale.com
-Scott
On 15:51 Wed 24 Jun , Scott Wood wrote:
On Wed, Jun 24, 2009 at 05:23:05PM +0200, Matthias Kaehlcke wrote:
Add NAND support for the KwikByte KB9202
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
El Tue, Jun 23, 2009 at 04:19:40PM -0500 Scott Wood ha dit:
I get conflicts in kb9202.h. Is this against an arch tree, or does it need to be respun?
The previous patches were against v2009-03, as i had problems building the current git head for the kb9202 when i started working on the patch. Did you apply the first patch of this series when you got the conflict? This patch is based on the current HEAD.
No - if it depends on other patches that go through an arch tree, then this patch should go through that tree as well.
Acked-by: Scott Wood scottwood@freescale.com
Scott I've not follow this patch but for the arm part it's looks fine so I'll let you handle
Best Regards, J.
On Sun, Jul 12, 2009 at 09:57:13PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:51 Wed 24 Jun , Scott Wood wrote:
On Wed, Jun 24, 2009 at 05:23:05PM +0200, Matthias Kaehlcke wrote:
Add NAND support for the KwikByte KB9202
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
El Tue, Jun 23, 2009 at 04:19:40PM -0500 Scott Wood ha dit:
I get conflicts in kb9202.h. Is this against an arch tree, or does it need to be respun?
The previous patches were against v2009-03, as i had problems building the current git head for the kb9202 when i started working on the patch. Did you apply the first patch of this series when you got the conflict? This patch is based on the current HEAD.
No - if it depends on other patches that go through an arch tree, then this patch should go through that tree as well.
Acked-by: Scott Wood scottwood@freescale.com
Scott I've not follow this patch but for the arm part it's looks fine so I'll let you handle
It still does not apply to the current tree, so I cannot accept it as is.
The NAND tree is not an appropriate route for unrelated changes to a board config file (such as CONFIG_BOOTARGS/CONFIG_BOOTCOMMAND) to go -- and even if it were, I don't have an easily applyable version of patch 1/2 (the mailing list archives mangle things).
Matthias, can you resend a patch that just adds the NAND driver (for me), and a separate patch that just touches the board config (for the arch tree)?
-Scott
Add KB9202 NAND driver
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
---
El Thu, Jul 16, 2009 at 01:45:57PM -0500 Scott Wood ha dit:
On Sun, Jul 12, 2009 at 09:57:13PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:51 Wed 24 Jun , Scott Wood wrote:
On Wed, Jun 24, 2009 at 05:23:05PM +0200, Matthias Kaehlcke wrote:
Add NAND support for the KwikByte KB9202
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
El Tue, Jun 23, 2009 at 04:19:40PM -0500 Scott Wood ha dit:
I get conflicts in kb9202.h. Is this against an arch tree, or does it need to be respun?
The previous patches were against v2009-03, as i had problems building the current git head for the kb9202 when i started working on the patch. Did you apply the first patch of this series when you got the conflict? This patch is based on the current HEAD.
No - if it depends on other patches that go through an arch tree, then this patch should go through that tree as well.
Acked-by: Scott Wood scottwood@freescale.com
Scott I've not follow this patch but for the arm part it's looks fine so I'll let you handle
It still does not apply to the current tree, so I cannot accept it as is.
The NAND tree is not an appropriate route for unrelated changes to a board config file (such as CONFIG_BOOTARGS/CONFIG_BOOTCOMMAND) to go -- and even if it were, I don't have an easily applyable version of patch 1/2 (the mailing list archives mangle things).
Matthias, can you resend a patch that just adds the NAND driver (for me), and a separate patch that just touches the board config (for the arch tree)?
ok, here is a patch that only adds the NAND driver. i'll prepare a board config patch after my first patch has hit mainline to avoid further confusion :)
changes regarding v5:
* only add the NAND driver, without touching the board configuration
drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/kb9202_nand.c | 150 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 151 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/kb9202_nand.c
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index a5680e8..aab3b70 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o +COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o diff --git a/drivers/mtd/nand/kb9202_nand.c b/drivers/mtd/nand/kb9202_nand.c new file mode 100644 index 0000000..b8f46fa --- /dev/null +++ b/drivers/mtd/nand/kb9202_nand.c @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2006 + * KwikByte kb9200_dev@kwikbyte.com + * + * (C) Copyright 2009 + * Matthias Kaehlcke matthias@kaehlcke.net + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/AT91RM9200.h> +#include <asm/arch/hardware.h> + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ + +#define MASK_ALE (1 << 22) /* our ALE is A22 */ +#define MASK_CLE (1 << 21) /* our CLE is A21 */ + +#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */ +#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */ + +#define KB9202_SMC2_NWS (1 << 2) +#define KB9202_SMC2_TDF (1 << 8) +#define KB9202_SMC2_RWSETUP (1 << 24) +#define KB9202_SMC2_RWHOLD (1 << 29) + +/* + * Board-specific function to access device control signals + */ +static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + /* clear ALE and CLE bits */ + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (ctrl & NAND_NCE) + writel(KB9202_NAND_NCE, AT91C_PIOC_CODR); + else + writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + + +/* + * Board-specific function to access the device ready signal. + */ +static int kb9202_nand_ready(struct mtd_info *mtd) +{ + return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY; +} + + +/* + * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference. + * + * struct nand_chip - NAND Private Flash Chip Data + * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device + * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device + * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines + * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line + * If set to NULL no access to ready/busy is available and the ready/busy information + * is read from the chip status register + * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only + * be provided if a hardware ECC is available + * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines + * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) + * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about + * special functionality. See the defines for further explanation +*/ +/* + * This routine initializes controller and GPIOs. + */ +int board_nand_init(struct nand_chip *nand) +{ + unsigned int value; + + nand->ecc.mode = NAND_ECC_SOFT; + nand->cmd_ctrl = kb9202_nand_hwcontrol; + nand->dev_ready = kb9202_nand_ready; + + /* in case running outside of bootloader */ + writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER); + + /* setup nand flash access (allow ample margin) */ + /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */ + writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF | + AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD, + AT91C_SMC_CSR3); + + /* enable internal NAND controller */ + value = readl(AT91C_EBI_CSA); + value |= AT91C_EBI_CS3A_SMC_SmartMedia; + writel(value, AT91C_EBI_CSA); + + /* enable SMOE/SMWE */ + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR); + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR); + writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER); + + /* set NCE to high */ + writel(KB9202_NAND_NCE, AT91C_PIOC_SODR); + + /* disable output on pin connected to the busy line of the NAND */ + writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR); + + /* enable the PIO to control NCE and BUSY */ + writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER); + + /* enable output for NCE */ + writel(KB9202_NAND_NCE, AT91C_PIOC_OER); + + return (0); +}
On Thu, Jul 16, 2009 at 09:19:29PM +0200, Matthias Kaehlcke wrote:
Add KB9202 NAND driver
Signed-off-by: Matthias Kaehlcke matthias@kaehlcke.net
Applied to u-boot-nand-flash/next.
-Scott
participants (5)
-
Jean-Christophe PLAGNIOL-VILLARD -
Matthias Kaehlcke -
Scott Wood -
Stefan Roese -
Wolfgang Denk