[U-Boot] [PATCH 00/10] ARC: updates, fixes & preparation to ARCv2 submission
This series is focused on fixes and clean-up in ARC-related code. The most visible changes are: 1. Move lots of sources in "lib" folder because they are arch-independent 2. Rename (generalize) "arc700" -> "arcv1" because we'll have another type of ARC CPUs soon as well as more flavours of existing family 3. Interrupt vector table is separated in its own section which is required for upcoing submission of ARCv2 support
Also some minor fixes were done to existing code.
Alexey Brodkin (6): arc: add dependences on MMU presence arc: relocate - minor refactoring and clean-up arc: move linker script in arch/arc/cpu folder arc: move common sources in library board/synopsys: remove selection of CPU from the board arc: rename "arc700" in "arcv1"
Igor Guryanov (4): arc: check caches existence before use arc: add ECR (exception cause register) output arc: interrupts - fix mask setup arc: introduce separate section for interrupt vector table
arch/arc/Kconfig | 3 + arch/arc/Makefile | 2 - arch/arc/config.mk | 4 ++ arch/arc/cpu/arc700/Makefile | 13 ---- arch/arc/cpu/{arc700/config.mk => arcv1/Makefile} | 2 +- arch/arc/cpu/{arc700 => arcv1}/config.mk | 0 arch/arc/cpu/{arc700 => arcv1}/start.S | 77 +++++++++++++---------- arch/arc/cpu/{arc700 => }/u-boot.lds | 15 ++++- arch/arc/include/asm/arcregs.h | 2 + arch/arc/include/asm/sections.h | 3 + arch/arc/lib/Makefile | 6 ++ arch/arc/{cpu/arc700 => lib}/cache.c | 29 +++++++++ arch/arc/{cpu/arc700 => lib}/cpu.c | 0 arch/arc/{cpu/arc700 => lib}/interrupts.c | 3 +- arch/arc/lib/relocate.c | 19 ++---- arch/arc/{cpu/arc700 => lib}/reset.c | 0 arch/arc/lib/sections.c | 2 + arch/arc/{cpu/arc700 => lib}/timer.c | 0 board/synopsys/Kconfig | 6 -- board/synopsys/axs101/Kconfig | 3 - 20 files changed, 117 insertions(+), 72 deletions(-) delete mode 100644 arch/arc/cpu/arc700/Makefile copy arch/arc/cpu/{arc700/config.mk => arcv1/Makefile} (80%) rename arch/arc/cpu/{arc700 => arcv1}/config.mk (100%) rename arch/arc/cpu/{arc700 => arcv1}/start.S (87%) rename arch/arc/cpu/{arc700 => }/u-boot.lds (88%) rename arch/arc/{cpu/arc700 => lib}/cache.c (79%) rename arch/arc/{cpu/arc700 => lib}/cpu.c (100%) rename arch/arc/{cpu/arc700 => lib}/interrupts.c (97%) rename arch/arc/{cpu/arc700 => lib}/reset.c (100%) rename arch/arc/{cpu/arc700 => lib}/timer.c (100%)
From: Igor Guryanov guryanov@synopsys.com
Some cache operations ({i|d}cache_{enable|disable|status} or flush_dcache_all) are built and used even if CONFIG_SYS_{I|D}CACHE_OFF is set.
This is required for force disable of caches on early boot. What if something was executed before U-boot and enabled caches (low-level bootloaders, previously run kernel etc.)?
But if CPU doesn't really have caches any attempt to access cache-related AUX registers triggers instruction error exception.
So for convenience we'll try to avoid exceptions by checking if CPU actually has caches (we check separately data and instruction cache existence) at all.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com Signed-off-by: Igor Guryanov guryanov@synopsys.com --- arch/arc/cpu/arc700/cache.c | 29 +++++++++++++++++++++++++++++ arch/arc/include/asm/arcregs.h | 2 ++ 2 files changed, 31 insertions(+)
diff --git a/arch/arc/cpu/arc700/cache.c b/arch/arc/cpu/arc700/cache.c index 39d522d..fa19a13 100644 --- a/arch/arc/cpu/arc700/cache.c +++ b/arch/arc/cpu/arc700/cache.c @@ -14,21 +14,34 @@ #define DC_CTRL_CACHE_DISABLE (1 << 0) #define DC_CTRL_INV_MODE_FLUSH (1 << 6) #define DC_CTRL_FLUSH_STATUS (1 << 8) +#define CACHE_VER_NUM_MASK 0xF
int icache_status(void) { + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)) + return 0; + return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) != IC_CTRL_CACHE_DISABLE; }
void icache_enable(void) { + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)) + return; + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & ~IC_CTRL_CACHE_DISABLE); }
void icache_disable(void) { + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK)) + return; + write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | IC_CTRL_CACHE_DISABLE); } @@ -43,24 +56,40 @@ void invalidate_icache_all(void)
int dcache_status(void) { + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)) + return 0; + return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) != DC_CTRL_CACHE_DISABLE; }
void dcache_enable(void) { + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)) + return; + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE)); }
void dcache_disable(void) { + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)) + return; + write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | DC_CTRL_CACHE_DISABLE); }
void flush_dcache_all(void) { + /* If no cache in CPU exit immediately */ + if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK)) + return; + /* Do flush of entire cache */ write_aux_reg(ARC_AUX_DC_FLSH, 1);
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 5d48d11..8ace87f 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -24,6 +24,7 @@ #if (CONFIG_ARC_MMU_VER > 2) #define ARC_AUX_IC_PTAG 0x1E #endif +#define ARC_BCR_IC_BUILD 0x77
/* Timer related auxiliary registers */ #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ @@ -42,6 +43,7 @@ #if (CONFIG_ARC_MMU_VER > 2) #define ARC_AUX_DC_PTAG 0x5C #endif +#define ARC_BCR_DC_BUILD 0x72
#ifndef __ASSEMBLY__ /* Accessors for auxiliary registers */
From: Igor Guryanov guryanov@synopsys.com
Exception cause register (ECR) contains value that describes a reason for exception that has happened. This helps a lot to figure-out what went wrong.
Now we print this register contents when dumping registers.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com Signed-off-by: Igor Guryanov guryanov@synopsys.com --- arch/arc/cpu/arc700/interrupts.c | 1 + arch/arc/cpu/arc700/start.S | 10 ++++++---- 2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arc/cpu/arc700/interrupts.c b/arch/arc/cpu/arc700/interrupts.c index d93a6eb..7dde74b 100644 --- a/arch/arc/cpu/arc700/interrupts.c +++ b/arch/arc/cpu/arc700/interrupts.c @@ -61,6 +61,7 @@ static void print_reg_file(long *reg_rev, int start_num)
void show_regs(struct pt_regs *regs) { + printf("ECR:\t0x%08lx\n", regs->ecr); printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n", regs->ret, regs->blink, regs->status32); printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25); diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arc700/start.S index 563513b..4d505bf 100644 --- a/arch/arc/cpu/arc700/start.S +++ b/arch/arc/cpu/arc700/start.S @@ -57,11 +57,13 @@ .endm
.macro SAVE_ALL_SYS - + /* saving %r0 to reg->r0 in advance since we read %ecr into it */ + st %r0, [%sp, -8] + lr %r0, [%ecr] /* all stack addressing is manual so far */ st %r0, [%sp] - lr %r0, [%ecr] - st %r0, [%sp, 8] /* ECR */ - st %sp, [%sp, 4] + st %sp, [%sp, -4] + /* now move %sp to reg->r0 position so we can do "push" automatically */ + sub %sp, %sp, 8
SAVE_R1_TO_R24 PUSH %r25
From: Igor Guryanov guryanov@synopsys.com
To disable interrupts we need to reset corresponding flags in STATUS32 register. For this we need to OR flags for interrupts level1 and level2 and then AND with current value in STATUS32.
Before that implementation was incorrect.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com Signed-off-by: Igor Guryanov guryanov@synopsys.com --- arch/arc/cpu/arc700/interrupts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arc/cpu/arc700/interrupts.c b/arch/arc/cpu/arc700/interrupts.c index 7dde74b..d7cab3b 100644 --- a/arch/arc/cpu/arc700/interrupts.c +++ b/arch/arc/cpu/arc700/interrupts.c @@ -23,7 +23,7 @@ int interrupt_init(void) int disable_interrupts(void) { int status = read_aux_reg(ARC_AUX_STATUS32); - int state = (status | E1_MASK | E2_MASK) ? 1 : 0; + int state = (status & (E1_MASK | E2_MASK)) ? 1 : 0;
status &= ~(E1_MASK | E2_MASK); /* STATUS32 register is updated indirectly with "FLAG" instruction */
Depending on MMU presence in CPU there're differences in HW behavior. For example address of instruction that caused exception is put in ECR register if MMU exists and in ERET register otherwise.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com Signed-off-by: Igor Guryanov guryanov@synopsys.com --- arch/arc/config.mk | 4 ++++ arch/arc/cpu/arc700/start.S | 18 ++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/arch/arc/config.mk b/arch/arc/config.mk index e408800..5321987 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -21,6 +21,10 @@ ifeq ($(CROSS_COMPILE),) CROSS_COMPILE := $(ARC_CROSS_COMPILE) endif
+ifdef CONFIG_ARC_MMU_VER +CONFIG_MMU = 1 +endif + PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2
# Needed for relocation diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arc700/start.S index 4d505bf..2318282 100644 --- a/arch/arc/cpu/arc700/start.S +++ b/arch/arc/cpu/arc700/start.S @@ -78,6 +78,16 @@ PUSHAX %erbta .endm
+.macro SAVE_EXCEPTION_SOURCE +#ifdef CONFIG_MMU + /* If MMU exists exception faulting address is loaded in EFA reg */ + lr %r0, [%efa] +#else + /* Otherwise in ERET (exception return) reg */ + lr %r0, [%eret] +#endif +.endm + .align 4 .globl _start _start: @@ -102,13 +112,13 @@ _start:
memory_error: SAVE_ALL_SYS - lr %r0, [%efa] + SAVE_EXCEPTION_SOURCE mov %r1, %sp j do_memory_error
instruction_error: SAVE_ALL_SYS - lr %r0, [%efa] + SAVE_EXCEPTION_SOURCE mov %r1, %sp j do_instruction_error
@@ -119,7 +129,7 @@ interrupt_handler:
EV_MachineCheck: SAVE_ALL_SYS - lr %r0, [%efa] + SAVE_EXCEPTION_SOURCE mov %r1, %sp j do_machine_check_fault
@@ -135,7 +145,7 @@ EV_TLBMissD:
EV_TLBProtV: SAVE_ALL_SYS - lr %r0, [%efa] + SAVE_EXCEPTION_SOURCE mov %r1, %sp j do_tlb_prot_violation
From: Igor Guryanov guryanov@synopsys.com
Even though existing implementation works fine in preparation to submission of ARCv2 architecture we need this change.
In case of ARCv2 interrupt vector table consists of just addresses of corresponding handlers. And if those addresses will be in .text section then assembler will encode them as everything in .text section as middle-endian and then on real execution CPU will read swapped addresses and will jump into the wild.
Once introduced new section is situated so .text section remains the first which allows us to use common linker option for linking everything to a specified CONFIG_SYS_TEXT_BASE.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com Signed-off-by: Igor Guryanov guryanov@synopsys.com --- arch/arc/Makefile | 2 -- arch/arc/cpu/arc700/Makefile | 3 +-- arch/arc/cpu/arc700/start.S | 49 +++++++++++++++++++++-------------------- arch/arc/cpu/arc700/u-boot.lds | 15 ++++++++++++- arch/arc/include/asm/sections.h | 2 ++ arch/arc/lib/relocate.c | 4 ++-- arch/arc/lib/sections.c | 2 ++ 7 files changed, 46 insertions(+), 31 deletions(-)
diff --git a/arch/arc/Makefile b/arch/arc/Makefile index de25cc9..374432d 100644 --- a/arch/arc/Makefile +++ b/arch/arc/Makefile @@ -2,7 +2,5 @@ # SPDX-License-Identifier: GPL-2.0+ #
-head-y := arch/arc/cpu/$(CPU)/start.o - libs-y += arch/arc/cpu/$(CPU)/ libs-y += arch/arc/lib/ diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arc700/Makefile index cdc5002..021e3a2 100644 --- a/arch/arc/cpu/arc700/Makefile +++ b/arch/arc/cpu/arc700/Makefile @@ -4,10 +4,9 @@ # SPDX-License-Identifier: GPL-2.0+ #
-extra-y += start.o - obj-y += cache.o obj-y += cpu.o obj-y += interrupts.o obj-y += reset.o +obj-y += start.o obj-y += timer.o diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arc700/start.S index 2318282..01cfba4 100644 --- a/arch/arc/cpu/arc700/start.S +++ b/arch/arc/cpu/arc700/start.S @@ -88,11 +88,11 @@ #endif .endm
+.section .ivt, "ax",@progbits .align 4 -.globl _start -_start: +_ivt: /* Critical system events */ - j reset /* 0 - 0x000 */ + j _start /* 0 - 0x000 */ j memory_error /* 1 - 0x008 */ j instruction_error /* 2 - 0x010 */
@@ -110,6 +110,28 @@ _start: j EV_Trap /* 0x128, Trap exception (0x25) */ j EV_Extension /* 0x130, Extn Intruction Excp (0x26) */
+.text +.globl _start +_start: + /* Setup interrupt vector base that matches "__text_start" */ + sr __ivt_start, [ARC_AUX_INTR_VEC_BASE] + + /* Setup stack pointer */ + mov %sp, CONFIG_SYS_INIT_SP_ADDR + mov %fp, %sp + + /* Clear bss */ + mov %r0, __bss_start + mov %r1, __bss_end + +clear_bss: + st.ab 0, [%r0, 4] + brlt %r0, %r1, clear_bss + + /* Zero the one and only argument of "board_init_f" */ + mov_s %r0, 0 + j board_init_f + memory_error: SAVE_ALL_SYS SAVE_EXCEPTION_SOURCE @@ -164,27 +186,6 @@ EV_Extension: mov %r0, %sp j do_extension
- -reset: - /* Setup interrupt vector base that matches "__text_start" */ - sr __text_start, [ARC_AUX_INTR_VEC_BASE] - - /* Setup stack pointer */ - mov %sp, CONFIG_SYS_INIT_SP_ADDR - mov %fp, %sp - - /* Clear bss */ - mov %r0, __bss_start - mov %r1, __bss_end - -clear_bss: - st.ab 0, [%r0, 4] - brlt %r0, %r1, clear_bss - - /* Zero the one and only argument of "board_init_f" */ - mov_s %r0, 0 - j board_init_f - /* * void relocate_code (addr_sp, gd, addr_moni) * diff --git a/arch/arc/cpu/arc700/u-boot.lds b/arch/arc/cpu/arc700/u-boot.lds index 2d01b21..e548dc3 100644 --- a/arch/arc/cpu/arc700/u-boot.lds +++ b/arch/arc/cpu/arc700/u-boot.lds @@ -13,7 +13,6 @@ SECTIONS .text : { *(.__text_start) *(.__image_copy_start) - CPUDIR/start.o (.text*) *(.text*) }
@@ -23,6 +22,20 @@ SECTIONS *(.__text_end) }
+ . = ALIGN(1024); + .ivt_start : { + *(.__ivt_start) + } + + .ivt : + { + *(.ivt) + } + + .ivt_end : { + *(.__ivt_end) + } + . = ALIGN(4); .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h index 18484a1..2a7a987 100644 --- a/arch/arc/include/asm/sections.h +++ b/arch/arc/include/asm/sections.h @@ -10,5 +10,7 @@ #include <asm-generic/sections.h>
extern ulong __text_end; +extern ulong __ivt_start; +extern ulong __ivt_end;
#endif /* __ASM_ARC_SECTIONS_H */ diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c index 2482bcd..5618b6a 100644 --- a/arch/arc/lib/relocate.c +++ b/arch/arc/lib/relocate.c @@ -44,7 +44,7 @@ int do_elf_reloc_fixups(void) #ifdef __LITTLE_ENDIAN__ /* If location in ".text" section swap value */ if ((unsigned int)offset_ptr_rom < - (unsigned int)&__text_end) + (unsigned int)&__ivt_end) val = (val << 16) | (val >> 16); #endif
@@ -55,7 +55,7 @@ int do_elf_reloc_fixups(void) #ifdef __LITTLE_ENDIAN__ /* If location in ".text" section swap value */ if ((unsigned int)offset_ptr_rom < - (unsigned int)&__text_end) + (unsigned int)&__ivt_end) val = (val << 16) | (val >> 16); #endif memcpy(offset_ptr_ram, &val, sizeof(int)); diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c index b0b46a4..a72c694 100644 --- a/arch/arc/lib/sections.c +++ b/arch/arc/lib/sections.c @@ -19,3 +19,5 @@ char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); char __text_start[0] __attribute__((section(".__text_start"))); char __text_end[0] __attribute__((section(".__text_end"))); char __init_end[0] __attribute__((section(".__init_end"))); +char __ivt_start[0] __attribute__((section(".__ivt_start"))); +char __ivt_end[0] __attribute__((section(".__ivt_end")));
* use better symbols for relocatable region boundaries ("__image_copy_start" instead of "CONFIG_SYS_TEXT_BASE") * remove useless debug messages because they will only show up in case of both problem (when normal "if" branch won't be taken) and DEBUG take place which is pretty rare situation.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com --- arch/arc/include/asm/sections.h | 1 + arch/arc/lib/relocate.c | 15 ++++----------- 2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h index 2a7a987..b8f2a85 100644 --- a/arch/arc/include/asm/sections.h +++ b/arch/arc/include/asm/sections.h @@ -12,5 +12,6 @@ extern ulong __text_end; extern ulong __ivt_start; extern ulong __ivt_end; +extern ulong __image_copy_start;
#endif /* __ASM_ARC_SECTIONS_H */ diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c index 5618b6a..7797782 100644 --- a/arch/arc/lib/relocate.c +++ b/arch/arc/lib/relocate.c @@ -26,7 +26,7 @@ int do_elf_reloc_fixups(void) offset_ptr_rom = (Elf32_Addr *)re_src->r_offset;
/* Check that the location of the relocation is in .text */ - if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE && + if (offset_ptr_rom >= (Elf32_Addr *)&__image_copy_start && offset_ptr_rom > last_offset) { unsigned int val; /* Switch to the in-RAM version */ @@ -48,9 +48,9 @@ int do_elf_reloc_fixups(void) val = (val << 16) | (val >> 16); #endif
- /* Check that the target points into .text */ - if (val >= CONFIG_SYS_TEXT_BASE && val <= - (unsigned int)&__bss_end) { + /* Check that the target points into executable */ + if (val >= (unsigned int)&__image_copy_start && val <= + (unsigned int)&__image_copy_end) { val += gd->reloc_off; #ifdef __LITTLE_ENDIAN__ /* If location in ".text" section swap value */ @@ -59,14 +59,7 @@ int do_elf_reloc_fixups(void) val = (val << 16) | (val >> 16); #endif memcpy(offset_ptr_ram, &val, sizeof(int)); - } else { - debug(" %p: rom reloc %x, ram %p, value %x, limit %x\n", - re_src, re_src->r_offset, offset_ptr_ram, - val, (unsigned int)&__bss_end); } - } else { - debug(" %p: rom reloc %x, last %p\n", re_src, - re_src->r_offset, last_offset); } last_offset = offset_ptr_rom;
This way we'll be able to use the same one script for either ARC CPU.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com --- arch/arc/cpu/{arc700 => }/u-boot.lds | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename arch/arc/cpu/{arc700 => }/u-boot.lds (100%)
diff --git a/arch/arc/cpu/arc700/u-boot.lds b/arch/arc/cpu/u-boot.lds similarity index 100% rename from arch/arc/cpu/arc700/u-boot.lds rename to arch/arc/cpu/u-boot.lds
"reset.c" and "cpu.c" have no architecture-specific code at all. Others are applicable to either ARC CPU.
This change is a preparation to submission of ARCv2 architecture port.
Even though ARCv1 and ARCv2 ISAs are not binary compatible most of built-in modules still have the same programming model - AUX registers are mapped in the same addresses and hold the same data (new featues extend existing ones).
So only low-level assembly code (start-up, interrupt handlers) is left as CPU(actually ISA)-specific. This significantyl simplifies maintenance of multiple CPUs/ISAs.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com Signed-off-by: Igor Guryanov guryanov@synopsys.com --- arch/arc/cpu/arc700/Makefile | 7 +------ arch/arc/lib/Makefile | 6 ++++++ arch/arc/{cpu/arc700 => lib}/cache.c | 0 arch/arc/{cpu/arc700 => lib}/cpu.c | 0 arch/arc/{cpu/arc700 => lib}/interrupts.c | 0 arch/arc/{cpu/arc700 => lib}/reset.c | 0 arch/arc/{cpu/arc700 => lib}/timer.c | 0 7 files changed, 7 insertions(+), 6 deletions(-) rename arch/arc/{cpu/arc700 => lib}/cache.c (100%) rename arch/arc/{cpu/arc700 => lib}/cpu.c (100%) rename arch/arc/{cpu/arc700 => lib}/interrupts.c (100%) rename arch/arc/{cpu/arc700 => lib}/reset.c (100%) rename arch/arc/{cpu/arc700 => lib}/timer.c (100%)
diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arc700/Makefile index 021e3a2..3704ebe 100644 --- a/arch/arc/cpu/arc700/Makefile +++ b/arch/arc/cpu/arc700/Makefile @@ -4,9 +4,4 @@ # SPDX-License-Identifier: GPL-2.0+ #
-obj-y += cache.o -obj-y += cpu.o -obj-y += interrupts.o -obj-y += reset.o -obj-y += start.o -obj-y += timer.o +obj-y += start.o diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile index 7675f85..bae4419 100644 --- a/arch/arc/lib/Makefile +++ b/arch/arc/lib/Makefile @@ -4,6 +4,9 @@ # SPDX-License-Identifier: GPL-2.0+ #
+obj-y += cache.o +obj-y += cpu.o +obj-y += interrupts.o obj-y += sections.o obj-y += relocate.o obj-y += strchr-700.o @@ -13,4 +16,7 @@ obj-y += strlen.o obj-y += memcmp.o obj-y += memcpy-700.o obj-y += memset.o +obj-y += reset.o +obj-y += timer.o + obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/arc/cpu/arc700/cache.c b/arch/arc/lib/cache.c similarity index 100% rename from arch/arc/cpu/arc700/cache.c rename to arch/arc/lib/cache.c diff --git a/arch/arc/cpu/arc700/cpu.c b/arch/arc/lib/cpu.c similarity index 100% rename from arch/arc/cpu/arc700/cpu.c rename to arch/arc/lib/cpu.c diff --git a/arch/arc/cpu/arc700/interrupts.c b/arch/arc/lib/interrupts.c similarity index 100% rename from arch/arc/cpu/arc700/interrupts.c rename to arch/arc/lib/interrupts.c diff --git a/arch/arc/cpu/arc700/reset.c b/arch/arc/lib/reset.c similarity index 100% rename from arch/arc/cpu/arc700/reset.c rename to arch/arc/lib/reset.c diff --git a/arch/arc/cpu/arc700/timer.c b/arch/arc/lib/timer.c similarity index 100% rename from arch/arc/cpu/arc700/timer.c rename to arch/arc/lib/timer.c
Both ARCangel4 and AXS10x are FPGA-based boards so they may have different CPUs. For now we have only 1 option (ARC700) and we define this as default in arch Kconfig.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com --- arch/arc/Kconfig | 3 +++ board/synopsys/Kconfig | 6 ------ board/synopsys/axs101/Kconfig | 3 --- 3 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index d3ef58b..6a77b8f 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -4,6 +4,9 @@ menu "ARC architecture" config SYS_ARCH default "arc"
+config SYS_CPU + default "arc700" + choice prompt "Target select"
diff --git a/board/synopsys/Kconfig b/board/synopsys/Kconfig index a54d3df..f614f88 100644 --- a/board/synopsys/Kconfig +++ b/board/synopsys/Kconfig @@ -1,8 +1,5 @@ if TARGET_ARCANGEL4
-config SYS_CPU - default "arc700" - config SYS_VENDOR default "synopsys"
@@ -13,9 +10,6 @@ endif
if TARGET_ARCANGEL4_BE
-config SYS_CPU - default "arc700" - config SYS_VENDOR default "synopsys"
diff --git a/board/synopsys/axs101/Kconfig b/board/synopsys/axs101/Kconfig index 8448265..79e5400 100644 --- a/board/synopsys/axs101/Kconfig +++ b/board/synopsys/axs101/Kconfig @@ -1,8 +1,5 @@ if TARGET_AXS101
-config SYS_CPU - default "arc700" - config SYS_BOARD default "axs101"
As a preparation to ARCv2 port submission we rename "arc700" folder to "arcv1" which stands for ARCv1 ISA also known as ARCompact.
This will allow us to add more flavours of binary-compatible ARCv1 CPUs like ARC600 if needed later on and all required ARCv2 CPUs (which are binary incompatible with ARCv1) in "arcv2" folder in subsequent commits.
Signed-off-by: Alexey Brodkin abrodkin@synopsys.com Signed-off-by: Igor Guryanov guryanov@synopsys.com --- arch/arc/Kconfig | 2 +- arch/arc/cpu/{arc700 => arcv1}/Makefile | 0 arch/arc/cpu/{arc700 => arcv1}/config.mk | 0 arch/arc/cpu/{arc700 => arcv1}/start.S | 0 4 files changed, 1 insertion(+), 1 deletion(-) rename arch/arc/cpu/{arc700 => arcv1}/Makefile (100%) rename arch/arc/cpu/{arc700 => arcv1}/config.mk (100%) rename arch/arc/cpu/{arc700 => arcv1}/start.S (100%)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 6a77b8f..c6b1efe 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -5,7 +5,7 @@ config SYS_ARCH default "arc"
config SYS_CPU - default "arc700" + default "arcv1"
choice prompt "Target select" diff --git a/arch/arc/cpu/arc700/Makefile b/arch/arc/cpu/arcv1/Makefile similarity index 100% rename from arch/arc/cpu/arc700/Makefile rename to arch/arc/cpu/arcv1/Makefile diff --git a/arch/arc/cpu/arc700/config.mk b/arch/arc/cpu/arcv1/config.mk similarity index 100% rename from arch/arc/cpu/arc700/config.mk rename to arch/arc/cpu/arcv1/config.mk diff --git a/arch/arc/cpu/arc700/start.S b/arch/arc/cpu/arcv1/start.S similarity index 100% rename from arch/arc/cpu/arc700/start.S rename to arch/arc/cpu/arcv1/start.S
participants (1)
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Alexey Brodkin