From: Ye Li ye.li@nxp.com

The USDHC move the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN, HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec register. The driver uses RSTA to replace the clock gate off operation. But this is not a good solution. This is because: 1. when using RSTA, we should wait this bit to clear by itself. This is not implemeneted in the code. 2. After RSTA is set, it is recommended that the Host Driver reset the external card and reinitialize it.

So in this patch, we change to use the vendorspec registers for these bits operation.

Signed-off-by: Ye Li ye.li@nxp.com Signed-off-by: Peng Fan van.freenix@gmail.com Cc: York Sun york.sun@nxp.com Cc: Stefano Babic sbabic@denx.de Cc: Pantelis Antoniou panto@antoniou-consulting.com Cc: Fabio Estevam fabio.estevam@nxp.com ---

V2: Rebased to latest U-Boot master

drivers/mmc/fsl_esdhc.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 9cd582f..d3a18c0 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -538,7 +538,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4);

#ifdef CONFIG_FSL_USDHC - esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA); + esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); #else esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); #endif @@ -548,7 +548,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) udelay(10000);

#ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(&regs->sysctl, SYSCTL_RSTA); + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); #else esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -643,6 +643,8 @@ static int esdhc_init(struct mmc *mmc)

#ifndef CONFIG_FSL_USDHC esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); +#else + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); #endif

/* Set the initial clock speed */ @@ -740,6 +742,9 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv) #ifndef CONFIG_FSL_USDHC esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); +#else + esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | + VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); #endif

writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);

Introudce wp_enable. If want to check WPSPL, then in board code, need to set wp_enable to 1.

Take i.MX6UL for example, to some boards, they do not use WP singal, so they does not configure USDHC1_WP_SELECT_INPUT, and its default value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and SION bit set. So USDHC controller can always get wp signal and WPSPL shows write protect and blocks driver continuing. This is not what we want to see, so add wp_enable, and if set to 0, just omit the WPSPL checking and this does not effect normal working of usdhc controller.

To DT case, add wp_gpio, if there is wp-gpios provided in dts, wp_enable is set to 1; if no, set to 0.

Signed-off-by: Peng Fan van.freenix@gmail.com Cc: Pantelis Antoniou panto@antoniou-consulting.com Cc: York Sun york.sun@nxp.com Cc: Stefano Babic sbabic@denx.de Cc: Fabio Estevam fabio.estevam@nxp.com Tested-by: Fabio Estevam fabio.estevam@nxp.com ---

V2: Rebased to lastest U-Boot master. Add Fabio's tested-by tag.

drivers/mmc/fsl_esdhc.c | 21 ++++++++++++++++++--- include/fsl_esdhc.h | 1 + 2 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index d3a18c0..7ee5a24 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -91,7 +91,9 @@ struct fsl_esdhc { * Following is used when Driver Model is enabled for MMC * @dev: pointer for the device * @non_removable: 0: removable; 1: non-removable + * @wp_enable: 1: enable checking wp; 0: no check * @cd_gpio: gpio for card detection + * @wp_gpio: gpio for write protection */ struct fsl_esdhc_priv { struct fsl_esdhc *esdhc_regs; @@ -101,7 +103,9 @@ struct fsl_esdhc_priv { struct mmc *mmc; struct udevice *dev; int non_removable; + int wp_enable; struct gpio_desc cd_gpio; + struct gpio_desc wp_gpio; };

/* Return the XFERTYP flags for a given command and data packet */ @@ -245,9 +249,12 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) #endif if (wml_value > WML_WR_WML_MAX) wml_value = WML_WR_WML_MAX_VAL; - if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) { - printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); - return TIMEOUT; + if (priv->wp_enable) { + if ((esdhc_read32(&regs->prsstat) & + PRSSTAT_WPSPL) == 0) { + printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); + return TIMEOUT; + } }

esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK, @@ -721,6 +728,7 @@ static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg, priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); priv->bus_width = cfg->max_bus_width; priv->sdhc_clk = cfg->sdhc_clk; + priv->wp_enable = cfg->wp_enable;

return 0; }; @@ -963,6 +971,13 @@ static int fsl_esdhc_probe(struct udevice *dev) &priv->cd_gpio, GPIOD_IS_IN); }

+ priv->wp_enable = 1; + + ret = gpio_request_by_name_nodev(fdt, node, "wp-gpios", 0, + &priv->wp_gpio, GPIOD_IS_IN); + if (ret) + priv->wp_enable = 0; + /* * TODO: * Because lack of clk driver, if SDHC clk is not enabled, diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 78c67c8..c6f4666 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -177,6 +177,7 @@ struct fsl_esdhc_cfg { phys_addr_t esdhc_base; u32 sdhc_clk; u8 max_bus_width; + u8 wp_enable; struct mmc_config cfg; };

Hi York, Stefano

Any comments on this patch set? Would you kindly pick up this patch set?

Thanks, Peng. On Wed, Jun 15, 2016 at 10:53:00AM +0800, Peng Fan wrote:

When booting in eMMC fast boot, MMC host does not exit from boot mode after bootrom loading image. So the first command 'CMD0' sent in uboot will pull down the CMD line to low and cause errors.

This patch cleans the MMC boot register in "mmc_init" to put the MMC host back to normal mode.

Also clear DLL_CTRL delay line settings at USDHC initialization to eliminate the pre-settings from boot rom.

Signed-off-by: Peng Fan van.freenix@gmail.com Cc: Pantelis Antoniou panto@antoniou-consulting.com Cc: York Sun york.sun@nxp.com Cc: Stefano Babic sbabic@denx.de Cc: Fabio Estevam fabio.estevam@nxp.com

---

V2: Rebased to lastest u-boot master

drivers/mmc/fsl_esdhc.c | 38 +++++++++++++++++++++++++++++--------- include/fsl_esdhc.h | 6 ++++++ 2 files changed, 35 insertions(+), 9 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 57ad975..9cd582f 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -56,21 +56,27 @@ struct fsl_esdhc { uint fevt; /* Force event register */ uint admaes; /* ADMA error status register */ uint adsaddr; /* ADMA system address register */

• char reserved2[100]; /* reserved */
• uint vendorspec; /* Vendor Specific register */
• char reserved3[56]; /* reserved */

• char reserved2[4];
• uint dllctrl;
• uint dllstat;
• uint clktunectrlstatus;
• char reserved3[84];
• uint vendorspec;
• uint mmcboot;
• uint vendorspec2;
• char reserved4[48]; uint hostver; /* Host controller version register */

• char reserved4[4]; /* reserved */
• uint dmaerraddr; /* DMA error address register */ char reserved5[4]; /* reserved */
• uint dmaerrattr; /* DMA error attribute register */

• uint dmaerraddr; /* DMA error address register */ char reserved6[4]; /* reserved */
• uint dmaerrattr; /* DMA error attribute register */
• char reserved7[4]; /* reserved */ uint hostcapblt2; /* Host controller capabilities register 2 */

• char reserved7[8]; /* reserved */

• char reserved8[8]; /* reserved */ uint tcr; /* Tuning control register */

• char reserved8[28]; /* reserved */

• char reserved9[28]; /* reserved */ uint sddirctl; /* SD direction control register */

• char reserved9[712]; /* reserved */

• char reserved10[712];/* reserved */ uint scr; /* eSDHC control register */

};

@@ -616,6 +622,20 @@ static int esdhc_init(struct mmc *mmc) while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout) udelay(1000);

+#if defined(CONFIG_FSL_USDHC)

• /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
• esdhc_write32(&regs->mmcboot, 0x0);
• /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
• esdhc_write32(&regs->mixctrl, 0x0);
• esdhc_write32(&regs->clktunectrlstatus, 0x0);
• /* Put VEND_SPEC to default value */
• esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
• /* Disable DLL_CTRL delay line */
• esdhc_write32(&regs->dllctrl, 0x0);

+#endif

#ifndef ARCH_MXC /* Enable cache snooping */ esdhc_write32(&regs->scr, 0x00000040); diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index fa760a5..78c67c8 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -35,6 +35,12 @@ #define SYSCTL_RSTC 0x02000000 #define SYSCTL_RSTD 0x04000000

+#define VENDORSPEC_CKEN 0x00004000 +#define VENDORSPEC_PEREN 0x00002000 +#define VENDORSPEC_HCKEN 0x00001000 +#define VENDORSPEC_IPGEN 0x00000800 +#define VENDORSPEC_INIT 0x20007809

#define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000)

#define IRQSTAT_AC12E (0x01000000)

2.6.2