This is still a non-generic board.

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Guennadi Liakhovetski g.liakhovetski@gmx.de Acked-by: Marek Vasut marex@denx.de ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/arm/Kconfig | 5 - board/imx31_phycore/Kconfig | 12 --- board/imx31_phycore/MAINTAINERS | 11 -- board/imx31_phycore/Makefile | 9 -- board/imx31_phycore/imx31_phycore.c | 153 --------------------------- board/imx31_phycore/lowlevel_init.S | 88 ---------------- configs/imx31_phycore_defconfig | 2 - configs/imx31_phycore_eet_defconfig | 3 - doc/README.scrapyard | 1 + include/configs/imx31_phycore.h | 202 ------------------------------------ 10 files changed, 1 insertion(+), 485 deletions(-) delete mode 100644 board/imx31_phycore/Kconfig delete mode 100644 board/imx31_phycore/MAINTAINERS delete mode 100644 board/imx31_phycore/Makefile delete mode 100644 board/imx31_phycore/imx31_phycore.c delete mode 100644 board/imx31_phycore/lowlevel_init.S delete mode 100644 configs/imx31_phycore_defconfig delete mode 100644 configs/imx31_phycore_eet_defconfig delete mode 100644 include/configs/imx31_phycore.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7c8b324..57cee0c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -264,10 +264,6 @@ config TARGET_INTEGRATORCP_CM1136 bool "Support integratorcp_cm1136" select CPU_ARM1136

-config TARGET_IMX31_PHYCORE - bool "Support imx31_phycore" - select CPU_ARM1136 - config TARGET_QONG bool "Support qong" select CPU_ARM1136 @@ -812,7 +808,6 @@ source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hale/tt01/Kconfig" source "board/icpdas/lp8x4x/Kconfig" -source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" source "board/jornada/Kconfig" source "board/karo/tx25/Kconfig" diff --git a/board/imx31_phycore/Kconfig b/board/imx31_phycore/Kconfig deleted file mode 100644 index d3d2025..0000000 --- a/board/imx31_phycore/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_IMX31_PHYCORE - -config SYS_BOARD - default "imx31_phycore" - -config SYS_SOC - default "mx31" - -config SYS_CONFIG_NAME - default "imx31_phycore" - -endif diff --git a/board/imx31_phycore/MAINTAINERS b/board/imx31_phycore/MAINTAINERS deleted file mode 100644 index 41f6cae..0000000 --- a/board/imx31_phycore/MAINTAINERS +++ /dev/null @@ -1,11 +0,0 @@ -IMX31_PHYCORE BOARD -#M: - -S: Maintained -F: board/imx31_phycore/ -F: include/configs/imx31_phycore.h -F: configs/imx31_phycore_defconfig - -IMX31_PHYCORE_EET BOARD -#M: (resigned) Guennadi Liakhovetski g.liakhovetski@gmx.de -S: Orphan (since 2013-09) -F: configs/imx31_phycore_eet_defconfig diff --git a/board/imx31_phycore/Makefile b/board/imx31_phycore/Makefile deleted file mode 100644 index e781c13..0000000 --- a/board/imx31_phycore/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := imx31_phycore.o -obj-y += lowlevel_init.o diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c deleted file mode 100644 index 3f45e4e..0000000 --- a/board/imx31_phycore/imx31_phycore.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer s.hauer@pengutronix.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#include <common.h> -#include <s6e63d6.h> -#include <netdev.h> -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/sys_proto.h> - -DECLARE_GLOBAL_DATA_PTR; - -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - return 0; -} - -int board_init(void) -{ - - gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ - gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ - - return 0; -} - -int board_early_init_f(void) -{ - /* CS0: Nor Flash */ - static const struct mxc_weimcs cs0 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 15, 0, 0, 3), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(1, 0, 0, 0, 0, 1, 5, 0, 0, 0, 1, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(0, 0, 7, 2, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0) - }; - - /* CS1: Network Controller */ - static const struct mxc_weimcs cs1 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 31, 0, 0, 6), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0) - }; - - /* CS4: SRAM */ - static const struct mxc_weimcs cs4 = { - /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ - CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3), - /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ - CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1), - /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ - CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0) - }; - - mxc_setup_weimcs(0, &cs0); - mxc_setup_weimcs(1, &cs1); - mxc_setup_weimcs(4, &cs4); - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* setup pins for I2C2 (for EEPROM, RTC) */ - mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); - mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); - - return 0; -} - -#ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ -#ifdef CONFIG_S6E63D6 - struct s6e63d6 data = { - /* - * See comment in mxc_spi.c::decode_cs() for .cs field format. - * We use GPIO 57 as a chipselect for the S6E63D6 and chipselect - * 2 of the SPI controller #1, since it is unused. - */ - .cs = 2 | (57 << 8), - .bus = 0, - .id = 0, - }; - int ret; - - /* SPI1 */ - mx31_gpio_mux(MUX_CSPI1_SCLK__CSPI1_CLK); - mx31_gpio_mux(MUX_CSPI1_SPI_RDY__CSPI1_DATAREADY_B); - mx31_gpio_mux(MUX_CSPI1_MOSI__CSPI1_MOSI); - mx31_gpio_mux(MUX_CSPI1_MISO__CSPI1_MISO); - mx31_gpio_mux(MUX_CSPI1_SS0__CSPI1_SS0_B); - mx31_gpio_mux(MUX_CSPI1_SS1__CSPI1_SS1_B); - mx31_gpio_mux(MUX_CSPI1_SS2__CSPI1_SS2_B); - - /* start SPI1 clock */ - __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 2); - - /* GPIO 57 */ - /* sw_mux_ctl_key_col4_key_col5_key_col6_key_col7 */ - mx31_gpio_mux(IOMUX_MODE(0x63, MUX_CTL_GPIO)); - - /* SPI1 CS2 is free */ - ret = s6e63d6_init(&data); - if (ret) - return ret; - - /* - * This is a "magic" sequence to initialise a C0240QGLA / C0283QGLC - * OLED display connected to a S6E63D6 SPI display controller in the - * 18 bit RGB mode - */ - s6e63d6_index(&data, 2); - s6e63d6_param(&data, 0x0182); - s6e63d6_index(&data, 3); - s6e63d6_param(&data, 0x8130); - s6e63d6_index(&data, 0x10); - s6e63d6_param(&data, 0x0000); - s6e63d6_index(&data, 5); - s6e63d6_param(&data, 0x0001); - s6e63d6_index(&data, 0x22); -#endif - return 0; -} -#endif - -int checkboard (void) -{ - printf("Board: Phytec phyCore i.MX31\n"); - return 0; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S deleted file mode 100644 index 6ea3878..0000000 --- a/board/imx31_phycore/lowlevel_init.S +++ /dev/null @@ -1,88 +0,0 @@ -/* - * - * (c) 2007 Pengutronix, Sascha Hauer s.hauer@pengutronix.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <asm/arch/imx-regs.h> - -.macro REG reg, val - ldr r2, =\reg - ldr r3, =\val - str r3, [r2] -.endm - -.macro REG8 reg, val - ldr r2, =\reg - ldr r3, =\val - strb r3, [r2] -.endm - -.macro DELAY loops - ldr r2, =\loops -1: - subs r2, r2, #1 - nop - bcs 1b -.endm - -.globl lowlevel_init -lowlevel_init: - - REG IPU_CONF, IPU_CONF_DI_EN - REG CCM_CCMR, 0x074B0BF5 - - DELAY 0x40000 - - REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE - REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS - - REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0) - - REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd) - - REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1) - - REG 0x43FAC26C, 0 /* SDCLK */ - REG 0x43FAC270, 0 /* CAS */ - REG 0x43FAC274, 0 /* RAS */ - REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ - REG 0x43FAC284, 0 /* DQM3 */ - REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ - REG 0x43FAC28C, 0 - REG 0x43FAC290, 0 - REG 0x43FAC294, 0 - REG 0x43FAC298, 0 - REG 0x43FAC29C, 0 - REG 0x43FAC2A0, 0 - REG 0x43FAC2A4, 0 - REG 0x43FAC2A8, 0 - REG 0x43FAC2AC, 0 - REG 0x43FAC2B0, 0 - REG 0x43FAC2B4, 0 - REG 0x43FAC2B8, 0 - REG 0x43FAC2BC, 0 - REG 0x43FAC2C0, 0 - REG 0x43FAC2C4, 0 - REG 0x43FAC2C8, 0 - REG 0x43FAC2CC, 0 - REG 0x43FAC2D0, 0 - REG 0x43FAC2D4, 0 - REG 0x43FAC2D8, 0 - REG 0x43FAC2DC, 0 - REG 0xB8001010, 0x00000004 - REG 0xB8001004, 0x006ac73a - REG 0xB8001000, 0x92100000 - REG 0x80000f00, 0x12344321 - REG 0xB8001000, 0xa2100000 - REG 0x80000000, 0x12344321 - REG 0x80000000, 0x12344321 - REG 0xB8001000, 0xb2100000 - REG8 0x80000033, 0xda - REG8 0x81000000, 0xff - REG 0xB8001000, 0x82226080 - REG 0x80000000, 0xDEADBEEF - REG 0xB8001010, 0x0000000c - - mov pc, lr diff --git a/configs/imx31_phycore_defconfig b/configs/imx31_phycore_defconfig deleted file mode 100644 index 563de57..0000000 --- a/configs/imx31_phycore_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_IMX31_PHYCORE=y diff --git a/configs/imx31_phycore_eet_defconfig b/configs/imx31_phycore_eet_defconfig deleted file mode 100644 index 9531952..0000000 --- a/configs/imx31_phycore_eet_defconfig +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX31_PHYCORE_EET" -CONFIG_ARM=y -CONFIG_TARGET_IMX31_PHYCORE=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index c6f3d14..cd51249 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +imx31_phycore arm arm1136 - - Guennadi Liakhovetski g.liakhovetski@gmx.de mx31ads arm arm1136 - - Guennadi Liakhovetski g.liakhovetski@gmx.de icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk wd@denx.de Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23 diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h deleted file mode 100644 index 4195fa3..0000000 --- a/include/configs/imx31_phycore.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Richard Woodruff r-woodruff2@ti.com - * Kshitij Gupta kshitij@ti.com - * - * Configuration settings for the phyCORE-i.MX31 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <asm/arch/imx-regs.h> - -/* High Level Configuration Options */ -#define CONFIG_MX31 /* This is a mx31 */ -#define CONFIG_MX31_CLK32 32000 - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ - -#include <config_cmd_default.h> - -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C - -#define CONFIG_BOOTDELAY 3 - -#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro," \ - "1536k(kernel),-(root)" - -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.23.168 -#define CONFIG_SERVERIP 192.168.23.2 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ - "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ - "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bootargs_flash=setenv bootargs $(bootargs) " \ - "root=/dev/mtdblock2 rootfstype=jffs2\0" \ - "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \ - "tftpboot 0x80000000 $(uimage);bootm\0" \ - "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \ - "bootm 0x80000000\0" \ - "unlock=yes\0" \ - "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "prg_uboot=tftpboot 0x80000000 $(uboot);" \ - "protect off 0xa0000000 +0x20000;" \ - "erase 0xa0000000 +0x20000;" \ - "cp.b 0x80000000 0xa0000000 $(filesize)\0" \ - "prg_kernel=tftpboot 0x80000000 $(uimage);" \ - "erase 0xa0040000 +0x180000;" \ - "cp.b 0x80000000 0xa0040000 $(filesize)\0" \ - "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \ - "erase 0xa01c0000 0xa1ffffff;" \ - "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \ - "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \ - "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \ - "sync:1241513985,vmode:0\0" - - -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0xa8000000 -#define CONFIG_SMC911X_32_BIT - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "uboot> " -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 256 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR 0 /* default load address */ - -#define CONFIG_CMDLINE_EDITING - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SYS_TEXT_BASE 0xA0000000 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE 0xa0000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_IS_IN_EEPROM -#define CONFIG_ENV_OFFSET 0x00 /* env. starts here */ -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */ - -/* - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ -#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */ -#define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */ - -/* - * Timeout for Flash Erase and Flash Write - * timeout values are in ticks - */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ) - -/* - * JFFS2 partitions - */ -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_JFFS2_DEV "nor0" - -/* EET platform additions */ -#ifdef CONFIG_IMX31_PHYCORE_EET -#define CONFIG_BOARD_LATE_INIT - -#define CONFIG_MXC_GPIO - -#define CONFIG_HARD_SPI -#define CONFIG_MXC_SPI -#define CONFIG_CMD_SPI - -#define CONFIG_S6E63D6 - -#define CONFIG_VIDEO -#define CONFIG_CFB_CONSOLE -#define CONFIG_VIDEO_MX3 -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_SW_CURSOR -#define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SPLASH_SCREEN -#define CONFIG_CMD_BMP -#define CONFIG_BMP_16BPP -#endif - -#endif /* __CONFIG_H */

This is still a non-generic board.

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Matthias Weisser weisserm@arcor.de Acked-by: Marek Vasut marex@denx.de ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/arm/Kconfig | 5 - arch/arm/cpu/arm926ejs/Makefile | 1 - arch/arm/cpu/arm926ejs/mb86r0x/Makefile | 8 - arch/arm/cpu/arm926ejs/mb86r0x/clock.c | 27 -- arch/arm/cpu/arm926ejs/mb86r0x/reset.c | 24 -- arch/arm/cpu/arm926ejs/mb86r0x/timer.c | 115 ----- arch/arm/include/asm/arch-mb86r0x/hardware.h | 15 - arch/arm/include/asm/arch-mb86r0x/mb86r0x.h | 599 --------------------------- arch/arm/lib/asm-offsets.c | 46 -- board/syteco/jadecpu/Kconfig | 15 - board/syteco/jadecpu/MAINTAINERS | 6 - board/syteco/jadecpu/Makefile | 13 - board/syteco/jadecpu/jadecpu.c | 160 ------- board/syteco/jadecpu/lowlevel_init.S | 249 ----------- configs/jadecpu_defconfig | 2 - doc/README.scrapyard | 1 + drivers/video/Makefile | 1 - drivers/video/mb86r0xgdc.c | 168 -------- include/configs/jadecpu.h | 273 ------------ include/serial.h | 2 +- 20 files changed, 2 insertions(+), 1728 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/Makefile delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/clock.c delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/reset.c delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/timer.c delete mode 100644 arch/arm/include/asm/arch-mb86r0x/hardware.h delete mode 100644 arch/arm/include/asm/arch-mb86r0x/mb86r0x.h delete mode 100644 board/syteco/jadecpu/Kconfig delete mode 100644 board/syteco/jadecpu/MAINTAINERS delete mode 100644 board/syteco/jadecpu/Makefile delete mode 100644 board/syteco/jadecpu/jadecpu.c delete mode 100644 board/syteco/jadecpu/lowlevel_init.S delete mode 100644 configs/jadecpu_defconfig delete mode 100644 drivers/video/mb86r0xgdc.c delete mode 100644 include/configs/jadecpu.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 57cee0c..b24fb18 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -144,10 +144,6 @@ config TARGET_DEVKIT3250 bool "Support devkit3250" select CPU_ARM926EJS

-config TARGET_JADECPU - bool "Support jadecpu" - select CPU_ARM926EJS - config TARGET_MX25PDK bool "Support mx25pdk" select CPU_ARM926EJS @@ -843,7 +839,6 @@ source "board/st-ericsson/snowball/Kconfig" source "board/st-ericsson/u8500/Kconfig" source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" -source "board/syteco/jadecpu/Kconfig" source "board/syteco/zmx25/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/ti/am335x/Kconfig" diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index f5944cc..ac23116 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -16,7 +16,6 @@ endif

obj-$(CONFIG_ARMADA100) += armada100/ obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/ -obj-$(CONFIG_MB86R0x) += mb86r0x/ obj-$(CONFIG_MX25) += mx25/ obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile deleted file mode 100644 index 365892c..0000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = clock.o reset.o timer.o diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c deleted file mode 100644 index 1f6f66e..0000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser weisserm@arcor.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -/* - * Get the peripheral bus frequency depending on pll pin settings - */ -ulong get_bus_freq(ulong dummy) -{ - struct mb86r0x_crg * crg = (struct mb86r0x_crg *) - MB86R0x_CRG_BASE; - uint32_t pllmode; - - pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE; - - if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20) - return 40000000; - - return 41164767; -} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c deleted file mode 100644 index 7bd77ff..0000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser weisserm@arcor.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -/* - * Reset the cpu by setting software reset request bit - */ -void reset_cpu(ulong ignored) -{ - struct mb86r0x_crg * crg = (struct mb86r0x_crg *) - MB86R0x_CRG_BASE; - - writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr); - while (1) - /* NOP */; - /* Never reached */ -} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c deleted file mode 100644 index bb07819..0000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop stelian@popies.net - * Lead Tech Design <www.leadtechdesign.com> - * - * (C) Copyright 2010 - * Matthias Weisser, Graf-Syteco weisserm@arcor.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <div64.h> -#include <common.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> - -#define TIMER_LOAD_VAL 0xffffffff -#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256) - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= TIMER_FREQ; - do_div(usec, 1000000); - - return usec; -} - -/* nothing really to do with interrupts, just starts up a counter. */ -int timer_init(void) -{ - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) - MB86R0x_TIMER_BASE; - ulong ctrl = readl(&timer->control); - - writel(TIMER_LOAD_VAL, &timer->load); - - ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S | - MB86R0x_TIMER_SIZE_32; - - writel(ctrl, &timer->control); - - /* capture current value time */ - lastdec = readl(&timer->value); - timestamp = 0; /* start "advancing" time stamp from 0 */ - - return 0; -} - -/* - * timer without interrupts - */ -unsigned long long get_ticks(void) -{ - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) - MB86R0x_TIMER_BASE; - ulong now = readl(&timer->value); - - if (now <= lastdec) { - /* normal mode (non roll) */ - /* move stamp forward with absolut diff ticks */ - timestamp += lastdec - now; - } else { - /* we have rollover of incrementer */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - return timestamp; -} - -ulong get_timer_masked(void) -{ - return tick_to_time(get_ticks()); -} - -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = usec_to_tick(usec); - tmp = get_ticks(); /* get current timestamp */ - - while ((get_ticks() - tmp) < tmo) /* loop till event */ - /*NOP*/; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - ulong tbclk; - - tbclk = TIMER_FREQ; - return tbclk; -} diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h deleted file mode 100644 index 42a52bc..0000000 --- a/arch/arm/include/asm/arch-mb86r0x/hardware.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2007 - * - * Author : Carsten Schneider, mycable GmbH - * cs@mycable.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include <linux/sizes.h> -#include <asm/arch/mb86r0x.h> - -#endif diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h deleted file mode 100644 index 7fec971..0000000 --- a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h +++ /dev/null @@ -1,599 +0,0 @@ -/* - * (C) Copyright 2007 - * - * mb86r0x definitions - * - * Author : Carsten Schneider, mycable GmbH - * cs@mycable.de - * - * (C) Copyright 2010 - * Matthias Weisser weisserm@arcor.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef MB86R0X_H -#define MB86R0X_H - -#ifndef __ASSEMBLY__ - -/* GPIO registers */ -struct mb86r0x_gpio { - uint32_t gpdr0; - uint32_t gpdr1; - uint32_t gpdr2; - uint32_t res; - uint32_t gpddr0; - uint32_t gpddr1; - uint32_t gpddr2; -}; - -/* PWM registers */ -struct mb86r0x_pwm { - uint32_t bcr; - uint32_t tpr; - uint32_t pr; - uint32_t dr; - uint32_t cr; - uint32_t sr; - uint32_t ccr; - uint32_t ir; -}; - -/* The mb86r0x chip control (CCNT) register set. */ -struct mb86r0x_ccnt { - uint32_t ccid; - uint32_t csrst; - uint32_t pad0[2]; - uint32_t cist; - uint32_t cistm; - uint32_t cgpio_ist; - uint32_t cgpio_istm; - uint32_t cgpio_ip; - uint32_t cgpio_im; - uint32_t caxi_bw; - uint32_t caxi_ps; - uint32_t cmux_md; - uint32_t cex_pin_st; - uint32_t cmlb; - uint32_t pad1[1]; - uint32_t cusb; - uint32_t pad2[41]; - uint32_t cbsc; - uint32_t cdcrc; - uint32_t cmsr0; - uint32_t cmsr1; - uint32_t pad3[2]; -}; - -/* The mb86r0x clock reset generator */ -struct mb86r0x_crg { - uint32_t crpr; - uint32_t pad0; - uint32_t crwr; - uint32_t crsr; - uint32_t crda; - uint32_t crdb; - uint32_t crha; - uint32_t crpa; - uint32_t crpb; - uint32_t crhb; - uint32_t cram; -}; - -/* The mb86r0x timer */ -struct mb86r0x_timer { - uint32_t load; - uint32_t value; - uint32_t control; - uint32_t intclr; - uint32_t ris; - uint32_t mis; - uint32_t bgload; -}; - -/* mb86r0x gdc display controller */ -struct mb86r0x_gdc_dsp { - /* Display settings */ - uint32_t dcm0; - uint16_t pad00; - uint16_t htp; - uint16_t hdp; - uint16_t hdb; - uint16_t hsp; - uint8_t hsw; - uint8_t vsw; - uint16_t pad01; - uint16_t vtr; - uint16_t vsp; - uint16_t vdp; - uint16_t wx; - uint16_t wy; - uint16_t ww; - uint16_t wh; - - /* Layer 0 */ - uint32_t l0m; - uint32_t l0oa; - uint32_t l0da; - uint16_t l0dx; - uint16_t l0dy; - - /* Layer 1 */ - uint32_t l1m; - uint32_t cbda0; - uint32_t cbda1; - uint32_t pad02; - - /* Layer 2 */ - uint32_t l2m; - uint32_t l2oa0; - uint32_t l2da0; - uint32_t l2oa1; - uint32_t l2da1; - uint16_t l2dx; - uint16_t l2dy; - - /* Layer 3 */ - uint32_t l3m; - uint32_t l3oa0; - uint32_t l3da0; - uint32_t l3oa1; - uint32_t l3da1; - uint16_t l3dx; - uint16_t l3dy; - - /* Layer 4 */ - uint32_t l4m; - uint32_t l4oa0; - uint32_t l4da0; - uint32_t l4oa1; - uint32_t l4da1; - uint16_t l4dx; - uint16_t l4dy; - - /* Layer 5 */ - uint32_t l5m; - uint32_t l5oa0; - uint32_t l5da0; - uint32_t l5oa1; - uint32_t l5da1; - uint16_t l5dx; - uint16_t l5dy; - - /* Cursor */ - uint16_t cutc; - uint8_t cpm; - uint8_t csize; - uint32_t cuoa0; - uint16_t cux0; - uint16_t cuy0; - uint32_t cuoa1; - uint16_t cux1; - uint16_t cuy1; - - /* Layer blending */ - uint32_t l0bld; - uint32_t pad03; - uint32_t l0tc; - uint16_t l3tc; - uint16_t l2tc; - uint32_t pad04[15]; - - /* Display settings */ - uint32_t dcm1; - uint32_t dcm2; - uint32_t dcm3; - uint32_t pad05; - - /* Layer 0 extended */ - uint32_t l0em; - uint16_t l0wx; - uint16_t l0wy; - uint16_t l0ww; - uint16_t l0wh; - uint32_t pad06; - - /* Layer 1 extended */ - uint32_t l1em; - uint16_t l1wx; - uint16_t l1wy; - uint16_t l1ww; - uint16_t l1wh; - uint32_t pad07; - - /* Layer 2 extended */ - uint32_t l2em; - uint16_t l2wx; - uint16_t l2wy; - uint16_t l2ww; - uint16_t l2wh; - uint32_t pad08; - - /* Layer 3 extended */ - uint32_t l3em; - uint16_t l3wx; - uint16_t l3wy; - uint16_t l3ww; - uint16_t l3wh; - uint32_t pad09; - - /* Layer 4 extended */ - uint32_t l4em; - uint16_t l4wx; - uint16_t l4wy; - uint16_t l4ww; - uint16_t l4wh; - uint32_t pad10; - - /* Layer 5 extended */ - uint32_t l5em; - uint16_t l5wx; - uint16_t l5wy; - uint16_t l5ww; - uint16_t l5wh; - uint32_t pad11; - - /* Multi screen control */ - uint32_t msc; - uint32_t pad12[3]; - uint32_t dls; - uint32_t dbgc; - - /* Layer blending */ - uint32_t l1bld; - uint32_t l2bld; - uint32_t l3bld; - uint32_t l4bld; - uint32_t l5bld; - uint32_t pad13; - - /* Extended transparency control */ - uint32_t l0etc; - uint32_t l1etc; - uint32_t l2etc; - uint32_t l3etc; - uint32_t l4etc; - uint32_t l5etc; - uint32_t pad14[10]; - - /* YUV coefficients */ - uint32_t l1ycr0; - uint32_t l1ycr1; - uint32_t l1ycg0; - uint32_t l1ycg1; - uint32_t l1ycb0; - uint32_t l1ycb1; - uint32_t pad15[130]; - - /* Layer palletes */ - uint32_t l0pal[256]; - uint32_t l1pal[256]; - uint32_t pad16[256]; - uint32_t l2pal[256]; - uint32_t l3pal[256]; - uint32_t pad17[256]; - - /* PWM settings */ - uint32_t vpwmm; - uint16_t vpwms; - uint16_t vpwme; - uint32_t vpwmc; - uint32_t pad18[253]; -}; - -/* mb86r0x gdc capture controller */ -struct mb86r0x_gdc_cap { - uint32_t vcm; - uint32_t csc; - uint32_t vcs; - uint32_t pad01; - - uint32_t cbm; - uint32_t cboa; - uint32_t cbla; - uint16_t cihstr; - uint16_t civstr; - uint16_t cihend; - uint16_t civend; - uint32_t pad02; - - uint32_t chp; - uint32_t cvp; - uint32_t pad03[4]; - - uint32_t clpf; - uint32_t pad04; - uint32_t cmss; - uint32_t cmds; - uint32_t pad05[12]; - - uint32_t rgbhc; - uint32_t rgbhen; - uint32_t rgbven; - uint32_t pad06; - uint32_t rgbs; - uint32_t pad07[11]; - - uint32_t rgbcmy; - uint32_t rgbcmcb; - uint32_t rgbcmcr; - uint32_t rgbcmb; - uint32_t pad08[12 + 1984]; -}; - -/* mb86r0x gdc draw */ -struct mb86r0x_gdc_draw { - uint32_t ys; - uint32_t xs; - uint32_t dxdy; - uint32_t xus; - uint32_t dxudy; - uint32_t xls; - uint32_t dxldy; - uint32_t usn; - uint32_t lsn; - uint32_t pad01[7]; - uint32_t rs; - uint32_t drdx; - uint32_t drdy; - uint32_t gs; - uint32_t dgdx; - uint32_t dgdy; - uint32_t bs; - uint32_t dbdx; - uint32_t dbdy; - uint32_t pad02[7]; - uint32_t zs; - uint32_t dzdx; - uint32_t dzdy; - uint32_t pad03[13]; - uint32_t ss; - uint32_t dsdx; - uint32_t dsdy; - uint32_t ts; - uint32_t dtdx; - uint32_t dtdy; - uint32_t qs; - uint32_t dqdx; - uint32_t dqdy; - uint32_t pad04[23]; - uint32_t lpn; - uint32_t lxs; - uint32_t lxde; - uint32_t lys; - uint32_t lyde; - uint32_t lzs; - uint32_t lzde; - uint32_t pad05[13]; - uint32_t pxdc; - uint32_t pydc; - uint32_t pzdc; - uint32_t pad06[25]; - uint32_t rxs; - uint32_t rys; - uint32_t rsizex; - uint32_t rsizey; - uint32_t pad07[12]; - uint32_t saddr; - uint32_t sstride; - uint32_t srx; - uint32_t sry; - uint32_t daddr; - uint32_t dstride; - uint32_t drx; - uint32_t dry; - uint32_t brsizex; - uint32_t brsizey; - uint32_t tcolor; - uint32_t pad08[93]; - uint32_t blpo; - uint32_t pad09[7]; - uint32_t ctr; - uint32_t ifsr; - uint32_t ifcnt; - uint32_t sst; - uint32_t ds; - uint32_t pst; - uint32_t est; - uint32_t pad10; - uint32_t mdr0; - uint32_t mdr1; - uint32_t mdr2; - uint32_t mdr3; - uint32_t mdr4; - uint32_t pad14[2]; - uint32_t mdr7; - uint32_t fbr; - uint32_t xres; - uint32_t zbr; - uint32_t tbr; - uint32_t pfbr; - uint32_t cxmin; - uint32_t cxmax; - uint32_t cymin; - uint32_t cymax; - uint32_t txs; - uint32_t tis; - uint32_t toa; - uint32_t sho; - uint32_t abr; - uint32_t pad15[2]; - uint32_t fc; - uint32_t bc; - uint32_t alf; - uint32_t blp; - uint32_t pad16; - uint32_t tbc; - uint32_t pad11[42]; - uint32_t lx0dc; - uint32_t ly0dc; - uint32_t lx1dc; - uint32_t ly1dc; - uint32_t pad12[12]; - uint32_t x0dc; - uint32_t y0dc; - uint32_t x1dc; - uint32_t y1dc; - uint32_t x2dc; - uint32_t y2dc; - uint32_t pad13[666]; -}; - -/* mb86r0x gdc geometry engine */ -struct mb86r0x_gdc_geom { - uint32_t gctr; - uint32_t pad00[15]; - uint32_t gmdr0; - uint32_t gmdr1; - uint32_t gmdr2; - uint32_t pad01[237]; - uint32_t dfifog; - uint32_t pad02[767]; -}; - -/* mb86r0x gdc */ -struct mb86r0x_gdc { - uint32_t pad00[2]; - uint32_t lts; - uint32_t pad01; - uint32_t lsta; - uint32_t pad02[3]; - uint32_t ist; - uint32_t imask; - uint32_t pad03[6]; - uint32_t lsa; - uint32_t lco; - uint32_t lreq; - - uint32_t pad04[16*1024 - 19]; - struct mb86r0x_gdc_dsp dsp0; - struct mb86r0x_gdc_dsp dsp1; - uint32_t pad05[4*1024 - 2]; - uint32_t vccc; - uint32_t vcsr; - struct mb86r0x_gdc_cap cap0; - struct mb86r0x_gdc_cap cap1; - uint32_t pad06[4*1024]; - uint32_t texture_base[16*1024]; - struct mb86r0x_gdc_draw draw; - uint32_t pad07[7*1024]; - struct mb86r0x_gdc_geom geom; - uint32_t pad08[7*1024]; -}; - -/* mb86r0x ddr2c */ -struct mb86r0x_ddr2c { - uint16_t dric; - uint16_t dric1; - uint16_t dric2; - uint16_t drca; - uint16_t drcm; - uint16_t drcst1; - uint16_t drcst2; - uint16_t drcr; - uint16_t pad00[8]; - uint16_t drcf; - uint16_t pad01[7]; - uint16_t drasr; - uint16_t pad02[15]; - uint16_t drims; - uint16_t pad03[7]; - uint16_t dros; - uint16_t pad04; - uint16_t dribsodt1; - uint16_t dribsocd; - uint16_t dribsocd2; - uint16_t pad05[3]; - uint16_t droaba; - uint16_t pad06[9]; - uint16_t drobs; - uint16_t pad07[5]; - uint16_t drimr1; - uint16_t drimr2; - uint16_t drimr3; - uint16_t drimr4; - uint16_t droisr1; - uint16_t droisr2; -}; - -/* mb86r0x memc */ -struct mb86r0x_memc { - uint32_t mcfmode[8]; - uint32_t mcftim[8]; - uint32_t mcfarea[8]; -}; - -#endif /* __ASSEMBLY__ */ - -/* - * Physical Address Defines - */ -#define MB86R0x_DDR2_BASE 0xf3000000 -#define MB86R0x_GDC_BASE 0xf1fc0000 -#define MB86R0x_CCNT_BASE 0xfff42000 -#define MB86R0x_CAN0_BASE 0xfff54000 -#define MB86R0x_CAN1_BASE 0xfff55000 -#define MB86R0x_I2C0_BASE 0xfff56000 -#define MB86R0x_I2C1_BASE 0xfff57000 -#define MB86R0x_EHCI_BASE 0xfff80000 -#define MB86R0x_OHCI_BASE 0xfff81000 -#define MB86R0x_IRC1_BASE 0xfffb0000 -#define MB86R0x_MEMC_BASE 0xfffc0000 -#define MB86R0x_TIMER_BASE 0xfffe0000 -#define MB86R0x_UART0_BASE 0xfffe1000 -#define MB86R0x_UART1_BASE 0xfffe2000 -#define MB86R0x_IRCE_BASE 0xfffe4000 -#define MB86R0x_CRG_BASE 0xfffe7000 -#define MB86R0x_IRC0_BASE 0xfffe8000 -#define MB86R0x_GPIO_BASE 0xfffe9000 -#define MB86R0x_PWM0_BASE 0xfff41000 -#define MB86R0x_PWM1_BASE 0xfff41100 - -#define MB86R0x_CRSR_SWRSTREQ (1 << 1) - -/* - * Timer register bits - */ -#define MB86R0x_TIMER_ENABLE (1 << 7) -#define MB86R0x_TIMER_MODE_MSK (1 << 6) -#define MB86R0x_TIMER_MODE_FR (0 << 6) -#define MB86R0x_TIMER_MODE_PD (1 << 6) - -#define MB86R0x_TIMER_INT_EN (1 << 5) -#define MB86R0x_TIMER_PRS_MSK (3 << 2) -#define MB86R0x_TIMER_PRS_4S (1 << 2) -#define MB86R0x_TIMER_PRS_8S (1 << 3) -#define MB86R0x_TIMER_SIZE_32 (1 << 1) -#define MB86R0x_TIMER_ONE_SHT (1 << 0) - -/* - * Clock reset generator bits - */ -#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8) -#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0) -/* - * DDR2 controller bits - */ -#define MB86R0x_DDR2_DRCI_DRINI (1 << 15) -#define MB86R0x_DDR2_DRCI_CKEN (1 << 14) -#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0) -#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \ - MB86R0x_DDR2_DRCI_CKEN | \ - MB86R0x_DDR2_DRCI_DRCMD) -#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \ - MB86R0x_DDR2_DRCI_CKEN) -#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN -#endif /* MB86R0X_H */ diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index b0c26e5..e5bcaea 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -15,9 +15,6 @@ #include <common.h> #include <linux/kbuild.h>

-#if defined(CONFIG_MB86R0x) -#include <asm/arch/mb86r0x.h> -#endif #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ || defined(CONFIG_MX51) || defined(CONFIG_MX53) #include <asm/arch/imx-regs.h> @@ -27,8 +24,6 @@ int main(void) { /* * TODO : Check if each entry in this file is really necessary. - * - struct mb86r0x_ddr2 - * - struct mb86r0x_memc * - struct esdramc_regs * - struct max_regs * - struct aips_regs @@ -40,47 +35,6 @@ int main(void) * code. Is it better to define the macros directly in headers? */

-#if defined(CONFIG_MB86R0x) - /* ddr2 controller */ - DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); - DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); - DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); - DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); - DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); - DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); - DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); - DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); - DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); - DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); - DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); - DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); - DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); - DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); - DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); - - /* clock reset generator */ - DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); - DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); - DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); - DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); - DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); - DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); - - /* chip control module */ - DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); - - /* external bus interface */ - DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); - DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); - DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); - DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); - DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); - DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); - DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); - DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); - DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); -#endif - #if defined(CONFIG_MX25) /* Clock Control Module */ DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); diff --git a/board/syteco/jadecpu/Kconfig b/board/syteco/jadecpu/Kconfig deleted file mode 100644 index 6e9392e..0000000 --- a/board/syteco/jadecpu/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_JADECPU - -config SYS_BOARD - default "jadecpu" - -config SYS_VENDOR - default "syteco" - -config SYS_SOC - default "mb86r0x" - -config SYS_CONFIG_NAME - default "jadecpu" - -endif diff --git a/board/syteco/jadecpu/MAINTAINERS b/board/syteco/jadecpu/MAINTAINERS deleted file mode 100644 index b53e7ca..0000000 --- a/board/syteco/jadecpu/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -JADECPU BOARD -M: Matthias Weisser weisserm@arcor.de -S: Maintained -F: board/syteco/jadecpu/ -F: include/configs/jadecpu.h -F: configs/jadecpu_defconfig diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile deleted file mode 100644 index 7426436..0000000 --- a/board/syteco/jadecpu/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop stelian@popies.net -# Lead Tech Design <www.leadtechdesign.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += jadecpu.o -obj-y += lowlevel_init.o diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c deleted file mode 100644 index 6c60a41..0000000 --- a/board/syteco/jadecpu/jadecpu.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (c) 2010 Graf-Syteco, Matthias Weisser - * weisserm@arcor.de - * - * (C) Copyright 2007, mycable GmbH - * Carsten Schneider cs@mycable.de, Alexander Bigga ab@mycable.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <netdev.h> -#include <asm/io.h> -#include <asm/arch/mb86r0x.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *) - MB86R0x_CCNT_BASE; - - /* We select mode 0 for group 2 and mode 1 for group 4 */ - writel(0x00000010, &ccnt->cmux_md); - - gd->flags = 0; - gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; - - icache_enable(); - dcache_enable(); - - return 0; -} - -static void setup_display_power(uint32_t pwr_bit, char *pwm_opts, - unsigned long pwm_base) -{ - struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) - MB86R0x_GPIO_BASE; - struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base; - const char *e; - - writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2); - - e = getenv(pwm_opts); - if (e != NULL) { - const char *s; - uint32_t freq, init; - - freq = 0; - init = 0; - - s = strchr(e, 'f'); - if (s != NULL) - freq = simple_strtol(s + 2, NULL, 0); - - s = strchr(e, 'i'); - if (s != NULL) - init = simple_strtol(s + 2, NULL, 0); - - if (freq > 0) { - writel(CONFIG_MB86R0x_IOCLK / 1000 / freq, - &pwm->bcr); - writel(1002, &pwm->tpr); - writel(1, &pwm->pr); - writel(init * 10 + 1, &pwm->dr); - writel(1, &pwm->cr); - writel(1, &pwm->sr); - } - } -} - -int board_late_init(void) -{ - struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) - MB86R0x_GPIO_BASE; - uint32_t in_word; - -#ifdef CONFIG_VIDEO_MB86R0xGDC - /* Check if we have valid display settings and turn on power if so */ - /* Display 0 */ - if (getenv("gs_dsp_0_param") || getenv("videomode")) - setup_display_power((1 << 3), "gs_dsp_0_pwm", - MB86R0x_PWM0_BASE); - - /* The corresponding GPIO is always an output */ - writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2); - - /* Display 1 */ - if (getenv("gs_dsp_1_param") || getenv("videomode1")) - setup_display_power((1 << 4), "gs_dsp_1_pwm", - MB86R0x_PWM1_BASE); - - /* The corresponding GPIO is always an output */ - writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2); -#endif /* CONFIG_VIDEO_MB86R0xGDC */ - - /* 5V enable */ - writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1); - writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1); - - /* We have special boot options if told by GPIOs */ - in_word = readl(&gpio->gpdr1); - - if ((in_word & 0xC0) == 0xC0) { - setenv("stdin", "serial"); - setenv("stdout", "serial"); - setenv("stderr", "serial"); - setenv("preboot", "run gs_slow_boot"); - } else if ((in_word & 0xC0) != 0) { - setenv("stdout", "vga"); - setenv("preboot", "run gs_slow_boot"); - } else { - setenv("stdin", "serial"); - setenv("stdout", "serial"); - setenv("stderr", "serial"); - if (getenv("gs_devel")) { - setenv("preboot", "run gs_slow_boot"); - } else { - setenv("preboot", "run gs_fast_boot"); - } - } - - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -/* - * DRAM configuration - */ -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, - PHYS_SDRAM_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = gd->ram_size; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S deleted file mode 100644 index 9568cec..0000000 --- a/board/syteco/jadecpu/lowlevel_init.S +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2007, mycable GmbH - * Carsten Schneider cs@mycable.de, Alexander Bigga ab@mycable.de - * - * (C) Copyright 2003, ARM Ltd. - * Philippe Robin, philippe.robin@arm.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/macro.h> -#include <asm/arch/mb86r0x.h> -#include <generated/asm-offsets.h> - -/* Set up the platform, once the cpu has been initialized */ -.globl lowlevel_init -lowlevel_init: -/* - * Initialize Clock Reset Generator (CRG) - */ - - ldr r0, =MB86R0x_CRG_BASE - - /* Not change the initial value that is set by external pin.*/ -WAIT_PLL: - ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */ - tst r2, #MB86R0x_CRG_CRPR_PLLRDY - beq WAIT_PLL - - /* Set clock gate control */ - ldr r1, =CONFIG_SYS_CRG_CRHA_INIT - str r1, [r0, #CRG_CRHA] - ldr r1, =CONFIG_SYS_CRG_CRPA_INIT - str r1, [r0, #CRG_CRPA] - ldr r1, =CONFIG_SYS_CRG_CRPB_INIT - str r1, [r0, #CRG_CRPB] - ldr r1, =CONFIG_SYS_CRG_CRHB_INIT - str r1, [r0, #CRG_CRHB] - ldr r1, =CONFIG_SYS_CRG_CRAM_INIT - str r1, [r0, #CRG_CRAM] - -/* - * Initialize External Bus Interface - */ - ldr r0, =MB86R0x_MEMC_BASE - - ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT - str r1, [r0, #MEMC_MCFMODE0] - ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT - str r1, [r0, #MEMC_MCFMODE2] - ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT - str r1, [r0, #MEMC_MCFMODE4] - - ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT - str r1, [r0, #MEMC_MCFTIM0] - ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT - str r1, [r0, #MEMC_MCFTIM2] - ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT - str r1, [r0, #MEMC_MCFTIM4] - - ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT - str r1, [r0, #MEMC_MCFAREA0] - ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT - str r1, [r0, #MEMC_MCFAREA2] - ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT - str r1, [r0, #MEMC_MCFAREA4] - -/* - * Initialize DDR2 Controller - */ - - /* Wait for PLL LOCK up time or more */ - wait_timer 20 - - /* - * (2) Initialize DDRIF - */ - ldr r0, =MB86R0x_DDR2_BASE - ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT - strh r1, [r0, #DDR2_DRIMS] - - /* - * (3) Wait for 20MCKPs(120nsec) or more - */ - wait_timer 20 - - /* - * (4) IRESET/IUSRRST release - */ - ldr r0, =MB86R0x_CCNT_BASE - ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1 - str r1, [r0, #CCNT_CDCRC] - - /* - * (5) Wait for 20MCKPs(120nsec) or more - */ - wait_timer 20 - - /* - * (6) IDLLRST release - */ - ldr r0, =MB86R0x_CCNT_BASE - ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2 - str r1, [r0, #CCNT_CDCRC] - - /* - * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) - */ - wait_timer 33536 - - /* - * (9) MCKE ON - */ - ldr r0, =MB86R0x_DDR2_BASE - ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT - strh r1, [r0, #DDR2_DRCA] - ldr r1, =MB86R0x_DDR2_DRCI_INIT - strh r1, [r0, #DDR2_DRIC] - - /* - * (10) Initialize SDRAM - */ - - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 67 /* 400ns wait */ - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 200 - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 18 /* 105ns wait */ - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 200 /* MRS to OCD: 200clock */ - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT - strh r1, [r0, #DDR2_DRCM] - - ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT - strh r1, [r0, #DDR2_DRCST1] - - ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT - strh r1, [r0, #DDR2_DRCST2] - - ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT - strh r1, [r0, #DDR2_DRCR] - - ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT - strh r1, [r0, #DDR2_DRCF] - - ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT - strh r1, [r0, #DDR2_DRASR] - - /* - * (11) ODT setting - */ - ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT - strh r1, [r0, #DDR2_DROBS] - ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT - strh r1, [r0, #DDR2_DROABA] - ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT - strh r1, [r0, #DDR2_DRIBSODT1] - - /* - * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode - */ - ldr r1, =CONFIG_SYS_DDR2_DROS_INIT - strh r1, [r0, #DDR2_DROS] - ldr r1, =MB86R0x_DDR2_DRCI_NORMAL - strh r1, [r0, #DDR2_DRIC] - - mov pc, lr diff --git a/configs/jadecpu_defconfig b/configs/jadecpu_defconfig deleted file mode 100644 index 4348e0e..0000000 --- a/configs/jadecpu_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_JADECPU=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index cd51249..fbeb2cd 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +jadecpu arm arm926ejs - - Matthias Weisser weisserm@arcor.de imx31_phycore arm arm1136 - - Guennadi Liakhovetski g.liakhovetski@gmx.de mx31ads arm arm1136 - - Guennadi Liakhovetski g.liakhovetski@gmx.de icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk wd@denx.de diff --git a/drivers/video/Makefile b/drivers/video/Makefile index af2d47b..22a316b 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -32,7 +32,6 @@ obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o -obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o diff --git a/drivers/video/mb86r0xgdc.c b/drivers/video/mb86r0xgdc.c deleted file mode 100644 index bb7a749..0000000 --- a/drivers/video/mb86r0xgdc.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser weisserm@arcor.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic - * controller. - */ - -#include <common.h> - -#include <malloc.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <video_fb.h> -#include "videomodes.h" - -/* - * 4MB (at the end of system RAM) - */ -#define VIDEO_MEM_SIZE 0x400000 - -#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ - -/* - * Graphic Device - */ -static GraphicDevice mb86r0x; - -static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr, - u32 *videomem) -{ - struct ctfb_res_modes var_mode; - u32 dcm1, dcm2, dcm3; - u16 htp, hdp, hdb, hsp, vtr, vsp, vdp; - u8 hsw, vsw; - u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1; - u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh; - unsigned long div; - int bpp; - - bpp = video_get_params(&var_mode, modestr); - - if (bpp == 0) { - var_mode.xres = 640; - var_mode.yres = 480; - var_mode.pixclock = 39721; /* 25MHz */ - var_mode.left_margin = 48; - var_mode.right_margin = 16; - var_mode.upper_margin = 33; - var_mode.lower_margin = 10; - var_mode.hsync_len = 96; - var_mode.vsync_len = 2; - var_mode.sync = 0; - var_mode.vmode = 0; - bpp = 15; - } - - /* Fill memory with white */ - memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2); - - mb86r0x.winSizeX = var_mode.xres; - mb86r0x.winSizeY = var_mode.yres; - - /* LCD base clock is ~ 660MHZ. We do calculations in kHz */ - div = 660000 / (1000000000L / var_mode.pixclock); - if (div > 64) - div = 64; - if (0 == div) - div = 1; - - dcm1 = (div - 1) << 8; - dcm2 = 0x00000000; - if (var_mode.sync & FB_SYNC_CLK_INV) - dcm3 = 0x00000100; - else - dcm3 = 0x00000000; - - htp = var_mode.left_margin + var_mode.xres + - var_mode.hsync_len + var_mode.right_margin; - hdp = var_mode.xres; - hdb = var_mode.xres; - hsp = var_mode.xres + var_mode.right_margin; - hsw = var_mode.hsync_len; - - vsw = var_mode.vsync_len; - vtr = var_mode.upper_margin + var_mode.yres + - var_mode.vsync_len + var_mode.lower_margin; - vsp = var_mode.yres + var_mode.lower_margin; - vdp = var_mode.yres; - - l2m = ((var_mode.yres - 1) << (0)) | - (((var_mode.xres * 2) / 64) << (16)) | - ((1) << (31)); - - l2em = (1 << 0) | (1 << 1); - - l2oa0 = mb86r0x.frameAdrs; - l2da0 = mb86r0x.frameAdrs; - l2oa1 = mb86r0x.frameAdrs; - l2da1 = mb86r0x.frameAdrs; - l2dx = 0; - l2dy = 0; - l2wx = 0; - l2wy = 0; - l2ww = var_mode.xres; - l2wh = var_mode.yres - 1; - - writel(dcm1, &dsp->dcm1); - writel(dcm2, &dsp->dcm2); - writel(dcm3, &dsp->dcm3); - - writew(htp, &dsp->htp); - writew(hdp, &dsp->hdp); - writew(hdb, &dsp->hdb); - writew(hsp, &dsp->hsp); - writeb(hsw, &dsp->hsw); - - writeb(vsw, &dsp->vsw); - writew(vtr, &dsp->vtr); - writew(vsp, &dsp->vsp); - writew(vdp, &dsp->vdp); - - writel(l2m, &dsp->l2m); - writel(l2em, &dsp->l2em); - writel(l2oa0, &dsp->l2oa0); - writel(l2da0, &dsp->l2da0); - writel(l2oa1, &dsp->l2oa1); - writel(l2da1, &dsp->l2da1); - writew(l2dx, &dsp->l2dx); - writew(l2dy, &dsp->l2dy); - writew(l2wx, &dsp->l2wx); - writew(l2wy, &dsp->l2wy); - writew(l2ww, &dsp->l2ww); - writew(l2wh, &dsp->l2wh); - - writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1); -} - -void *video_hw_init(void) -{ - struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE; - GraphicDevice *pGD = &mb86r0x; - char *s; - u32 *vid; - - memset(pGD, 0, sizeof(GraphicDevice)); - - pGD->gdfIndex = GDF_15BIT_555RGB; - pGD->gdfBytesPP = 2; - pGD->memSize = VIDEO_MEM_SIZE; - pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; - - vid = (u32 *)pGD->frameAdrs; - - s = getenv("videomode"); - if (s != NULL) - dsp_init(&gdc->dsp0, s, vid); - - s = getenv("videomode1"); - if (s != NULL) - dsp_init(&gdc->dsp1, s, vid); - - return pGD; -} diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h deleted file mode 100644 index 8175621..0000000 --- a/include/configs/jadecpu.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser weisserm@arcor.de - * - * Configuation settings for the jadecpu board - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MB86R0x -#define CONFIG_MB86R0x_IOCLK get_bus_freq(0) -#define CONFIG_SYS_TEXT_BASE 0x10000000 - - -#define CONFIG_USE_ARCH_MEMCPY -#define CONFIG_USE_ARCH_MEMSET - -#define MACH_TYPE_JADECPU 2636 - -#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU - -/* - * Environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "gs_fast_boot=setenv bootdelay 5\0" \ - "gs_slow_boot=setenv bootdelay 10\0" \ - "bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \ - "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \ - "bootelf 0x40000000\0" \ - "" - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_BOARD_LATE_INIT - -/* - * Compressions - */ -#define CONFIG_LZO - -/* - * Hardware drivers - */ - -/* - * Serial - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */ -#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */ -#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */ -#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */ - -#define CONFIG_CONS_INDEX 4 - -/* - * Ethernet - */ -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x02000000 -#define CONFIG_SMC911X_16_BIT - -/* - * Video - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_MB86R0xGDC -#define CONFIG_SYS_WHITE_ON_BLACK -#define CONFIG_CFB_CONSOLE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024) -#define VIDEO_FB_16BPP_WORD_SWAP -#define VIDEO_KBD_INIT_FCT 0 -#define VIDEO_TSTC_FCT serial_stub_tstc -#define VIDEO_GETC_FCT serial_stub_getc - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG - -#define CONFIG_CMD_BMP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_CACHE - -#define CONFIG_SYS_HUSH_PARSER - -/* USB */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR 0x01008000 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (128 * 1024) - -/* - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */ - -#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "jade> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 - -#define CONFIG_PREBOOT "" - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" -#define CONFIG_AUTOBOOT_STOP_STR "stopgs" - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 << 20) -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20) - -/* - * Clock reset generator init - */ -#define CONFIG_SYS_CRG_CRHA_INIT 0xffff -#define CONFIG_SYS_CRG_CRPA_INIT 0xffff -#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe -#define CONFIG_SYS_CRG_CRHB_INIT 0xffff -#define CONFIG_SYS_CRG_CRAM_INIT 0xffef - -/* - * Memory controller settings - */ -#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */ -#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */ -#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/ -#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008 -#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008 -#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804 -#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */ -#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */ -#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */ - -/* - * DDR2 controller init settings - */ -#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555 -#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002 -#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003 -#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f -#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000 -#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */ -#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032 -#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418 -#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32 -#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141 -#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002 -#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001 -#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001 -#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103 -#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F -#define CONFIG_SYS_DDR2_DROS_INIT 0x0001 - -/* - * DRAM init sequence - */ - -/* PALL Command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017 -#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400 - -/* EMR(2) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006 -#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000 - -/* EMR(3) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007 -#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000 - -/* EMR(1) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005 -#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000 - -/* MRS command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004 -#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532 - -/* PALL command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017 -#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400 - -/* REF command 1 */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f -#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000 - -/* MRS command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004 -#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432 - -/* EMR(1) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005 -#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380 - -/* EMR(1) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005 -#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002 - -#endif /* __CONFIG_H */ diff --git a/include/serial.h b/include/serial.h index 66ed12c..3d2e569 100644 --- a/include/serial.h +++ b/include/serial.h @@ -29,7 +29,7 @@ extern struct serial_device *default_serial_console(void); #if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_440) || \ - defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ + defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \

These are still non-generic boards.

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Greg Ungerer greg.ungerer@opengear.com Acked-by: Marek Vasut marex@denx.de ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/arm/Kconfig | 10 - arch/arm/cpu/arm920t/Makefile | 1 - arch/arm/cpu/arm920t/ks8695/Makefile | 9 - arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 189 ------------- arch/arm/cpu/arm920t/ks8695/timer.c | 77 ------ arch/arm/include/asm/arch-ks8695/platform.h | 294 --------------------- board/cm4008/Kconfig | 12 - board/cm4008/MAINTAINERS | 6 - board/cm4008/Makefile | 8 - board/cm4008/cm4008.c | 88 ------- board/cm4008/config.mk | 1 - board/cm4008/flash.c | 395 ---------------------------- board/cm41xx/Kconfig | 12 - board/cm41xx/MAINTAINERS | 6 - board/cm41xx/Makefile | 8 - board/cm41xx/cm41xx.c | 88 ------- board/cm41xx/config.mk | 1 - board/cm41xx/flash.c | 395 ---------------------------- configs/cm4008_defconfig | 2 - configs/cm41xx_defconfig | 2 - doc/README.scrapyard | 2 + drivers/net/Makefile | 1 - drivers/net/ks8695eth.c | 229 ---------------- drivers/serial/Makefile | 1 - drivers/serial/serial.c | 2 - drivers/serial/serial_ks8695.c | 121 --------- include/configs/cm4008.h | 104 -------- include/configs/cm41xx.h | 104 -------- include/netdev.h | 1 - include/serial.h | 1 - 30 files changed, 2 insertions(+), 2168 deletions(-) delete mode 100644 arch/arm/cpu/arm920t/ks8695/Makefile delete mode 100644 arch/arm/cpu/arm920t/ks8695/lowlevel_init.S delete mode 100644 arch/arm/cpu/arm920t/ks8695/timer.c delete mode 100644 arch/arm/include/asm/arch-ks8695/platform.h delete mode 100644 board/cm4008/Kconfig delete mode 100644 board/cm4008/MAINTAINERS delete mode 100644 board/cm4008/Makefile delete mode 100644 board/cm4008/cm4008.c delete mode 100644 board/cm4008/config.mk delete mode 100644 board/cm4008/flash.c delete mode 100644 board/cm41xx/Kconfig delete mode 100644 board/cm41xx/MAINTAINERS delete mode 100644 board/cm41xx/Makefile delete mode 100644 board/cm41xx/cm41xx.c delete mode 100644 board/cm41xx/config.mk delete mode 100644 board/cm41xx/flash.c delete mode 100644 configs/cm4008_defconfig delete mode 100644 configs/cm41xx_defconfig delete mode 100644 drivers/net/ks8695eth.c delete mode 100644 drivers/serial/serial_ks8695.c delete mode 100644 include/configs/cm4008.h delete mode 100644 include/configs/cm41xx.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 32d89e1..e930bba 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -88,14 +88,6 @@ config TARGET_SCB9328 bool "Support scb9328" select CPU_ARM920T

-config TARGET_CM4008 - bool "Support cm4008" - select CPU_ARM920T - -config TARGET_CM41XX - bool "Support cm41xx" - select CPU_ARM920T - config TARGET_VCMA9 bool "Support VCMA9" select CPU_ARM920T @@ -758,8 +750,6 @@ source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" source "board/cirrus/edb93xx/Kconfig" -source "board/cm4008/Kconfig" -source "board/cm41xx/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_fx6/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig" diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index a16838b..29a350c 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -13,5 +13,4 @@ obj-$(CONFIG_USE_IRQ) += interrupts.o obj-$(if $(filter a320,$(SOC)),y) += a320/ obj-$(CONFIG_EP93XX) += ep93xx/ obj-$(CONFIG_IMX) += imx/ -obj-$(CONFIG_KS8695) += ks8695/ obj-$(CONFIG_S3C24X0) += s3c24x0/ diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile deleted file mode 100644 index 400aa89..0000000 --- a/arch/arm/cpu/arm920t/ks8695/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = lowlevel_init.o -obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S deleted file mode 100644 index a2a07f2..0000000 --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +++ /dev/null @@ -1,189 +0,0 @@ -/* - * lowlevel_init.S - basic hardware initialization for the KS8695 CPU - * - * Copyright (c) 2004-2005, Greg Ungerer greg.ungerer@opengear.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/platform.h> - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - -/* - ************************************************************************* - * - * Handy dandy macros - * - ************************************************************************* - */ - -/* Delay a bit */ -.macro DELAY_FOR cycles, reg0 - ldr \reg0, =\cycles - subs \reg0, \reg0, #1 - subne pc, pc, #0xc -.endm - -/* - ************************************************************************* - * - * Some local storage. - * - ************************************************************************* - */ - -/* Should we boot with an interactive console or not */ -.globl serial_console - -/* - ************************************************************************* - * - * Raw hardware initialization code. The important thing is to get - * SDRAM setup and running. We do some other basic things here too, - * like getting the PLL set for high speed, and init the LEDs. - * - ************************************************************************* - */ - -.globl lowlevel_init -lowlevel_init: - -#if DEBUG - /* - * enable UART for early debug trace - */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR) - mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE) - str r2, [r1] - ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL) - mov r2, #KS8695_UART_LINEC_WLEN8 - str r2, [r1] /* 8 data bits, no parity, 1 stop */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) - mov r2, #0x41 - str r2, [r1] /* write 'A' */ -#endif -#if DEBUG - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) - mov r2, #0x42 - str r2, [r1] -#endif - - /* - * remap the memory and flash regions. we want to end up with - * ram from address 0, and flash at 32MB. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0) - ldr r2, =0xbfc00040 - str r2, [r1] /* large flash map */ - ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */ -highflash: - ldr r2, =0x8fe00040 - str r2, [r1] /* remap flash range */ - - /* - * remap the second select region to the 4MB immediately after - * the first region. This way if you have a larger flash (say 8Mb) - * then you can have it all mapped nicely. Has no effect if you - * only have a 4Mb or smaller flash. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1) - ldr r2, =0x9fe40040 - str r2, [r1] /* remap flash2 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) - ldr r2, =0x30000005 - str r2, [r1] /* enable both flash selects */ - -#ifdef CONFIG_CM41xx - /* - * map the second flash chip, using the external IO lines. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0) - ldr r2, =0xafe80b6d - str r2, [r1] /* remap io0 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1) - ldr r2, =0xbfec0b6d - str r2, [r1] /* remap io1 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) - ldr r2, =0x30050005 - str r2, [r1] /* enable second flash */ -#endif - - /* - * before relocating, we have to setup RAM timing - */ - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0) -#if (PHYS_SDRAM_1_SIZE == 0x02000000) - ldr r2, =0x7fc0000e /* 32MB */ -#else - ldr r2, =0x3fc0000e /* 16MB */ -#endif - str r2, [r1] /* configure sdram bank0 setup */ - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1) - mov r2, #0 - str r2, [r1] /* configure sdram bank1 setup */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL) - ldr r2, =0x0000000a - str r2, [r1] /* set RAS/CAS timing */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) - ldr r2, =0x00030000 - str r2, [r1] /* send NOP command */ - DELAY_FOR 0x100, r0 - ldr r2, =0x00010000 - str r2, [r1] /* send PRECHARGE-ALL */ - DELAY_FOR 0x100, r0 - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH) - ldr r2, =0x00000020 - str r2, [r1] /* set for fast refresh */ - DELAY_FOR 0x100, r0 - ldr r2, =0x00000190 - str r2, [r1] /* set normal refresh timing */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) - ldr r2, =0x00020033 - str r2, [r1] /* send mode command */ - DELAY_FOR 0x100, r0 - ldr r2, =0x01f00000 - str r2, [r1] /* enable sdram fifos */ - - /* - * set pll to top speed - */ - ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK) - mov r2, #0 - str r2, [r1] /* set pll clock to 166MHz */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0) - ldr r2, [r1] /* Get switch ctrl0 register */ - and r2, r2, #0x0fc00000 /* Mask out LED control bits */ - orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */ - str r2, [r1] - -#ifdef CONFIG_CM4008 - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE) - ldr r2, =0x0000fe30 - str r2, [r1] /* enable LED's as outputs */ - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA) - ldr r2, =0x0000fe20 - str r2, [r1] /* turn on power LED */ -#endif -#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx) - ldr r2, [r1] /* get current GPIO input data */ - tst r2, #0x8 /* check if "erase" depressed */ - beq nobutton - mov r2, #0 /* be quiet on boot, no console */ - ldr r1, =serial_console - str r2, [r1] -nobutton: -#endif - - add lr, lr, #0x02000000 /* flash is now mapped high */ - add ip, ip, #0x02000000 /* this is a hack */ - mov pc, lr /* all done, return */ - -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c deleted file mode 100644 index 23db557..0000000 --- a/arch/arm/cpu/arm920t/ks8695/timer.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2004-2005, Greg Ungerer greg.ungerer@opengear.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/platform.h> - -/* - * Initial timer set constants. Nothing complicated, just set for a 1ms - * tick. - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1) -#define TIMER_COUNT (TIMER_INTERVAL / 2) -#define TIMER_PULSE TIMER_COUNT - -/* - * Handy KS8695 register access functions. - */ -#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a))) -#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v) - -ulong timer_ticks; - -int timer_init (void) -{ - /* Set the hadware timer for 1ms */ - ks8695_write(KS8695_TIMER1, TIMER_COUNT); - ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); - ks8695_write(KS8695_TIMER_CTRL, 0x2); - timer_ticks = 0; - - return 0; -} - -ulong get_timer_masked(void) -{ - /* Check for timer wrap */ - if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) { - /* Clear interrupt condition */ - ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1); - timer_ticks++; - } - return timer_ticks; -} - -ulong get_timer(ulong base) -{ - return (get_timer_masked() - base); -} - -void __udelay(ulong usec) -{ - ulong start = get_timer_masked(); - ulong end; - - /* Only 1ms resolution :-( */ - end = usec / 1000; - while (get_timer(start) < end) - ; -} - -void reset_cpu (ulong ignored) -{ - ulong tc; - - /* Set timer0 to watchdog, and let it timeout */ - tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2; - ks8695_write(KS8695_TIMER_CTRL, tc); - ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff)); - ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1)); - - /* Should only wait here till watchdog resets */ - for (;;) - ; -} diff --git a/arch/arm/include/asm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h deleted file mode 100644 index 02f6049..0000000 --- a/arch/arm/include/asm/arch-ks8695/platform.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __address_h -#define __address_h 1 - -#define KS8695_SDRAM_START 0x00000000 -#define KS8695_SDRAM_SIZE 0x01000000 -#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE -#define KS8695_MEM_START KS8695_SDRAM_START - -#define KS8695_PCMCIA_IO_BASE 0x03800000 -#define KS8695_PCMCIA_IO_SIZE 0x00040000 - -#define KS8695_IO_BASE 0x03FF0000 -#define KS8695_IO_SIZE 0x00010000 - -#define KS8695_SYSTEN_CONFIG 0x00 -#define KS8695_SYSTEN_BUS_CLOCK 0x04 - -#define KS8695_FLASH_START 0x02800000 -#define KS8695_FLASH_SIZE 0x00400000 - -/*i/o control registers offset difinitions*/ -#define KS8695_IO_CTRL0 0x4000 -#define KS8695_IO_CTRL1 0x4004 -#define KS8695_IO_CTRL2 0x4008 -#define KS8695_IO_CTRL3 0x400C - -/*memory control registers offset difinitions*/ -#define KS8695_MEM_CTRL0 0x4010 -#define KS8695_MEM_CTRL1 0x4014 -#define KS8695_MEM_CTRL2 0x4018 -#define KS8695_MEM_CTRL3 0x401C -#define KS8695_MEM_GENERAL 0x4020 -#define KS8695_SDRAM_CTRL0 0x4030 -#define KS8695_SDRAM_CTRL1 0x4034 -#define KS8695_SDRAM_GENERAL 0x4038 -#define KS8695_SDRAM_BUFFER 0x403C -#define KS8695_SDRAM_REFRESH 0x4040 - -/*WAN control registers offset difinitions*/ -#define KS8695_WAN_DMA_TX 0x6000 -#define KS8695_WAN_DMA_RX 0x6004 -#define KS8695_WAN_DMA_TX_START 0x6008 -#define KS8695_WAN_DMA_RX_START 0x600C -#define KS8695_WAN_TX_LIST 0x6010 -#define KS8695_WAN_RX_LIST 0x6014 -#define KS8695_WAN_MAC_LOW 0x6018 -#define KS8695_WAN_MAC_HIGH 0x601C -#define KS8695_WAN_MAC_ELOW 0x6080 -#define KS8695_WAN_MAC_EHIGH 0x6084 - -/*LAN control registers offset difinitions*/ -#define KS8695_LAN_DMA_TX 0x8000 -#define KS8695_LAN_DMA_RX 0x8004 -#define KS8695_LAN_DMA_TX_START 0x8008 -#define KS8695_LAN_DMA_RX_START 0x800C -#define KS8695_LAN_TX_LIST 0x8010 -#define KS8695_LAN_RX_LIST 0x8014 -#define KS8695_LAN_MAC_LOW 0x8018 -#define KS8695_LAN_MAC_HIGH 0x801C -#define KS8695_LAN_MAC_ELOW 0X8080 -#define KS8695_LAN_MAC_EHIGH 0X8084 - -/*HPNA control registers offset difinitions*/ -#define KS8695_HPNA_DMA_TX 0xA000 -#define KS8695_HPNA_DMA_RX 0xA004 -#define KS8695_HPNA_DMA_TX_START 0xA008 -#define KS8695_HPNA_DMA_RX_START 0xA00C -#define KS8695_HPNA_TX_LIST 0xA010 -#define KS8695_HPNA_RX_LIST 0xA014 -#define KS8695_HPNA_MAC_LOW 0xA018 -#define KS8695_HPNA_MAC_HIGH 0xA01C -#define KS8695_HPNA_MAC_ELOW 0xA080 -#define KS8695_HPNA_MAC_EHIGH 0xA084 - -/*UART control registers offset difinitions*/ -#define KS8695_UART_RX_BUFFER 0xE000 -#define KS8695_UART_TX_HOLDING 0xE004 - -#define KS8695_UART_FIFO_CTRL 0xE008 -#define KS8695_UART_FIFO_TRIG01 0x00 -#define KS8695_UART_FIFO_TRIG04 0x80 -#define KS8695_UART_FIFO_TXRST 0x03 -#define KS8695_UART_FIFO_RXRST 0x02 -#define KS8695_UART_FIFO_FEN 0x01 - -#define KS8695_UART_LINE_CTRL 0xE00C -#define KS8695_UART_LINEC_BRK 0x40 -#define KS8695_UART_LINEC_EPS 0x10 -#define KS8695_UART_LINEC_PEN 0x08 -#define KS8695_UART_LINEC_STP2 0x04 -#define KS8695_UART_LINEC_WLEN8 0x03 -#define KS8695_UART_LINEC_WLEN7 0x02 -#define KS8695_UART_LINEC_WLEN6 0x01 -#define KS8695_UART_LINEC_WLEN5 0x00 - -#define KS8695_UART_MODEM_CTRL 0xE010 -#define KS8695_UART_MODEMC_RTS 0x02 -#define KS8695_UART_MODEMC_DTR 0x01 - -#define KS8695_UART_LINE_STATUS 0xE014 -#define KS8695_UART_LINES_TXFE 0x20 -#define KS8695_UART_LINES_BE 0x10 -#define KS8695_UART_LINES_FE 0x08 -#define KS8695_UART_LINES_PE 0x04 -#define KS8695_UART_LINES_OE 0x02 -#define KS8695_UART_LINES_RXFE 0x01 -#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE) - -#define KS8695_UART_MODEM_STATUS 0xE018 -#define KS8695_UART_MODEM_DCD 0x80 -#define KS8695_UART_MODEM_DSR 0x20 -#define KS8695_UART_MODEM_CTS 0x10 -#define KS8695_UART_MODEM_DDCD 0x08 -#define KS8695_UART_MODEM_DDSR 0x02 -#define KS8695_UART_MODEM_DCTS 0x01 -#define UART8695_MODEM_ANY 0xFF - -#define KS8695_UART_DIVISOR 0xE01C -#define KS8695_UART_STATUS 0xE020 - -/*Interrupt controlller registers offset difinitions*/ -#define KS8695_INT_CONTL 0xE200 -#define KS8695_INT_ENABLE 0xE204 -#define KS8695_INT_ENABLE_MODEM 0x0800 -#define KS8695_INT_ENABLE_ERR 0x0400 -#define KS8695_INT_ENABLE_RX 0x0200 -#define KS8695_INT_ENABLE_TX 0x0100 - -#define KS8695_INT_STATUS 0xE208 -#define KS8695_INT_WAN_PRIORITY 0xE20C -#define KS8695_INT_HPNA_PRIORITY 0xE210 -#define KS8695_INT_LAN_PRIORITY 0xE214 -#define KS8695_INT_TIMER_PRIORITY 0xE218 -#define KS8695_INT_UART_PRIORITY 0xE21C -#define KS8695_INT_EXT_PRIORITY 0xE220 -#define KS8695_INT_CHAN_PRIORITY 0xE224 -#define KS8695_INT_BUSERROR_PRO 0xE228 -#define KS8695_INT_MASK_STATUS 0xE22C -#define KS8695_FIQ_PEND_PRIORITY 0xE230 -#define KS8695_IRQ_PEND_PRIORITY 0xE234 - -/*timer registers offset difinitions*/ -#define KS8695_TIMER_CTRL 0xE400 -#define KS8695_TIMER1 0xE404 -#define KS8695_TIMER0 0xE408 -#define KS8695_TIMER1_PCOUNT 0xE40C -#define KS8695_TIMER0_PCOUNT 0xE410 - -/*GPIO registers offset difinitions*/ -#define KS8695_GPIO_MODE 0xE600 -#define KS8695_GPIO_CTRL 0xE604 -#define KS8695_GPIO_DATA 0xE608 - -/*SWITCH registers offset difinitions*/ -#define KS8695_SWITCH_CTRL0 0xE800 -#define KS8695_SWITCH_CTRL1 0xE804 -#define KS8695_SWITCH_PORT1 0xE808 -#define KS8695_SWITCH_PORT2 0xE80C -#define KS8695_SWITCH_PORT3 0xE810 -#define KS8695_SWITCH_PORT4 0xE814 -#define KS8695_SWITCH_PORT5 0xE818 -#define KS8695_SWITCH_AUTO0 0xE81C -#define KS8695_SWITCH_AUTO1 0xE820 -#define KS8695_SWITCH_LUE_CTRL 0xE824 -#define KS8695_SWITCH_LUE_HIGH 0xE828 -#define KS8695_SWITCH_LUE_LOW 0xE82C -#define KS8695_SWITCH_ADVANCED 0xE830 - -#define KS8695_SWITCH_LPPM12 0xE874 -#define KS8695_SWITCH_LPPM34 0xE878 - -/*host communication registers difinitions*/ -#define KS8695_DSCP_HIGH 0xE834 -#define KS8695_DSCP_LOW 0xE838 -#define KS8695_SWITCH_MAC_HIGH 0xE83C -#define KS8695_SWITCH_MAC_LOW 0xE840 - -/*miscellaneours registers difinitions*/ -#define KS8695_MANAGE_COUNTER 0xE844 -#define KS8695_MANAGE_DATA 0xE848 -#define KS8695_LAN12_POWERMAGR 0xE84C -#define KS8695_LAN34_POWERMAGR 0xE850 - -#define KS8695_DEVICE_ID 0xEA00 -#define KS8695_REVISION_ID 0xEA04 - -#define KS8695_MISC_CONTROL 0xEA08 -#define KS8695_WAN_CONTROL 0xEA0C -#define KS8695_WAN_POWERMAGR 0xEA10 -#define KS8695_WAN_PHY_CONTROL 0xEA14 -#define KS8695_WAN_PHY_STATUS 0xEA18 - -/* bus clock definitions*/ -#define KS8695_BUS_CLOCK_125MHZ 0x0 -#define KS8695_BUS_CLOCK_100MHZ 0x1 -#define KS8695_BUS_CLOCK_62MHZ 0x2 -#define KS8695_BUS_CLOCK_50MHZ 0x3 -#define KS8695_BUS_CLOCK_41MHZ 0x4 -#define KS8695_BUS_CLOCK_33MHZ 0x5 -#define KS8695_BUS_CLOCK_31MHZ 0x6 -#define KS8695_BUS_CLOCK_25MHZ 0x7 - -/* ------------------------------------------------------------------------------- - * definations for IRQ - * -------------------------------------------------------------------------------*/ - -#define KS8695_INT_EXT_INT0 2 -#define KS8695_INT_EXT_INT1 3 -#define KS8695_INT_EXT_INT2 4 -#define KS8695_INT_EXT_INT3 5 -#define KS8695_INT_TIMERINT0 6 -#define KS8695_INT_TIMERINT1 7 -#define KS8695_INT_UART_TX 8 -#define KS8695_INT_UART_RX 9 -#define KS8695_INT_UART_LINE_ERR 10 -#define KS8695_INT_UART_MODEMS 11 -#define KS8695_INT_LAN_STOP_RX 12 -#define KS8695_INT_LAN_STOP_TX 13 -#define KS8695_INT_LAN_BUF_RX_STATUS 14 -#define KS8695_INT_LAN_BUF_TX_STATUS 15 -#define KS8695_INT_LAN_RX_STATUS 16 -#define KS8695_INT_LAN_TX_STATUS 17 -#define KS8695_INT_HPAN_STOP_RX 18 -#define KS8695_INT_HPNA_STOP_TX 19 -#define KS8695_INT_HPNA_BUF_RX_STATUS 20 -#define KS8695_INT_HPNA_BUF_TX_STATUS 21 -#define KS8695_INT_HPNA_RX_STATUS 22 -#define KS8695_INT_HPNA_TX_STATUS 23 -#define KS8695_INT_BUS_ERROR 24 -#define KS8695_INT_WAN_STOP_RX 25 -#define KS8695_INT_WAN_STOP_TX 26 -#define KS8695_INT_WAN_BUF_RX_STATUS 27 -#define KS8695_INT_WAN_BUF_TX_STATUS 28 -#define KS8695_INT_WAN_RX_STATUS 29 -#define KS8695_INT_WAN_TX_STATUS 30 - -#define KS8695_INT_UART KS8695_INT_UART_TX - -/* ------------------------------------------------------------------------------- - * Interrupt bit positions - * - * ------------------------------------------------------------------------------- - */ - -#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 ) -#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 ) -#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 ) -#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 ) -#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 ) -#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 ) -#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX ) -#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX ) -#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR ) -#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS ) -#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX ) -#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX ) -#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX ) -#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX ) -#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS ) -#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS -#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS ) -#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS ) -#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR ) -#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX ) -#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX ) -#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS ) -#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS ) - -#define KS8695_SC_VALID_INT 0xFFFFFFFF -#define MAXIRQNUM 31 - -/* - * Timer definitions - * - * Use timer 1 & 2 - * (both run at 25MHz). - * - */ -#define TICKS_PER_uSEC 25 -#define mSEC_1 1000 -#define mSEC_10 (mSEC_1 * 10) - -#endif - -/* END */ diff --git a/board/cm4008/Kconfig b/board/cm4008/Kconfig deleted file mode 100644 index de87d5b..0000000 --- a/board/cm4008/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CM4008 - -config SYS_BOARD - default "cm4008" - -config SYS_SOC - default "ks8695" - -config SYS_CONFIG_NAME - default "cm4008" - -endif diff --git a/board/cm4008/MAINTAINERS b/board/cm4008/MAINTAINERS deleted file mode 100644 index 5f08bc3..0000000 --- a/board/cm4008/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM4008 BOARD -M: Greg Ungerer greg.ungerer@opengear.com -S: Maintained -F: board/cm4008/ -F: include/configs/cm4008.h -F: configs/cm4008_defconfig diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile deleted file mode 100644 index 04b1529..0000000 --- a/board/cm4008/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cm4008.o flash.o diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c deleted file mode 100644 index 740e164..0000000 --- a/board/cm4008/cm4008.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/platform.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) -#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b) - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ -int env_flash_cmdline (void) -{ - char *sp = (char *) 0x0201c020; - char *ep; - int len; - - /* Check if "erase" push button is depressed */ - if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) { - printf("### Entering network recovery mode...\n"); - setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0"); - setenv("bootcmd", "bootp 0x400000; gofsk 0x400000"); - setenv("bootdelay", "2"); - return 0; - } - - /* Check for flash based kernel boot args to use as default */ - for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++) - ; - - if ((len > 0) && (len <1024)) - setenv("bootargs", sp); - - return 0; -} - -int board_late_init (void) -{ - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return ks8695_eth_initialize(); -} - -int board_init (void) -{ - /* arch number of CM4008 */ - gd->bd->bi_arch_number = 624; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - /* power down all but port 0 on the switch */ - ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005); - ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005); - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/cm4008/config.mk b/board/cm4008/config.mk deleted file mode 100644 index 0d5923b..0000000 --- a/board/cm4008/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00f00000 diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c deleted file mode 100644 index 8315a57..0000000 --- a/board/cm4008/flash.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/byteorder/swab.h> -#include <asm/sections.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, unsigned char data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - /* ignore for now */ - flash_info[i].flash_id = FLASH_UNKNOWN; - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start), - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) - return; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info) -{ - volatile unsigned char value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = 0xAA; - addr[0x2AAA] = 0x55; - addr[0x5555] = 0x90; - - mb (); - value = addr[0]; - - switch (value) { - - case (unsigned char)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = 0xFF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[2]; /* device ID */ - - switch (value) { - - case (unsigned char)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (unsigned char)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = 0xFF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - ulong type; - int rcode = 0; - ulong start; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - volatile unsigned char *addr; - unsigned char status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - addr = (volatile unsigned char *) (info->start[sect]); - *addr = 0x50; /* clear status register */ - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x50; /* clear status register cmd */ - *addr = 0xFF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - unsigned char data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - wp = addr; - port_width = 1; - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, unsigned char data) -{ - volatile unsigned char *addr = (volatile unsigned char *) dest; - ulong status; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - *addr = 0x40; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0xFF; /* restore read mode */ - return (1); - } - } - - *addr = 0xFF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/cm41xx/Kconfig b/board/cm41xx/Kconfig deleted file mode 100644 index 99e675b..0000000 --- a/board/cm41xx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CM41XX - -config SYS_BOARD - default "cm41xx" - -config SYS_SOC - default "ks8695" - -config SYS_CONFIG_NAME - default "cm41xx" - -endif diff --git a/board/cm41xx/MAINTAINERS b/board/cm41xx/MAINTAINERS deleted file mode 100644 index f10eeb5..0000000 --- a/board/cm41xx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM41XX BOARD -#M: - -S: Maintained -F: board/cm41xx/ -F: include/configs/cm41xx.h -F: configs/cm41xx_defconfig diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile deleted file mode 100644 index b71ea05..0000000 --- a/board/cm41xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cm41xx.o flash.o diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c deleted file mode 100644 index eabad48..0000000 --- a/board/cm41xx/cm41xx.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger mgroeger@sysgo.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/platform.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) -#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b) - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ -int env_flash_cmdline (void) -{ - char *sp = (char *) 0x0201c020; - char *ep; - int len; - - /* Check if "erase" push button is depressed */ - if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) { - printf("### Entering network recovery mode...\n"); - setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0"); - setenv("bootcmd", "bootp 0x400000; gofsk 0x400000"); - setenv("bootdelay", "2"); - return 0; - } - - /* Check for flash based kernel boot args to use as default */ - for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++) - ; - - if ((len > 0) && (len <1024)) - setenv("bootargs", sp); - - return 0; -} - -int board_late_init (void) -{ - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return ks8695_eth_initialize(); -} - -int board_init (void) -{ - /* arch number of CM41xx */ - gd->bd->bi_arch_number = 672; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - /* power down all but port 0 on the switch */ - ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005); - ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005); - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/cm41xx/config.mk b/board/cm41xx/config.mk deleted file mode 100644 index 0d5923b..0000000 --- a/board/cm41xx/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00f00000 diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c deleted file mode 100644 index 8315a57..0000000 --- a/board/cm41xx/flash.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/byteorder/swab.h> -#include <asm/sections.h> - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, unsigned char data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - /* ignore for now */ - flash_info[i].flash_id = FLASH_UNKNOWN; - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start), - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) - return; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info) -{ - volatile unsigned char value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = 0xAA; - addr[0x2AAA] = 0x55; - addr[0x5555] = 0x90; - - mb (); - value = addr[0]; - - switch (value) { - - case (unsigned char)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = 0xFF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[2]; /* device ID */ - - switch (value) { - - case (unsigned char)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (unsigned char)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = 0xFF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - ulong type; - int rcode = 0; - ulong start; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - volatile unsigned char *addr; - unsigned char status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - addr = (volatile unsigned char *) (info->start[sect]); - *addr = 0x50; /* clear status register */ - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x50; /* clear status register cmd */ - *addr = 0xFF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - unsigned char data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - wp = addr; - port_width = 1; - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, unsigned char data) -{ - volatile unsigned char *addr = (volatile unsigned char *) dest; - ulong status; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - *addr = 0x40; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0xFF; /* restore read mode */ - return (1); - } - } - - *addr = 0xFF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/configs/cm4008_defconfig b/configs/cm4008_defconfig deleted file mode 100644 index 487589d..0000000 --- a/configs/cm4008_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_CM4008=y diff --git a/configs/cm41xx_defconfig b/configs/cm41xx_defconfig deleted file mode 100644 index 15e9362..0000000 --- a/configs/cm41xx_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_CM41XX=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index ce9dcb1..ba84c90 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +cm4008 arm arm920t - - Greg Ungerer greg.ungerer@opengear.com +cm41xx arm arm920t - - dkb arm arm926ejs - - Lei Wen leiwen@marvell.com zmx25 arm arm926ejs - - Matthias Weisser weisserm@arcor.de jadecpu arm arm926ejs - - Matthias Weisser weisserm@arcor.de diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 46c4ac6..da5e2bc 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o -obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o obj-$(CONFIG_MACB) += macb.o diff --git a/drivers/net/ks8695eth.c b/drivers/net/ks8695eth.c deleted file mode 100644 index b4822e9..0000000 --- a/drivers/net/ks8695eth.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * ks8695eth.c -- KS8695 ethernet driver - * - * (C) Copyright 2004-2005, Greg Ungerer greg.ungerer@opengear.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/****************************************************************************/ - -#include <common.h> -#include <malloc.h> -#include <net.h> -#include <asm/io.h> -#include <asm/arch/platform.h> - -/****************************************************************************/ - -/* - * Hardware register access to the KS8695 LAN ethernet port - * (well, it is the 4 port switch really). - */ -#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) -#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v) - -/****************************************************************************/ - -/* - * Define the descriptor in-memory data structures. - */ -struct ks8695_txdesc { - uint32_t owner; - uint32_t ctrl; - uint32_t addr; - uint32_t next; -}; - -struct ks8695_rxdesc { - uint32_t status; - uint32_t ctrl; - uint32_t addr; - uint32_t next; -}; - -/****************************************************************************/ - -/* - * Allocate local data structures to use for receiving and sending - * packets. Just to keep it all nice and simple. - */ - -#define TXDESCS 4 -#define RXDESCS 4 -#define BUFSIZE 2048 - -volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256))); -volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256))); -volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));; - -/****************************************************************************/ - -/* - * Ideally we want to use the MAC address stored in flash. - * But we do some sanity checks in case they are not present - * first. - */ -unsigned char eth_mac[] = { - 0x00, 0x13, 0xc6, 0x00, 0x00, 0x00 -}; - -void ks8695_getmac(void) -{ - unsigned char *fp; - int i; - - /* Check if flash MAC is valid */ - fp = (unsigned char *) 0x0201c000; - for (i = 0; (i < 6); i++) { - if ((fp[i] != 0) && (fp[i] != 0xff)) - break; - } - - /* If we found a valid looking MAC address then use it */ - if (i < 6) - memcpy(&eth_mac[0], fp, 6); -} - -/****************************************************************************/ - -static int ks8695_eth_init(struct eth_device *dev, bd_t *bd) -{ - int i; - - debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__); - - /* Reset the ethernet engines first */ - ks8695_write(KS8695_LAN_DMA_TX, 0x80000000); - ks8695_write(KS8695_LAN_DMA_RX, 0x80000000); - - ks8695_getmac(); - - /* Set MAC address */ - ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) | - (eth_mac[3] << 16) | (eth_mac[2] << 24))); - ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8))); - - /* Turn the 4 port switch on */ - i = ks8695_read(KS8695_SWITCH_CTRL0); - ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1)); - /* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */ - - /* Initialize descriptor rings */ - for (i = 0; (i < TXDESCS); i++) { - ks8695_tx[i].owner = 0; - ks8695_tx[i].ctrl = 0; - ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE]; - ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1]; - } - ks8695_tx[TXDESCS-1].ctrl = 0x02000000; - ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0]; - - for (i = 0; (i < RXDESCS); i++) { - ks8695_rx[i].status = 0x80000000; - ks8695_rx[i].ctrl = BUFSIZE - 4; - ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE]; - ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1]; - } - ks8695_rx[RXDESCS-1].ctrl |= 0x00080000; - ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0]; - - /* The KS8695 is pretty slow reseting the ethernets... */ - udelay(2000000); - - /* Enable the ethernet engine */ - ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]); - ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]); - ks8695_write(KS8695_LAN_DMA_TX, 0x3); - ks8695_write(KS8695_LAN_DMA_RX, 0x71); - ks8695_write(KS8695_LAN_DMA_RX_START, 0x1); - - printf("KS8695 ETHERNET: %pM\n", eth_mac); - return 0; -} - -/****************************************************************************/ - -static void ks8695_eth_halt(struct eth_device *dev) -{ - debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__); - - /* Reset the ethernet engines */ - ks8695_write(KS8695_LAN_DMA_TX, 0x80000000); - ks8695_write(KS8695_LAN_DMA_RX, 0x80000000); -} - -/****************************************************************************/ - -static int ks8695_eth_recv(struct eth_device *dev) -{ - volatile struct ks8695_rxdesc *dp; - int i, len = 0; - - debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__); - - for (i = 0; (i < RXDESCS); i++) { - dp= &ks8695_rx[i]; - if ((dp->status & 0x80000000) == 0) { - len = (dp->status & 0x7ff) - 4; - NetReceive((void *) dp->addr, len); - dp->status = 0x80000000; - ks8695_write(KS8695_LAN_DMA_RX_START, 0x1); - break; - } - } - - return len; -} - -/****************************************************************************/ - -static int ks8695_eth_send(struct eth_device *dev, void *packet, int len) -{ - volatile struct ks8695_txdesc *dp; - static int next = 0; - - debug ("%s(%d): eth_send(packet=%p,len=%d)\n", __FILE__, __LINE__, - packet, len); - - dp = &ks8695_tx[next]; - memcpy((void *) dp->addr, (void *) packet, len); - - if (len < 64) { - memset((void *) (dp->addr + len), 0, 64-len); - len = 64; - } - - dp->ctrl = len | 0xe0000000; - dp->owner = 0x80000000; - - ks8695_write(KS8695_LAN_DMA_TX, 0x3); - ks8695_write(KS8695_LAN_DMA_TX_START, 0x1); - - if (++next >= TXDESCS) - next = 0; - - return 0; -} - -/****************************************************************************/ - -int ks8695_eth_initialize(void) -{ - struct eth_device *dev; - - dev = malloc(sizeof(*dev)); - if (dev == NULL) - return -1; - memset(dev, 0, sizeof(*dev)); - - dev->iobase = KS8695_IO_BASE + KS8695_LAN_DMA_TX; - dev->init = ks8695_eth_init; - dev->halt = ks8695_eth_halt; - dev->send = ks8695_eth_send; - dev->recv = ks8695_eth_recv; - strcpy(dev->name, "ks8695eth"); - - eth_register(dev); - return 0; -} diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 63b0cbf..b385852 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o obj-$(CONFIG_IMX_SERIAL) += serial_imx.o -obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o obj-$(CONFIG_MXC_UART) += serial_mxc.o obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 95c992a..9f78492 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -127,7 +127,6 @@ serial_initfunc(evb64260_serial_initialize); serial_initfunc(imx_serial_initialize); serial_initfunc(iop480_serial_initialize); serial_initfunc(jz_serial_initialize); -serial_initfunc(ks8695_serial_initialize); serial_initfunc(leon2_serial_initialize); serial_initfunc(leon3_serial_initialize); serial_initfunc(lh7a40x_serial_initialize); @@ -220,7 +219,6 @@ void serial_initialize(void) imx_serial_initialize(); iop480_serial_initialize(); jz_serial_initialize(); - ks8695_serial_initialize(); leon2_serial_initialize(); leon3_serial_initialize(); lh7a40x_serial_initialize(); diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c deleted file mode 100644 index 13adabd..0000000 --- a/drivers/serial/serial_ks8695.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * serial.c -- KS8695 serial driver - * - * (C) Copyright 2004, Greg Ungerer greg.ungerer@opengear.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/platform.h> -#include <serial.h> -#include <linux/compiler.h> - -#ifndef CONFIG_SERIAL1 -#error "Bad: you didn't configure serial ..." -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Define the UART hardware register access structure. - */ -struct ks8695uart { - unsigned int RX; /* 0x00 - Receive data (r) */ - unsigned int TX; /* 0x04 - Transmit data (w) */ - unsigned int FCR; /* 0x08 - Fifo Control (r/w) */ - unsigned int LCR; /* 0x0c - Line Control (r/w) */ - unsigned int MCR; /* 0x10 - Modem Control (r/w) */ - unsigned int LSR; /* 0x14 - Line Status (r/w) */ - unsigned int MSR; /* 0x18 - Modem Status (r/w) */ - unsigned int BD; /* 0x1c - Baud Rate (r/w) */ - unsigned int SR; /* 0x20 - Status (r/w) */ -}; - -#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER)) -#define KS8695_UART_CLK 25000000 - - -/* - * Under some circumstances we want to be "quiet" and not issue any - * serial output - though we want u-boot to otherwise work and behave - * the same. By default be noisy. - */ -int serial_console = 1; - - -static void ks8695_serial_setbrg(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - - /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/ - uartp->BD = KS8695_UART_CLK / gd->baudrate; - uartp->LCR = KS8695_UART_LINEC_WLEN8; -} - -static int ks8695_serial_init(void) -{ - serial_console = 1; - serial_setbrg(); - return 0; -} - -static void ks8695_serial_raw_putc(const char c) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - int i; - - for (i = 0; (i < 0x100000); i++) { - if (uartp->LSR & KS8695_UART_LINES_TXFE) - break; - } - - uartp->TX = c; -} - -static void ks8695_serial_putc(const char c) -{ - if (serial_console) { - ks8695_serial_raw_putc(c); - if (c == '\n') - ks8695_serial_raw_putc('\r'); - } -} - -static int ks8695_serial_tstc(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - if (serial_console) - return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0); - return 0; -} - -static int ks8695_serial_getc(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - - while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0) - ; - return (uartp->RX); -} - -static struct serial_device ks8695_serial_drv = { - .name = "ks8695_serial", - .start = ks8695_serial_init, - .stop = NULL, - .setbrg = ks8695_serial_setbrg, - .putc = ks8695_serial_putc, - .puts = default_serial_puts, - .getc = ks8695_serial_getc, - .tstc = ks8695_serial_tstc, -}; - -void ks8695_serial_initialize(void) -{ - serial_register(&ks8695_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &ks8695_serial_drv; -} diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h deleted file mode 100644 index 1cb54b3..0000000 --- a/include/configs/cm4008.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2004 - * Greg Ungerer greg.ungerer@opengear.com. - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_KS8695 1 /* it is a KS8695 CPU */ -#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_KS8695_SERIAL -#define CONFIG_SERIAL1 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_SAVEENV - - -#define CONFIG_BOOTDELAY 0 -#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200" -#define CONFIG_BOOTCOMMAND "gofsk 0x02200000" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */ - -#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h deleted file mode 100644 index adebd4b..0000000 --- a/include/configs/cm41xx.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer greg.ungerer@opengear.com. - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_KS8695 1 /* it is a KS8695 CPU */ -#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_KS8695_SERIAL -#define CONFIG_SERIAL1 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#undef CONFIG_CMD_SAVEENV - - -#define CONFIG_BOOTDELAY 0 -#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200" -#define CONFIG_BOOTCOMMAND "gofsk 0x02200000" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */ - -#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -#endif /* __CONFIG_H */ diff --git a/include/netdev.h b/include/netdev.h index daffc12..90140bd 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -55,7 +55,6 @@ int ftmac100_initialize(bd_t *bits); int ftmac110_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); -int ks8695_eth_initialize(void); int ks8851_mll_initialize(u8 dev_num, int base_addr); int lan91c96_initialize(u8 dev_num, int base_addr); int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); diff --git a/include/serial.h b/include/serial.h index 3d2e569..de40e94 100644 --- a/include/serial.h +++ b/include/serial.h @@ -182,7 +182,6 @@ void evb64260_serial_initialize(void); void imx_serial_initialize(void); void iop480_serial_initialize(void); void jz_serial_initialize(void); -void ks8695_serial_initialize(void); void leon2_serial_initialize(void); void leon3_serial_initialize(void); void lh7a40x_serial_initialize(void);

This is still a non-generic board.

Signed-off-by: Masahiro Yamada yamada.m@jp.panasonic.com Cc: Chan-Taek Park c-park@ti.com Acked-by: Marek Vasut marex@denx.de ---

Changes in v4: None Changes in v3: None Changes in v2: None

arch/arm/Kconfig | 5 - arch/arm/cpu/arm1176/Makefile | 1 - arch/arm/cpu/arm1176/start.S | 22 -- arch/arm/cpu/arm1176/tnetv107x/Makefile | 6 - arch/arm/cpu/arm1176/tnetv107x/aemif.c | 78 ----- arch/arm/cpu/arm1176/tnetv107x/clock.c | 432 ------------------------- arch/arm/cpu/arm1176/tnetv107x/init.c | 22 -- arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 10 - arch/arm/cpu/arm1176/tnetv107x/mux.c | 319 ------------------ arch/arm/cpu/arm1176/tnetv107x/timer.c | 93 ------ arch/arm/include/asm/arch-tnetv107x/clock.h | 53 --- arch/arm/include/asm/arch-tnetv107x/hardware.h | 160 --------- arch/arm/include/asm/arch-tnetv107x/mux.h | 291 ----------------- board/ti/tnetv107xevm/Kconfig | 15 - board/ti/tnetv107xevm/MAINTAINERS | 6 - board/ti/tnetv107xevm/Makefile | 5 - board/ti/tnetv107xevm/config.mk | 5 - board/ti/tnetv107xevm/sdb_board.c | 134 -------- configs/tnetv107x_evm_defconfig | 2 - doc/README.scrapyard | 1 + drivers/watchdog/Makefile | 1 - drivers/watchdog/tnetv107x_wdt.c | 165 ---------- include/configs/tnetv107x_evm.h | 139 -------- 23 files changed, 1 insertion(+), 1964 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/Makefile delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/aemif.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/clock.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/init.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/mux.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/timer.c delete mode 100644 arch/arm/include/asm/arch-tnetv107x/clock.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/hardware.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/mux.h delete mode 100644 board/ti/tnetv107xevm/Kconfig delete mode 100644 board/ti/tnetv107xevm/MAINTAINERS delete mode 100644 board/ti/tnetv107xevm/Makefile delete mode 100644 board/ti/tnetv107xevm/config.mk delete mode 100644 board/ti/tnetv107xevm/sdb_board.c delete mode 100644 configs/tnetv107x_evm_defconfig delete mode 100644 drivers/watchdog/tnetv107x_wdt.c delete mode 100644 include/configs/tnetv107x_evm.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d5a9d15..b9284a3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -282,10 +282,6 @@ config TARGET_RPI_2 bool "Support rpi_2" select CPU_V7

-config TARGET_TNETV107X_EVM - bool "Support tnetv107x_evm" - select CPU_ARM1176 - config TARGET_INTEGRATORAP_CM946ES bool "Support integratorap_cm946es" select CPU_ARM946ES @@ -820,7 +816,6 @@ source "board/ti/am335x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/ti/ti814x/Kconfig" source "board/ti/ti816x/Kconfig" -source "board/ti/tnetv107xevm/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/tqc/tqma6/Kconfig" diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile index ead2303..480e130 100644 --- a/arch/arm/cpu/arm1176/Makefile +++ b/arch/arm/cpu/arm1176/Makefile @@ -12,4 +12,3 @@ extra-y = start.o obj-y = cpu.o

obj-$(CONFIG_BCM2835) += bcm2835/ -obj-$(CONFIG_TNETV107X) += tnetv107x/ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 0704bdd..ac937bf 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -96,28 +96,6 @@ mmu_disable: mov pc, r2 mmu_disable_phys:

-#ifdef CONFIG_DISABLE_TCM - /* - * Disable the TCMs - */ - mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ - cmp r0, #0 - beq skip_tcmdisable - mov r1, #0 - mov r2, #1 - tst r0, r2 - mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ - tst r0, r2, LSL #16 - mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ -skip_tcmdisable: -#endif -#endif - -#ifdef CONFIG_PERIPORT_REMAP - /* Peri port setup */ - ldr r0, =CONFIG_PERIPORT_BASE - orr r0, r0, #CONFIG_PERIPORT_SIZE - mcr p15,0,r0,c15,c2,4 #endif

/* diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile deleted file mode 100644 index a4c1edf..0000000 --- a/arch/arm/cpu/arm1176/tnetv107x/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += aemif.o clock.o init.o mux.o timer.o -obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/arch/arm/cpu/arm1176/tnetv107x/aemif.c deleted file mode 100644 index a0f5728..0000000 --- a/arch/arm/cpu/arm1176/tnetv107x/aemif.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * TNETV107X: Asynchronous EMIF Configuration - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/mux.h> - -#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE -#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4) -#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c) -#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60) -#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4) - -#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) -#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) -#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26) -#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20) -#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17) -#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13) -#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7) -#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4) -#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2) -#define CONFIG_WIDTH(v) (((v) & 0x03) << 0) - -#define NUM_CS 4 - -#define set_config_field(reg, field, val) \ - do { \ - if (val != -1) { \ - reg &= ~CONFIG_##field(0xffffffff); \ - reg |= CONFIG_##field(val); \ - } \ - } while (0) - -void configure_async_emif(int cs, struct async_emif_config *cfg) -{ - unsigned long tmp; - - if (cfg->mode == ASYNC_EMIF_MODE_NAND) { - tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL); - tmp |= (1 << cs); - __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL); - - } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) { - tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL); - tmp |= (1 << cs); - __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL); - } - - tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs)); - - set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); - set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); - set_config_field(tmp, WR_SETUP, cfg->wr_setup); - set_config_field(tmp, WR_STROBE, cfg->wr_strobe); - set_config_field(tmp, WR_HOLD, cfg->wr_hold); - set_config_field(tmp, RD_SETUP, cfg->rd_setup); - set_config_field(tmp, RD_STROBE, cfg->rd_strobe); - set_config_field(tmp, RD_HOLD, cfg->rd_hold); - set_config_field(tmp, TURN_AROUND, cfg->turn_around); - set_config_field(tmp, WIDTH, cfg->width); - - __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs)); -} - -void init_async_emif(int num_cs, struct async_emif_config *config) -{ - int cs; - - clk_enable(TNETV107X_LPSC_AEMIF); - - for (cs = 0; cs < num_cs; cs++) - configure_async_emif(cs, config + cs); -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c deleted file mode 100644 index 7ba28d3..0000000 --- a/arch/arm/cpu/arm1176/tnetv107x/clock.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * TNETV107X: Clock management APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm-generic/errno.h> -#include <asm/io.h> -#include <asm/processor.h> -#include <asm/arch/clock.h> - -#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE -#define PSC_BASE TNETV107X_PSC_BASE - -#define BIT(x) (1 << (x)) - -#define MAX_PREDIV 64 -#define MAX_POSTDIV 8UL -#define MAX_MULT 512 -#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV) - -/* LPSC registers */ -#define PSC_PTCMD 0x120 -#define PSC_PTSTAT 0x128 -#define PSC_MDSTAT(n) (0x800 + (n) * 4) -#define PSC_MDCTL(n) (0xA00 + (n) * 4) - -#define PSC_MDCTL_LRSTZ BIT(8) - -#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg))) -#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg))) - -/* SSPLL registers */ -struct sspll_regs { - u32 modes; - u32 postdiv; - u32 prediv; - u32 mult_factor; - u32 divider_range; - u32 bw_divider; - u32 spr_amount; - u32 spr_rate_div; - u32 diag; -}; - -/* SSPLL base addresses */ -static struct sspll_regs *sspll_regs[] = { - (struct sspll_regs *)(CLOCK_BASE + 0x040), - (struct sspll_regs *)(CLOCK_BASE + 0x080), - (struct sspll_regs *)(CLOCK_BASE + 0x0c0), -}; - -#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg)) -#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg)) -#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg)) - - -/* PLL Control Registers */ -struct pllctl_regs { - u32 ctl; /* 00 */ - u32 ocsel; /* 04 */ - u32 secctl; /* 08 */ - u32 __pad0; - u32 mult; /* 10 */ - u32 prediv; /* 14 */ - u32 div1; /* 18 */ - u32 div2; /* 1c */ - u32 div3; /* 20 */ - u32 oscdiv1; /* 24 */ - u32 postdiv; /* 28 */ - u32 bpdiv; /* 2c */ - u32 wakeup; /* 30 */ - u32 __pad1; - u32 cmd; /* 38 */ - u32 stat; /* 3c */ - u32 alnctl; /* 40 */ - u32 dchange; /* 44 */ - u32 cken; /* 48 */ - u32 ckstat; /* 4c */ - u32 systat; /* 50 */ - u32 ckctl; /* 54 */ - u32 __pad2[2]; - u32 div4; /* 60 */ - u32 div5; /* 64 */ - u32 div6; /* 68 */ - u32 div7; /* 6c */ - u32 div8; /* 70 */ -}; - -struct lpsc_map { - int pll, div; -}; - -static struct pllctl_regs *pllctl_regs[] = { - (struct pllctl_regs *)(CLOCK_BASE + 0x700), - (struct pllctl_regs *)(CLOCK_BASE + 0x300), - (struct pllctl_regs *)(CLOCK_BASE + 0x500), -}; - -#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) -#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) -#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) - -#define pllctl_reg_rmw(pll, reg, mask, val) \ - pllctl_reg_write(pll, reg, \ - (pllctl_reg_read(pll, reg) & ~(mask)) | val) - -#define pllctl_reg_setbits(pll, reg, mask) \ - pllctl_reg_rmw(pll, reg, 0, mask) - -#define pllctl_reg_clrbits(pll, reg, mask) \ - pllctl_reg_rmw(pll, reg, mask, 0) - -/* PLLCTL Bits */ -#define PLLCTL_CLKMODE BIT(8) -#define PLLCTL_PLLSELB BIT(7) -#define PLLCTL_PLLENSRC BIT(5) -#define PLLCTL_PLLDIS BIT(4) -#define PLLCTL_PLLRST BIT(3) -#define PLLCTL_PLLPWRDN BIT(1) -#define PLLCTL_PLLEN BIT(0) - -#define PLLDIV_ENABLE BIT(15) - -static int pll_div_offset[] = { -#define div_offset(reg) offsetof(struct pllctl_regs, reg) - div_offset(div1), div_offset(div2), div_offset(div3), - div_offset(div4), div_offset(div5), div_offset(div6), - div_offset(div7), div_offset(div8), -}; - -static unsigned long pll_bypass_mask[] = { 1, 4, 2 }; -static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff }; - -/* Mappings from PLL+DIV to subsystem clocks */ -#define sys_arm1176_clk {SYS_PLL, 0} -#define sys_dsp_clk {SYS_PLL, 1} -#define sys_ddr_clk {SYS_PLL, 2} -#define sys_full_clk {SYS_PLL, 3} -#define sys_lcd_clk {SYS_PLL, 4} -#define sys_vlynq_ref_clk {SYS_PLL, 5} -#define sys_tsc_clk {SYS_PLL, 6} -#define sys_half_clk {SYS_PLL, 7} - -#define eth_clk_5 {ETH_PLL, 0} -#define eth_clk_50 {ETH_PLL, 1} -#define eth_clk_125 {ETH_PLL, 2} -#define eth_clk_250 {ETH_PLL, 3} -#define eth_clk_25 {ETH_PLL, 4} - -#define tdm_clk {TDM_PLL, 0} -#define tdm_extra_clk {TDM_PLL, 1} -#define tdm1_clk {TDM_PLL, 2} - -static const struct lpsc_map lpsc_clk_map[] = { - [TNETV107X_LPSC_ARM] = sys_arm1176_clk, - [TNETV107X_LPSC_GEM] = sys_dsp_clk, - [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk, - [TNETV107X_LPSC_TPCC] = sys_full_clk, - [TNETV107X_LPSC_TPTC0] = sys_full_clk, - [TNETV107X_LPSC_TPTC1] = sys_full_clk, - [TNETV107X_LPSC_RAM] = sys_full_clk, - [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk, - [TNETV107X_LPSC_LCD] = sys_lcd_clk, - [TNETV107X_LPSC_ETHSS] = eth_clk_125, - [TNETV107X_LPSC_AEMIF] = sys_full_clk, - [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk, - [TNETV107X_LPSC_TSC] = sys_tsc_clk, - [TNETV107X_LPSC_ROM] = sys_half_clk, - [TNETV107X_LPSC_UART2] = sys_half_clk, - [TNETV107X_LPSC_PKTSEC] = sys_half_clk, - [TNETV107X_LPSC_SECCTL] = sys_half_clk, - [TNETV107X_LPSC_KEYMGR] = sys_half_clk, - [TNETV107X_LPSC_KEYPAD] = sys_half_clk, - [TNETV107X_LPSC_GPIO] = sys_half_clk, - [TNETV107X_LPSC_MDIO] = sys_half_clk, - [TNETV107X_LPSC_SDIO0] = sys_half_clk, - [TNETV107X_LPSC_UART0] = sys_half_clk, - [TNETV107X_LPSC_UART1] = sys_half_clk, - [TNETV107X_LPSC_TIMER0] = sys_half_clk, - [TNETV107X_LPSC_TIMER1] = sys_half_clk, - [TNETV107X_LPSC_WDT_ARM] = sys_half_clk, - [TNETV107X_LPSC_WDT_DSP] = sys_half_clk, - [TNETV107X_LPSC_SSP] = sys_half_clk, - [TNETV107X_LPSC_TDM0] = tdm_clk, - [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk, - [TNETV107X_LPSC_MCDMA] = sys_half_clk, - [TNETV107X_LPSC_USB0] = sys_half_clk, - [TNETV107X_LPSC_TDM1] = tdm1_clk, - [TNETV107X_LPSC_DEBUGSS] = sys_half_clk, - [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250, - [TNETV107X_LPSC_SYSTEM] = sys_half_clk, - [TNETV107X_LPSC_IMCOP] = sys_dsp_clk, - [TNETV107X_LPSC_SPARE] = sys_half_clk, - [TNETV107X_LPSC_SDIO1] = sys_half_clk, - [TNETV107X_LPSC_USB1] = sys_half_clk, - [TNETV107X_LPSC_USBSS] = sys_half_clk, - [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk, - [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk, -}; - -static const unsigned long pll_ext_freq[] = { - [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ, - [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ, - [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ, -}; - -static unsigned long pll_freq_get(int pll) -{ - unsigned long mult = 1, prediv = 1, postdiv = 1; - unsigned long ref = CONFIG_SYS_INT_OSC_FREQ; - unsigned long ret; - u32 bypass; - - bypass = __raw_readl((u32 *)(CLOCK_BASE)); - if (!(bypass & pll_bypass_mask[pll])) { - mult = sspll_reg_read(pll, mult_factor); - prediv = sspll_reg_read(pll, prediv) + 1; - postdiv = sspll_reg_read(pll, postdiv) + 1; - } - - if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE) - ref = pll_ext_freq[pll]; - - if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN)) - return ref; - - ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256); - ret /= (prediv * postdiv); - - return ret; -} - -static unsigned long __pll_div_freq_get(int pll, unsigned int fpll, - int div) -{ - int divider = 1; - unsigned long divreg; - - divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]); - - if (divreg & PLLDIV_ENABLE) - divider = (divreg & pll_div_mask[pll]) + 1; - - return fpll / divider; -} - -static unsigned long pll_div_freq_get(int pll, int div) -{ - unsigned int fpll = pll_freq_get(pll); - - return __pll_div_freq_get(pll, fpll, div); -} - -static void __pll_div_freq_set(int pll, unsigned int fpll, int div, - unsigned long hz) -{ - int divider = (fpll / hz - 1); - - divider &= pll_div_mask[pll]; - divider |= PLLDIV_ENABLE; - - __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]); - pllctl_reg_setbits(pll, alnctl, (1 << div)); - pllctl_reg_setbits(pll, dchange, (1 << div)); -} - -static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz) -{ - unsigned int fpll = pll_freq_get(pll); - - __pll_div_freq_set(pll, fpll, div, hz); - - pllctl_reg_write(pll, cmd, 1); - - /* Wait until new divider takes effect */ - while (pllctl_reg_read(pll, stat) & 0x01); - - return __pll_div_freq_get(pll, fpll, div); -} - -unsigned long clk_get_rate(unsigned int clk) -{ - return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div); -} - -unsigned long clk_round_rate(unsigned int clk, unsigned long hz) -{ - unsigned long fpll, divider, pll; - - pll = lpsc_clk_map[clk].pll; - fpll = pll_freq_get(pll); - divider = (fpll / hz - 1); - divider &= pll_div_mask[pll]; - - return fpll / (divider + 1); -} - -int clk_set_rate(unsigned int clk, unsigned long _hz) -{ - unsigned long hz; - - hz = clk_round_rate(clk, _hz); - if (hz != _hz) - return -EINVAL; /* Cannot set to target freq */ - - pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz); - return 0; -} - -void lpsc_control(int mod, unsigned long state, int lrstz) -{ - u32 mdctl; - - mdctl = psc_reg_read(PSC_MDCTL(mod)); - mdctl &= ~0x1f; - mdctl |= state; - - if (lrstz == 0) - mdctl &= ~PSC_MDCTL_LRSTZ; - else if (lrstz == 1) - mdctl |= PSC_MDCTL_LRSTZ; - - psc_reg_write(PSC_MDCTL(mod), mdctl); - - psc_reg_write(PSC_PTCMD, 1); - - /* wait for power domain transition to end */ - while (psc_reg_read(PSC_PTSTAT) & 1); - - /* Wait for module state change */ - while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state); -} - -int lpsc_status(unsigned int id) -{ - return psc_reg_read(PSC_MDSTAT(id)) & 0x1f; -} - -static void init_pll(const struct pll_init_data *data) -{ - unsigned long fpll; - unsigned long best_pre = 0, best_post = 0, best_mult = 0; - unsigned long div, prediv, postdiv, mult; - unsigned long delta, actual; - long best_delta = -1; - int i; - u32 tmp; - - if (data->pll == SYS_PLL) - return; /* cannot reconfigure system pll on the fly */ - - tmp = pllctl_reg_read(data->pll, ctl); - if (data->internal_osc) { - tmp &= ~PLLCTL_CLKMODE; - fpll = CONFIG_SYS_INT_OSC_FREQ; - } else { - tmp |= PLLCTL_CLKMODE; - fpll = pll_ext_freq[data->pll]; - } - pllctl_reg_write(data->pll, ctl, tmp); - - mult = data->pll_freq / fpll; - for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) { - div = (fpll * mult) / data->pll_freq; - if (div < 1 || div > MAX_DIV) - continue; - - for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) { - prediv = div / postdiv; - if (prediv < 1 || prediv > MAX_PREDIV) - continue; - - actual = (fpll / prediv) * (mult / postdiv); - delta = (actual - data->pll_freq); - if (delta < 0) - delta = -delta; - if ((delta < best_delta) || (best_delta == -1)) { - best_delta = delta; - best_mult = mult; - best_pre = prediv; - best_post = postdiv; - if (delta == 0) - goto done; - } - } - } -done: - - if (best_delta == -1) { - printf("pll cannot derive %lu from %lu\n", - data->pll_freq, fpll); - return; - } - - fpll = fpll * best_mult; - fpll /= best_pre * best_post; - - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC); - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN); - - pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST); - - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN); - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS); - - sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8); - sspll_reg_write(data->pll, prediv, best_pre - 1); - sspll_reg_write(data->pll, postdiv, best_post - 1); - - for (i = 0; i < 10; i++) - if (data->div_freq[i]) - __pll_div_freq_set(data->pll, fpll, i, - data->div_freq[i]); - - pllctl_reg_write(data->pll, cmd, 1); - - /* Wait until pll "go" operation completes */ - while (pllctl_reg_read(data->pll, stat) & 0x01); - - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST); - pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); -} - -void init_plls(int num_pll, struct pll_init_data *config) -{ - int i; - - for (i = 0; i < num_pll; i++) - init_pll(&config[i]); -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/init.c b/arch/arm/cpu/arm1176/tnetv107x/init.c deleted file mode 100644 index d870826..0000000 --- a/arch/arm/cpu/arm1176/tnetv107x/init.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * TNETV107X: Architecture initialization - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> - -void chip_configuration_unlock(void) -{ - __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0); - __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1); -} - -int arch_cpu_init(void) -{ - icache_enable(); - chip_configuration_unlock(); - - return 0; -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S deleted file mode 100644 index a8bce47..0000000 --- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * TNETV107X: Low-level pre-relocation initialization - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.globl lowlevel_init -lowlevel_init: - /* nothing for now, maybe needed for more exotic boot modes */ - mov pc, lr diff --git a/arch/arm/cpu/arm1176/tnetv107x/mux.c b/arch/arm/cpu/arm1176/tnetv107x/mux.c deleted file mode 100644 index 310d84d..0000000 --- a/arch/arm/cpu/arm1176/tnetv107x/mux.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * TNETV107X: Pinmux configuration - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/mux.h> - -#define MUX_MODE_1 0x00 -#define MUX_MODE_2 0x04 -#define MUX_MODE_3 0x0c -#define MUX_MODE_4 0x1c - -#define MUX_DEBUG 0 - -static const struct pin_config pin_table[] = { - /* reg shift mode */ - TNETV107X_MUX_CFG(0, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(4, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(4, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(4, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(4, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 20, MUX_MODE_3), - TNETV107X_MUX_CFG(4, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(7, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(7, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(8, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(8, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(8, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(8, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(8, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(8, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(8, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(10, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(11, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(11, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(15, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(15, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(16, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(16, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(17, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(17, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(17, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(19, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(20, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(22, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 20, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 25, MUX_MODE_3), - TNETV107X_MUX_CFG(23, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(23, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(23, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(23, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(23, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(23, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(24, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(24, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(24, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(26, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(26, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(26, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(26, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 25, MUX_MODE_2), -}; - -const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]); - -int mux_select_pin(short index) -{ - const struct pin_config *cfg; - unsigned long mask, mode, reg; - - if (index >= pin_table_size) - return 0; - - cfg = &pin_table[index]; - - mask = 0x1f << cfg->mask_offset; - mode = cfg->mode << cfg->mask_offset; - - reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index)); - reg = (reg & ~mask) | mode; - __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index)); - - return 1; -} - -int mux_select_pins(const short *pins) -{ - int i, ret = 1; - - for (i = 0; pins[i] >= 0; i++) - ret &= mux_select_pin(pins[i]); - - return ret; -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c deleted file mode 100644 index 6e0dd0d..0000000 --- a/arch/arm/cpu/arm1176/tnetv107x/timer.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * TNETV107X: Timer implementation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> - -struct timer_regs { - u_int32_t pid12; - u_int32_t pad[3]; - u_int32_t tim12; - u_int32_t tim34; - u_int32_t prd12; - u_int32_t prd34; - u_int32_t tcr; - u_int32_t tgcr; - u_int32_t wdtcr; -}; - -#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE) - -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) -#define TIM_CLK_DIV 16 - -static ulong timestamp; -static ulong lastinc; - -int timer_init(void) -{ - clk_enable(TNETV107X_LPSC_TIMER0); - - lastinc = timestamp = 0; - - /* We are using timer34 in unchained 32-bit mode, full speed */ - __raw_writel(0x0, &regs->tcr); - __raw_writel(0x0, &regs->tgcr); - __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &regs->tgcr); - __raw_writel(0x0, &regs->tim34); - __raw_writel(TIMER_LOAD_VAL, &regs->prd34); - __raw_writel(2 << 22, &regs->tcr); - - return 0; -} - -static ulong get_timer_raw(void) -{ - ulong now = __raw_readl(&regs->tim34); - - if (now >= lastinc) - timestamp += now - lastinc; - else - timestamp += now + TIMER_LOAD_VAL - lastinc; - - lastinc = now; - - return timestamp; -} - -ulong get_timer(ulong base) -{ - return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base; -} - -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -void __udelay(unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - tmo = CONFIG_SYS_HZ_CLOCK / 1000; - tmo *= usec; - tmo /= (1000 * TIM_CLK_DIV); - - endtime = get_timer_raw() + tmo; - - do { - ulong now = get_timer_raw(); - diff = endtime - now; - } while (diff >= 0); -} - -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h deleted file mode 100644 index dfc3b1b..0000000 --- a/arch/arm/include/asm/arch-tnetv107x/clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * TNETV107X: Clock APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0 -#define PSC_MDCTL_NEXT_SYNCRST 0x1 -#define PSC_MDCTL_NEXT_DISABLE 0x2 -#define PSC_MDCTL_NEXT_ENABLE 0x3 - -#define CONFIG_SYS_INT_OSC_FREQ 24000000 - -#ifndef __ASSEMBLY__ - -/* PLL identifiers */ -enum pll_type_e { - SYS_PLL, - TDM_PLL, - ETH_PLL -}; - -/* PLL configuration data */ -struct pll_init_data { - int pll; - int internal_osc; - unsigned long pll_freq; - unsigned long div_freq[10]; -}; - -void init_plls(int num_pll, struct pll_init_data *config); -int lpsc_status(unsigned int mod); -void lpsc_control(int mod, unsigned long state, int lrstz); -unsigned long clk_get_rate(unsigned int clk); -unsigned long clk_round_rate(unsigned int clk, unsigned long hz); -int clk_set_rate(unsigned int clk, unsigned long hz); - -static inline void clk_enable(unsigned int mod) -{ - lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1); -} - -static inline void clk_disable(unsigned int mod) -{ - lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1); -} - -#endif - -#endif diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h deleted file mode 100644 index d458e0b..0000000 --- a/arch/arm/include/asm/arch-tnetv107x/hardware.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * TNETV107X: Hardware information - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#ifndef __ASSEMBLY__ - -#include <linux/sizes.h> - -#define ASYNC_EMIF_NUM_CS 4 -#define ASYNC_EMIF_MODE_NOR 0 -#define ASYNC_EMIF_MODE_NAND 1 -#define ASYNC_EMIF_MODE_ONENAND 2 -#define ASYNC_EMIF_PRESERVE -1 - -struct async_emif_config { - unsigned mode; - unsigned select_strobe; - unsigned extend_wait; - unsigned wr_setup; - unsigned wr_strobe; - unsigned wr_hold; - unsigned rd_setup; - unsigned rd_strobe; - unsigned rd_hold; - unsigned turn_around; - enum { - ASYNC_EMIF_8 = 0, - ASYNC_EMIF_16 = 1, - ASYNC_EMIF_32 = 2, - } width; -}; - -void init_async_emif(int num_cs, struct async_emif_config *config); - -int wdt_start(unsigned long msecs); -int wdt_stop(void); -int wdt_kick(void); - -#endif - -/* Chip configuration unlock codes and registers */ -#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38) -#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c) -#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4) -#define TNETV107X_KICK0_MAGIC 0x83e70b13 -#define TNETV107X_KICK1_MAGIC 0x95a4f1e0 - -/* Module base addresses */ -#define TNETV107X_TPCC_BASE 0x01C00000 -#define TNETV107X_TPTC0_BASE 0x01C10000 -#define TNETV107X_TPTC1_BASE 0x01C10400 -#define TNETV107X_INTC_BASE 0x03000000 -#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000 -#define TNETV107X_INTD_BASE 0x08038000 -#define TNETV107X_INTD_IPC_BASE 0x08038000 -#define TNETV107X_INTD_FAST_BASE 0x08039000 -#define TNETV107X_INTD_ASYNC_BASE 0x0803A000 -#define TNETV107X_INTD_SLOW_BASE 0x0803B000 -#define TNETV107X_PKA_BASE 0x08040000 -#define TNETV107X_RNG_BASE 0x08044000 -#define TNETV107X_TIMER0_BASE 0x08086500 -#define TNETV107X_TIMER1_BASE 0x08086600 -#define TNETV107X_WDT0_ARM_BASE 0x08086700 -#define TNETV107X_WDT1_DSP_BASE 0x08086800 -#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000 -#define TNETV107X_GPIO_BASE 0x08088000 -#define TNETV107X_UART1_BASE 0x08088400 -#define TNETV107X_TOUCHSCREEN_BASE 0x08088500 -#define TNETV107X_SDIO0_BASE 0x08088700 -#define TNETV107X_SDIO1_BASE 0x08088800 -#define TNETV107X_MDIO_BASE 0x08088900 -#define TNETV107X_KEYPAD_BASE 0x08088A00 -#define TNETV107X_SSP_BASE 0x08088C00 -#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000 -#define TNETV107X_PSC_BASE 0x0808B000 -#define TNETV107X_TDM0_BASE 0x08100000 -#define TNETV107X_TDM1_BASE 0x08100100 -#define TNETV107X_MCDMA_BASE 0x08108000 -#define TNETV107X_UART0_DMA_BASE 0x08108200 -#define TNETV107X_USBSS_BASE 0x08120000 -#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000 -#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 -#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000 -#define TNETV107X_IMCOP_BASE 0x01CC0000 -#define TNETV107X_MBX_LITE_BASE 0x07000000 -#define TNETV107X_ETHSS_BASE 0x0803C000 -#define TNETV107X_CPSW_BASE 0x0803C000 -#define TNETV107X_SPF_BASE 0x0803C800 -#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000 -#define TNETV107X_VTP_CNTRL_0 0x0803D800 -#define TNETV107X_VTP_CNTRL_1 0x0803D900 -#define TNETV107X_UART2_DMA_BASE 0x08108400 -#define TNETV107X_INTERNAL_MEMORY 0x20000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 -#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000 -#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000 - -/* LPSC module definitions */ -#define TNETV107X_LPSC_ARM 0 -#define TNETV107X_LPSC_GEM 1 -#define TNETV107X_LPSC_DDR2_PHY 2 -#define TNETV107X_LPSC_TPCC 3 -#define TNETV107X_LPSC_TPTC0 4 -#define TNETV107X_LPSC_TPTC1 5 -#define TNETV107X_LPSC_RAM 6 -#define TNETV107X_LPSC_MBX_LITE 7 -#define TNETV107X_LPSC_LCD 8 -#define TNETV107X_LPSC_ETHSS 9 -#define TNETV107X_LPSC_AEMIF 10 -#define TNETV107X_LPSC_CHIP_CFG 11 -#define TNETV107X_LPSC_TSC 12 -#define TNETV107X_LPSC_ROM 13 -#define TNETV107X_LPSC_UART2 14 -#define TNETV107X_LPSC_PKTSEC 15 -#define TNETV107X_LPSC_SECCTL 16 -#define TNETV107X_LPSC_KEYMGR 17 -#define TNETV107X_LPSC_KEYPAD 18 -#define TNETV107X_LPSC_GPIO 19 -#define TNETV107X_LPSC_MDIO 20 -#define TNETV107X_LPSC_SDIO0 21 -#define TNETV107X_LPSC_UART0 22 -#define TNETV107X_LPSC_UART1 23 -#define TNETV107X_LPSC_TIMER0 24 -#define TNETV107X_LPSC_TIMER1 25 -#define TNETV107X_LPSC_WDT_ARM 26 -#define TNETV107X_LPSC_WDT_DSP 27 -#define TNETV107X_LPSC_SSP 28 -#define TNETV107X_LPSC_TDM0 29 -#define TNETV107X_LPSC_VLYNQ 30 -#define TNETV107X_LPSC_MCDMA 31 -#define TNETV107X_LPSC_USB0 32 -#define TNETV107X_LPSC_TDM1 33 -#define TNETV107X_LPSC_DEBUGSS 34 -#define TNETV107X_LPSC_ETHSS_RGMII 35 -#define TNETV107X_LPSC_SYSTEM 36 -#define TNETV107X_LPSC_IMCOP 37 -#define TNETV107X_LPSC_SPARE 38 -#define TNETV107X_LPSC_SDIO1 39 -#define TNETV107X_LPSC_USB1 40 -#define TNETV107X_LPSC_USBSS 41 -#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42 -#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43 -#define TNETV107X_LPSC_MAX 44 - -/* Interrupt controller */ -#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10) -#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500) -#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380) - -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h deleted file mode 100644 index 3f832c4..0000000 --- a/arch/arm/include/asm/arch-tnetv107x/mux.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * TNETV107X: Pinmux APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MUX_H -#define __ASM_ARCH_MUX_H - -struct pin_config { - unsigned char reg_index; - unsigned char mask_offset; - unsigned char mode; -}; - -#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \ - { reg, offset, mux_mode } - -int mux_select_pin(short index); -int mux_select_pins(const short *pins); - -enum tnetv107x_pin_mux_index { - TNETV107X_PIN_ASR_A00, - TNETV107X_PIN_GPIO32, - TNETV107X_PIN_ASR_A01, - TNETV107X_PIN_GPIO33, - TNETV107X_PIN_ASR_A02, - TNETV107X_PIN_GPIO34, - TNETV107X_PIN_ASR_A03, - TNETV107X_PIN_GPIO35, - TNETV107X_PIN_ASR_A04, - TNETV107X_PIN_GPIO36, - TNETV107X_PIN_ASR_A05, - TNETV107X_PIN_GPIO37, - TNETV107X_PIN_ASR_A06, - TNETV107X_PIN_GPIO38, - TNETV107X_PIN_ASR_A07, - TNETV107X_PIN_GPIO39, - TNETV107X_PIN_ASR_A08, - TNETV107X_PIN_GPIO40, - TNETV107X_PIN_ASR_A09, - TNETV107X_PIN_GPIO41, - TNETV107X_PIN_ASR_A10, - TNETV107X_PIN_GPIO42, - TNETV107X_PIN_ASR_A11, - TNETV107X_PIN_BOOT_STRP_0, - TNETV107X_PIN_ASR_A12, - TNETV107X_PIN_BOOT_STRP_1, - TNETV107X_PIN_ASR_A13, - TNETV107X_PIN_GPIO43, - TNETV107X_PIN_ASR_A14, - TNETV107X_PIN_GPIO44, - TNETV107X_PIN_ASR_A15, - TNETV107X_PIN_GPIO45, - TNETV107X_PIN_ASR_A16, - TNETV107X_PIN_GPIO46, - TNETV107X_PIN_ASR_A17, - TNETV107X_PIN_GPIO47, - TNETV107X_PIN_ASR_A18, - TNETV107X_PIN_GPIO48, - TNETV107X_PIN_SDIO1_DATA3_0, - TNETV107X_PIN_ASR_A19, - TNETV107X_PIN_GPIO49, - TNETV107X_PIN_SDIO1_DATA2_0, - TNETV107X_PIN_ASR_A20, - TNETV107X_PIN_GPIO50, - TNETV107X_PIN_SDIO1_DATA1_0, - TNETV107X_PIN_ASR_A21, - TNETV107X_PIN_GPIO51, - TNETV107X_PIN_SDIO1_DATA0_0, - TNETV107X_PIN_ASR_A22, - TNETV107X_PIN_GPIO52, - TNETV107X_PIN_SDIO1_CMD_0, - TNETV107X_PIN_ASR_A23, - TNETV107X_PIN_GPIO53, - TNETV107X_PIN_SDIO1_CLK_0, - TNETV107X_PIN_ASR_BA_1, - TNETV107X_PIN_GPIO54, - TNETV107X_PIN_SYS_PLL_CLK, - TNETV107X_PIN_ASR_CS0, - TNETV107X_PIN_ASR_CS1, - TNETV107X_PIN_ASR_CS2, - TNETV107X_PIN_TDM_PLL_CLK, - TNETV107X_PIN_ASR_CS3, - TNETV107X_PIN_ETH_PHY_CLK, - TNETV107X_PIN_ASR_D00, - TNETV107X_PIN_GPIO55, - TNETV107X_PIN_ASR_D01, - TNETV107X_PIN_GPIO56, - TNETV107X_PIN_ASR_D02, - TNETV107X_PIN_GPIO57, - TNETV107X_PIN_ASR_D03, - TNETV107X_PIN_GPIO58, - TNETV107X_PIN_ASR_D04, - TNETV107X_PIN_GPIO59_0, - TNETV107X_PIN_ASR_D05, - TNETV107X_PIN_GPIO60_0, - TNETV107X_PIN_ASR_D06, - TNETV107X_PIN_GPIO61_0, - TNETV107X_PIN_ASR_D07, - TNETV107X_PIN_GPIO62_0, - TNETV107X_PIN_ASR_D08, - TNETV107X_PIN_GPIO63_0, - TNETV107X_PIN_ASR_D09, - TNETV107X_PIN_GPIO64_0, - TNETV107X_PIN_ASR_D10, - TNETV107X_PIN_SDIO1_DATA3_1, - TNETV107X_PIN_ASR_D11, - TNETV107X_PIN_SDIO1_DATA2_1, - TNETV107X_PIN_ASR_D12, - TNETV107X_PIN_SDIO1_DATA1_1, - TNETV107X_PIN_ASR_D13, - TNETV107X_PIN_SDIO1_DATA0_1, - TNETV107X_PIN_ASR_D14, - TNETV107X_PIN_SDIO1_CMD_1, - TNETV107X_PIN_ASR_D15, - TNETV107X_PIN_SDIO1_CLK_1, - TNETV107X_PIN_ASR_OE, - TNETV107X_PIN_BOOT_STRP_2, - TNETV107X_PIN_ASR_RNW, - TNETV107X_PIN_GPIO29_0, - TNETV107X_PIN_ASR_WAIT, - TNETV107X_PIN_GPIO30_0, - TNETV107X_PIN_ASR_WE, - TNETV107X_PIN_BOOT_STRP_3, - TNETV107X_PIN_ASR_WE_DQM0, - TNETV107X_PIN_GPIO31, - TNETV107X_PIN_LCD_PD17_0, - TNETV107X_PIN_ASR_WE_DQM1, - TNETV107X_PIN_ASR_BA0_0, - TNETV107X_PIN_VLYNQ_CLK, - TNETV107X_PIN_GPIO14, - TNETV107X_PIN_LCD_PD19_0, - TNETV107X_PIN_VLYNQ_RXD0, - TNETV107X_PIN_GPIO15, - TNETV107X_PIN_LCD_PD20_0, - TNETV107X_PIN_VLYNQ_RXD1, - TNETV107X_PIN_GPIO16, - TNETV107X_PIN_LCD_PD21_0, - TNETV107X_PIN_VLYNQ_TXD0, - TNETV107X_PIN_GPIO17, - TNETV107X_PIN_LCD_PD22_0, - TNETV107X_PIN_VLYNQ_TXD1, - TNETV107X_PIN_GPIO18, - TNETV107X_PIN_LCD_PD23_0, - TNETV107X_PIN_SDIO0_CLK, - TNETV107X_PIN_GPIO19, - TNETV107X_PIN_SDIO0_CMD, - TNETV107X_PIN_GPIO20, - TNETV107X_PIN_SDIO0_DATA0, - TNETV107X_PIN_GPIO21, - TNETV107X_PIN_SDIO0_DATA1, - TNETV107X_PIN_GPIO22, - TNETV107X_PIN_SDIO0_DATA2, - TNETV107X_PIN_GPIO23, - TNETV107X_PIN_SDIO0_DATA3, - TNETV107X_PIN_GPIO24, - TNETV107X_PIN_EMU0, - TNETV107X_PIN_EMU1, - TNETV107X_PIN_RTCK, - TNETV107X_PIN_TRST_N, - TNETV107X_PIN_TCK, - TNETV107X_PIN_TDI, - TNETV107X_PIN_TDO, - TNETV107X_PIN_TMS, - TNETV107X_PIN_TDM1_CLK, - TNETV107X_PIN_TDM1_RX, - TNETV107X_PIN_TDM1_TX, - TNETV107X_PIN_TDM1_FS, - TNETV107X_PIN_KEYPAD_R0, - TNETV107X_PIN_KEYPAD_R1, - TNETV107X_PIN_KEYPAD_R2, - TNETV107X_PIN_KEYPAD_R3, - TNETV107X_PIN_KEYPAD_R4, - TNETV107X_PIN_KEYPAD_R5, - TNETV107X_PIN_KEYPAD_R6, - TNETV107X_PIN_GPIO12, - TNETV107X_PIN_KEYPAD_R7, - TNETV107X_PIN_GPIO10, - TNETV107X_PIN_KEYPAD_C0, - TNETV107X_PIN_KEYPAD_C1, - TNETV107X_PIN_KEYPAD_C2, - TNETV107X_PIN_KEYPAD_C3, - TNETV107X_PIN_KEYPAD_C4, - TNETV107X_PIN_KEYPAD_C5, - TNETV107X_PIN_KEYPAD_C6, - TNETV107X_PIN_GPIO13, - TNETV107X_PIN_TEST_CLK_IN, - TNETV107X_PIN_KEYPAD_C7, - TNETV107X_PIN_GPIO11, - TNETV107X_PIN_SSP0_0, - TNETV107X_PIN_SCC_DCLK, - TNETV107X_PIN_LCD_PD20_1, - TNETV107X_PIN_SSP0_1, - TNETV107X_PIN_SCC_CS_N, - TNETV107X_PIN_LCD_PD21_1, - TNETV107X_PIN_SSP0_2, - TNETV107X_PIN_SCC_D, - TNETV107X_PIN_LCD_PD22_1, - TNETV107X_PIN_SSP0_3, - TNETV107X_PIN_SCC_RESETN, - TNETV107X_PIN_LCD_PD23_1, - TNETV107X_PIN_SSP1_0, - TNETV107X_PIN_GPIO25, - TNETV107X_PIN_UART2_CTS, - TNETV107X_PIN_SSP1_1, - TNETV107X_PIN_GPIO26, - TNETV107X_PIN_UART2_RD, - TNETV107X_PIN_SSP1_2, - TNETV107X_PIN_GPIO27, - TNETV107X_PIN_UART2_RTS, - TNETV107X_PIN_SSP1_3, - TNETV107X_PIN_GPIO28, - TNETV107X_PIN_UART2_TD, - TNETV107X_PIN_UART0_CTS, - TNETV107X_PIN_UART0_RD, - TNETV107X_PIN_UART0_RTS, - TNETV107X_PIN_UART0_TD, - TNETV107X_PIN_UART1_RD, - TNETV107X_PIN_UART1_TD, - TNETV107X_PIN_LCD_AC_NCS, - TNETV107X_PIN_LCD_HSYNC_RNW, - TNETV107X_PIN_LCD_VSYNC_A0, - TNETV107X_PIN_LCD_MCLK, - TNETV107X_PIN_LCD_PD16_0, - TNETV107X_PIN_LCD_PCLK_E, - TNETV107X_PIN_LCD_PD00, - TNETV107X_PIN_LCD_PD01, - TNETV107X_PIN_LCD_PD02, - TNETV107X_PIN_LCD_PD03, - TNETV107X_PIN_LCD_PD04, - TNETV107X_PIN_LCD_PD05, - TNETV107X_PIN_LCD_PD06, - TNETV107X_PIN_LCD_PD07, - TNETV107X_PIN_LCD_PD08, - TNETV107X_PIN_GPIO59_1, - TNETV107X_PIN_LCD_PD09, - TNETV107X_PIN_GPIO60_1, - TNETV107X_PIN_LCD_PD10, - TNETV107X_PIN_ASR_BA0_1, - TNETV107X_PIN_GPIO61_1, - TNETV107X_PIN_LCD_PD11, - TNETV107X_PIN_GPIO62_1, - TNETV107X_PIN_LCD_PD12, - TNETV107X_PIN_GPIO63_1, - TNETV107X_PIN_LCD_PD13, - TNETV107X_PIN_GPIO64_1, - TNETV107X_PIN_LCD_PD14, - TNETV107X_PIN_GPIO29_1, - TNETV107X_PIN_LCD_PD15, - TNETV107X_PIN_GPIO30_1, - TNETV107X_PIN_EINT0, - TNETV107X_PIN_GPIO08, - TNETV107X_PIN_EINT1, - TNETV107X_PIN_GPIO09, - TNETV107X_PIN_GPIO00, - TNETV107X_PIN_LCD_PD20_2, - TNETV107X_PIN_TDM_CLK_IN_2, - TNETV107X_PIN_GPIO01, - TNETV107X_PIN_LCD_PD21_2, - TNETV107X_PIN_24M_CLK_OUT_1, - TNETV107X_PIN_GPIO02, - TNETV107X_PIN_LCD_PD22_2, - TNETV107X_PIN_GPIO03, - TNETV107X_PIN_LCD_PD23_2, - TNETV107X_PIN_GPIO04, - TNETV107X_PIN_LCD_PD16_1, - TNETV107X_PIN_USB0_RXERR, - TNETV107X_PIN_GPIO05, - TNETV107X_PIN_LCD_PD17_1, - TNETV107X_PIN_TDM_CLK_IN_1, - TNETV107X_PIN_GPIO06, - TNETV107X_PIN_LCD_PD18, - TNETV107X_PIN_24M_CLK_OUT_2, - TNETV107X_PIN_GPIO07, - TNETV107X_PIN_LCD_PD19_1, - TNETV107X_PIN_USB1_RXERR, - TNETV107X_PIN_ETH_PLL_CLK, - TNETV107X_PIN_MDIO, - TNETV107X_PIN_MDC, - TNETV107X_PIN_AIC_MUTE_STAT_N, - TNETV107X_PIN_TDM0_CLK, - TNETV107X_PIN_AIC_HNS_EN_N, - TNETV107X_PIN_TDM0_FS, - TNETV107X_PIN_AIC_HDS_EN_STAT_N, - TNETV107X_PIN_TDM0_TX, - TNETV107X_PIN_AIC_HNF_EN_STAT_N, - TNETV107X_PIN_TDM0_RX, -}; - -#endif diff --git a/board/ti/tnetv107xevm/Kconfig b/board/ti/tnetv107xevm/Kconfig deleted file mode 100644 index 637f20e..0000000 --- a/board/ti/tnetv107xevm/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TNETV107X_EVM - -config SYS_BOARD - default "tnetv107xevm" - -config SYS_VENDOR - default "ti" - -config SYS_SOC - default "tnetv107x" - -config SYS_CONFIG_NAME - default "tnetv107x_evm" - -endif diff --git a/board/ti/tnetv107xevm/MAINTAINERS b/board/ti/tnetv107xevm/MAINTAINERS deleted file mode 100644 index 8a92c6b..0000000 --- a/board/ti/tnetv107xevm/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TNETV107XEVM BOARD -#M: Chan-Taek Park c-park@ti.com -S: Orphan (since 2014-06) -F: board/ti/tnetv107xevm/ -F: include/configs/tnetv107x_evm.h -F: configs/tnetv107x_evm_defconfig diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile deleted file mode 100644 index 0a6128f..0000000 --- a/board/ti/tnetv107xevm/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += sdb_board.o diff --git a/board/ti/tnetv107xevm/config.mk b/board/ti/tnetv107xevm/config.mk deleted file mode 100644 index 51c2886..0000000 --- a/board/ti/tnetv107xevm/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0x83FC0000 diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c deleted file mode 100644 index a84ec84..0000000 --- a/board/ti/tnetv107xevm/sdb_board.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * TNETV107X-EVM: Board initialization - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <miiphy.h> -#include <linux/mtd/nand.h> -#include <asm/arch/hardware.h> -#include <asm/arch/clock.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <asm/ti-common/davinci_nand.h> -#include <asm/arch/mux.h> - -DECLARE_GLOBAL_DATA_PTR; - -static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = { - { /* CS0 */ - .mode = ASYNC_EMIF_MODE_NAND, - .wr_setup = 5, - .wr_strobe = 5, - .wr_hold = 2, - .rd_setup = 5, - .rd_strobe = 5, - .rd_hold = 2, - .turn_around = 5, - .width = ASYNC_EMIF_8, - }, - { /* CS1 */ - .mode = ASYNC_EMIF_MODE_NOR, - .wr_setup = 2, - .wr_strobe = 27, - .wr_hold = 4, - .rd_setup = 2, - .rd_strobe = 27, - .rd_hold = 4, - .turn_around = 2, - .width = ASYNC_EMIF_PRESERVE, - }, - { /* CS2 */ - .mode = ASYNC_EMIF_MODE_NOR, - .wr_setup = 2, - .wr_strobe = 27, - .wr_hold = 4, - .rd_setup = 2, - .rd_strobe = 27, - .rd_hold = 4, - .turn_around = 2, - .width = ASYNC_EMIF_PRESERVE, - }, - { /* CS3 */ - .mode = ASYNC_EMIF_MODE_NOR, - .wr_setup = 1, - .wr_strobe = 90, - .wr_hold = 3, - .rd_setup = 1, - .rd_strobe = 26, - .rd_hold = 3, - .turn_around = 1, - .width = ASYNC_EMIF_8, - }, -}; - -static struct pll_init_data pll_config[] = { - { - .pll = ETH_PLL, - .internal_osc = 1, - .pll_freq = 500000000, - .div_freq = { - 5000000, 50000000, 125000000, 250000000, 25000000, - }, - }, -}; - -static const short sdio1_pins[] = { - TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1, - TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1, - TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1, - -1 -}; - -static const short uart1_pins[] = { - TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1 -}; - -static const short ssp_pins[] = { - TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2, - TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2, - TNETV107X_PIN_SSP1_3, -1 -}; - -int board_init(void) -{ -#ifndef CONFIG_USE_IRQ - __raw_writel(0, INTC_GLB_EN); /* Global disable */ - __raw_writel(0, INTC_HINT_EN); /* Disable host ints */ - __raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */ - __raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */ - __raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */ -#endif - - gd->bd->bi_arch_number = MACH_TYPE_TNETV107X; - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - init_plls(ARRAY_SIZE(pll_config), pll_config); - - init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config); - - mux_select_pin(TNETV107X_PIN_ASR_CS3); - mux_select_pins(sdio1_pins); - mux_select_pins(uart1_pins); - mux_select_pins(ssp_pins); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#ifdef CONFIG_NAND_DAVINCI -int board_nand_init(struct nand_chip *nand) -{ - davinci_nand_init(nand); - - return 0; -} -#endif diff --git a/configs/tnetv107x_evm_defconfig b/configs/tnetv107x_evm_defconfig deleted file mode 100644 index b0915d2..0000000 --- a/configs/tnetv107x_evm_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_TNETV107X_EVM=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 7ce7101..f34afce 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.

Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +tnetv107x arm arm1176 - - Chan-Taek Park c-park@ti.com a320evb arm arm920t - - Po-Yu Chuang ratbert@faraday-tech.com cm4008 arm arm920t - - Greg Ungerer greg.ungerer@opengear.com cm41xx arm arm920t - - diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 1dc0f5a..482a4bd 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa)) obj-y += imx_watchdog.o endif -obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o diff --git a/drivers/watchdog/tnetv107x_wdt.c b/drivers/watchdog/tnetv107x_wdt.c deleted file mode 100644 index 3d3f366..0000000 --- a/drivers/watchdog/tnetv107x_wdt.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * TNETV107X: Watchdog timer implementation (for reset) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/clock.h> - -#define MAX_DIV 0xFFFE0001 - -struct wdt_regs { - u32 kick_lock; -#define KICK_LOCK_1 0x5555 -#define KICK_LOCK_2 0xaaaa - u32 kick; - - u32 change_lock; -#define CHANGE_LOCK_1 0x6666 -#define CHANGE_LOCK_2 0xbbbb - u32 change; - - u32 disable_lock; -#define DISABLE_LOCK_1 0x7777 -#define DISABLE_LOCK_2 0xcccc -#define DISABLE_LOCK_3 0xdddd - u32 disable; - - u32 prescale_lock; -#define PRESCALE_LOCK_1 0x5a5a -#define PRESCALE_LOCK_2 0xa5a5 - u32 prescale; -}; - -static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE; - -#define wdt_reg_read(reg) __raw_readl(&regs->reg) -#define wdt_reg_write(reg, val) __raw_writel((val), &regs->reg) - -static int write_prescale_reg(unsigned long prescale_value) -{ - wdt_reg_write(prescale_lock, PRESCALE_LOCK_1); - if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(prescale_lock, PRESCALE_LOCK_2); - if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(prescale, prescale_value); - - return 0; -} - -static int write_change_reg(unsigned long initial_timer_value) -{ - wdt_reg_write(change_lock, CHANGE_LOCK_1); - if ((wdt_reg_read(change_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(change_lock, CHANGE_LOCK_2); - if ((wdt_reg_read(change_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(change, initial_timer_value); - - return 0; -} - -static int wdt_control(unsigned long disable_value) -{ - wdt_reg_write(disable_lock, DISABLE_LOCK_1); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(disable_lock, DISABLE_LOCK_2); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x2) - return -1; - - wdt_reg_write(disable_lock, DISABLE_LOCK_3); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(disable, disable_value); - return 0; -} - -static int wdt_set_period(unsigned long msec) -{ - unsigned long change_value, count_value; - unsigned long prescale_value = 1; - unsigned long refclk_khz, maxdiv; - int ret; - - refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM); - maxdiv = (MAX_DIV / refclk_khz); - - if ((!msec) || (msec > maxdiv)) - return -1; - - count_value = refclk_khz * msec; - if (count_value > 0xffff) { - change_value = count_value / 0xffff + 1; - prescale_value = count_value / change_value; - } else { - change_value = count_value; - } - - ret = write_prescale_reg(prescale_value - 1); - if (ret) - return ret; - - ret = write_change_reg(change_value); - if (ret) - return ret; - - return 0; -} - -unsigned long last_wdt = -1; - -int wdt_start(unsigned long msecs) -{ - int ret; - ret = wdt_control(0); - if (ret) - return ret; - ret = wdt_set_period(msecs); - if (ret) - return ret; - ret = wdt_control(1); - if (ret) - return ret; - ret = wdt_kick(); - last_wdt = msecs; - return ret; -} - -int wdt_stop(void) -{ - last_wdt = -1; - return wdt_control(0); -} - -int wdt_kick(void) -{ - wdt_reg_write(kick_lock, KICK_LOCK_1); - if ((wdt_reg_read(kick_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(kick_lock, KICK_LOCK_2); - if ((wdt_reg_read(kick_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(kick, 1); - return 0; -} - -void reset_cpu(ulong addr) -{ - clk_enable(TNETV107X_LPSC_WDT_ARM); - wdt_start(1); - wdt_kick(); -} diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h deleted file mode 100644 index 00a1a9e..0000000 --- a/include/configs/tnetv107x_evm.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2008 Texas Instruments, Inc <www.ti.com> - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn ksi@koi8.net - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <linux/sizes.h> -#include <asm/arch/hardware.h> -#include <asm/arch/clock.h> - -/* Architecture, CPU, etc */ -#define CONFIG_TNETV107X -#define CONFIG_TNETV107X_EVM -#define CONFIG_TNETV107X_WATCHDOG -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_DISABLE_TCM -#define CONFIG_PERIPORT_REMAP -#define CONFIG_PERIPORT_BASE 0x2000000 -#define CONFIG_PERIPORT_SIZE 0x10 -#define CONFIG_SYS_CLK_FREQ clk_get_rate(TNETV107X_LPSC_ARM) - -#define CONFIG_SYS_TIMERBASE TNETV107X_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get_rate(TNETV107X_LPSC_TIMER0) - -#define CONFIG_PLL_SYS_EXT_FREQ 25000000 -#define CONFIG_PLL_TDM_EXT_FREQ 19200000 -#define CONFIG_PLL_ETH_EXT_FREQ 25000000 - -/* Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) -#define PHYS_SDRAM_1 TNETV107X_DDR_EMIF_DATA_BASE -#define PHYS_SDRAM_1_SIZE 0x04000000 -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Serial Driver Info */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 TNETV107X_UART1_BASE -#define CONFIG_SYS_NS16550_CLK clk_get_rate(TNETV107X_LPSC_UART1) -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Flash and environment info */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (SZ_128K) -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_NAND_1BIT_ECC -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE -#define CONFIG_JFFS2_NAND -#define CONFIG_ENV_OFFSET 0x180000 - -/* - * davinci_nand is a bit of a misnomer since this particular EMIF block is - * commonly used across multiple TI devices. Unfortunately, this misnomer - * (amongst others) carries forward into the kernel too. Consequently, if we - * use a different device name here, the mtdparts variable won't be usable as - * a kernel command-line argument. - */ -#define MTDIDS_DEFAULT "nand0=davinci_nand.0" -#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ - "1536k(uboot)ro," \ - "128k(params)ro," \ - "4m(kernel)," \ - "-(filesystem)" - -/* General U-Boot configuration */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_SYS_PROMPT "U-Boot > " -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + \ - 0x700000) -#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=32M console=ttyS1,115200n8 " \ - "root=/dev/mmcblk0p1 rw noinitrd" -#define CONFIG_BOOTCOMMAND "" -#define CONFIG_BOOTDELAY 1 - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_IMI -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_ENV -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NAND -#define CONFIG_CMD_JFFS2 - -#endif /* __CONFIG_H */