[PATCH v1] cache_v8: agilex5: Disable Dcache in the SPL
From: Kah Jing Lee kah.jing.lee@intel.com
Dcache feature is not enabled in SPL and enable it will cause ISR exception. Since the Dcache is not supported in SPL, new CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache in SPL.
Signed-off-by: Kah Jing Lee kah.jing.lee@intel.com --- arch/arm/cpu/armv8/cache_v8.c | 20 +++++++++++--------- common/spl/Kconfig | 7 +++++++ 2 files changed, 18 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index cb1131a048..7f25d3a6ce 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -534,29 +534,31 @@ inline void flush_dcache_all(void) #endif }
-#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS -/* - * Invalidates range in all levels of D-cache/unified cache - */ +#if CONFIG_IS_ENABLED(SYS_DISABLE_DCACHE_OPS) || \ + CONFIG_IS_ENABLED(SPL_SYS_DISABLE_DCACHE_OPS) && \ + CONFIG_IS_ENABLED(SPL_BUILD) void invalidate_dcache_range(unsigned long start, unsigned long stop) { - __asm_invalidate_dcache_range(start, stop); }
-/* - * Flush range(clean & invalidate) from all levels of D-cache/unified cache - */ void flush_dcache_range(unsigned long start, unsigned long stop) { - __asm_flush_dcache_range(start, stop); } #else +/* + * Invalidates range in all levels of D-cache/unified cache + */ void invalidate_dcache_range(unsigned long start, unsigned long stop) { + __asm_invalidate_dcache_range(start, stop); }
+/* + * Flush range(clean & invalidate) from all levels of D-cache/unified cache + */ void flush_dcache_range(unsigned long start, unsigned long stop) { + __asm_flush_dcache_range(start, stop); } #endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2c042ad306..7e458503df 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -19,6 +19,13 @@ config SPL menu "SPL configuration options" depends on SPL
+config SPL_SYS_DISABLE_DCACHE_OPS + bool "Do not enable dcache operation in SPL" + depends on SPL + help + Do not enable data cache operation in SPL. This will turn off the + Dcache support and have the empty dcache declaration. + config SPL_FRAMEWORK bool "Support SPL based upon the common SPL framework" default y
On Wed, 21 Jun 2023 15:06:51 +0100, Jit Loon Lim jit.loon.lim@intel.com wrote:
From: Kah Jing Lee kah.jing.lee@intel.com
Dcache feature is not enabled in SPL and enable it will cause ISR exception. Since the Dcache is not supported in SPL, new CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache in SPL.
Signed-off-by: Kah Jing Lee kah.jing.lee@intel.com
This is missing your own SoB.
Now, I'd like to understand what you are actually trying to fix. What is this 'ISR' exception? This isn't something the architecture describes. Unless you are using CMOs on something that isn't memory or for which you don't have a mapping, this should never generate an exception.
Thanks,
M.
On 6/21/23 16:15, Marc Zyngier wrote:
On Wed, 21 Jun 2023 15:06:51 +0100, Jit Loon Lim jit.loon.lim@intel.com wrote:
From: Kah Jing Lee kah.jing.lee@intel.com
Dcache feature is not enabled in SPL and enable it will cause ISR exception. Since the Dcache is not supported in SPL, new CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache in SPL.
Signed-off-by: Kah Jing Lee kah.jing.lee@intel.com
This is missing your own SoB.
Now, I'd like to understand what you are actually trying to fix. What is this 'ISR' exception? This isn't something the architecture describes. Unless you are using CMOs on something that isn't memory or for which you don't have a mapping, this should never generate an exception.
You beat me to it, indeed, thanks !
-----Original Message----- From: Marek Vasut marex@denx.de Sent: Wednesday, 21 June, 2023 10:20 PM To: Marc Zyngier maz@kernel.org; Lim, Jit Loon jit.loon.lim@intel.com Cc: u-boot@lists.denx.de; Jagan Teki jagan@amarulasolutions.com; Simon simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Hea, Kok Kiang kok.kiang.hea@intel.com; Lokanathan, Raaj raaj.lokanathan@intel.com; Maniyam, Dinesh dinesh.maniyam@intel.com; Ng, Boon Khai boon.khai.ng@intel.com; Yuslaimi, Alif Zakuan alif.zakuan.yuslaimi@intel.com; Chong, Teik Heng teik.heng.chong@intel.com; Zamri, Muhammad Hazim Izzat muhammad.hazim.izzat.zamri@intel.com; Tang, Sieu Mun sieu.mun.tang@intel.com; Ying-Chun Liu paul.liu@linaro.org; Lee, Kah Jing kah.jing.lee@intel.com Subject: Re: [PATCH v1] cache_v8: agilex5: Disable Dcache in the SPL
On 6/21/23 16:15, Marc Zyngier wrote:
On Wed, 21 Jun 2023 15:06:51 +0100, Jit Loon Lim jit.loon.lim@intel.com wrote:
From: Kah Jing Lee kah.jing.lee@intel.com
Dcache feature is not enabled in SPL and enable it will cause ISR exception. Since the Dcache is not supported in SPL, new CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache in SPL.
Signed-off-by: Kah Jing Lee kah.jing.lee@intel.com
This is missing your own SoB.
Now, I'd like to understand what you are actually trying to fix. What is this 'ISR' exception? This isn't something the architecture describes. Unless you are using CMOs on something that isn't memory or for which you don't have a mapping, this should never generate an exception.
You beat me to it, indeed, thanks !
The intention of doing this is because when we init SDMMC driver, the driver will call the invalidate_dcache_range. However, during that time, the dcache is not available in SPL yet thus causing exception. https://elixir.bootlin.com/u-boot/latest/source/drivers/mmc/sdhci.c#L181 -> https://elixir.bootlin.com/u-boot/latest/source/include/linux/dma-mapping.h#... -> https://elixir.bootlin.com/u-boot/latest/source/arch/arm/cpu/armv8/cache_v8....
On Mon, 26 Jun 2023 10:00:09 +0100, "Lim, Jit Loon" jit.loon.lim@intel.com wrote:
-----Original Message----- From: Marek Vasut marex@denx.de Sent: Wednesday, 21 June, 2023 10:20 PM To: Marc Zyngier maz@kernel.org; Lim, Jit Loon jit.loon.lim@intel.com Cc: u-boot@lists.denx.de; Jagan Teki jagan@amarulasolutions.com; Simon simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Hea, Kok Kiang kok.kiang.hea@intel.com; Lokanathan, Raaj raaj.lokanathan@intel.com; Maniyam, Dinesh dinesh.maniyam@intel.com; Ng, Boon Khai boon.khai.ng@intel.com; Yuslaimi, Alif Zakuan alif.zakuan.yuslaimi@intel.com; Chong, Teik Heng teik.heng.chong@intel.com; Zamri, Muhammad Hazim Izzat muhammad.hazim.izzat.zamri@intel.com; Tang, Sieu Mun sieu.mun.tang@intel.com; Ying-Chun Liu paul.liu@linaro.org; Lee, Kah Jing kah.jing.lee@intel.com Subject: Re: [PATCH v1] cache_v8: agilex5: Disable Dcache in the SPL
On 6/21/23 16:15, Marc Zyngier wrote:
On Wed, 21 Jun 2023 15:06:51 +0100, Jit Loon Lim jit.loon.lim@intel.com wrote:
From: Kah Jing Lee kah.jing.lee@intel.com
Dcache feature is not enabled in SPL and enable it will cause ISR exception. Since the Dcache is not supported in SPL, new CONFIG_SPL_SYS_DISABLE_DCACHE_OPS is added to Kconfig to disable Dcache in SPL.
Signed-off-by: Kah Jing Lee kah.jing.lee@intel.com
This is missing your own SoB.
Now, I'd like to understand what you are actually trying to fix. What is this 'ISR' exception? This isn't something the architecture describes. Unless you are using CMOs on something that isn't memory or for which you don't have a mapping, this should never generate an exception.
You beat me to it, indeed, thanks !
The intention of doing this is because when we init SDMMC driver, the driver will call the invalidate_dcache_range. However, during that time, the dcache is not available in SPL yet thus causing exception.
Again: which exception?
There is no such thing as "the dcache isn't available". It is always valid to invalidate it, irrespective of it being enabled or not.
My impression is that you are papering over another bug (such as feeding non-memory to the CMOs), and are getting an SError back, which would be entirely justified.
M.
On 6/21/23 16:06, Jit Loon Lim wrote:
From: Kah Jing Lee kah.jing.lee@intel.com
Dcache feature is not enabled in SPL and enable it will cause ISR exception
Why would it cause an exception ?
participants (4)
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Jit Loon Lim -
Lim, Jit Loon
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Marc Zyngier -
Marek Vasut