[U-Boot] [PATCH v5 0/5] iMX6 SabreSD SPL Support
This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.
After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC.
sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69
Changes (v2): Merged the SPL support into the main board file Remove the compilation warmings
Changes (v3): Removed sp and gd Use imx_ddr_size to set the ram_size
Changes (v4): Add a separate board configuration file to enable SPL (mx6sabresd_spl_defconfig).
Mapped DCD data to mx6_mmdc_calibration, mx6dq_iomux_grp_regs, mx6dq_iomux_ddr_regs and mx6_ddr3_cfg data structures.
Read 11 and 12 bits of BOOT_CFG register to actually determine the active mmc port.
Changes (v5): Use the default CONFIG_SPL_STACK Add a macro #ifndef for CONFIG_SYS_TEXT_BASE to avoid compilation warning.
John Tobias (5): kconfig: imx6: add SUPPORT_SPL imx6: add spl in the header file imx6: add spl config for mx6sabresd mmc: imx6: call spl_board_mmc_init imx6: SPL support for iMX6 SabreSD
arch/arm/Kconfig | 1 + board/freescale/mx6sabresd/mx6sabresd.c | 187 +++++++++++++++++++++++++++++++- configs/mx6sabresd_spl_defconfig | 5 + drivers/mmc/mmc.c | 9 +- include/configs/mx6sabre_common.h | 2 + include/configs/mx6sabresd.h | 6 + include/mmc.h | 3 + 7 files changed, 208 insertions(+), 5 deletions(-) create mode 100644 configs/mx6sabresd_spl_defconfig
add SUPPORT_SPL feature for iMX6 SabreSD. It need to use mx6sabresd_spl_defconfig to compile it.
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 22eb2d5..ab0d284 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -609,6 +609,7 @@ config TARGET_MX6QSABREAUTO config TARGET_MX6SABRESD bool "Support mx6sabresd" select CPU_V7 + select SUPPORT_SPL
config TARGET_MX6SLEVK bool "Support mx6slevk"
add the spl info in the header file. Also, added the macro statement in m6sabre_common.h to avoid compiler warning.
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- include/configs/mx6sabre_common.h | 2 ++ include/configs/mx6sabresd.h | 6 ++++++ 2 files changed, 8 insertions(+)
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index c81e9e9..e4d0d14 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -95,7 +95,9 @@ #define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x12000000 +#ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x17800000 +#endif
#ifdef CONFIG_SUPPORT_EMMC_BOOT #define EMMC_ENV \ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 938030d..a346542 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -12,6 +12,12 @@ #include <asm/arch/imx-regs.h> #include <asm/imx-common/gpio.h>
+#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" +#endif + #define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONSOLE_DEV "ttymxc0"
add a build configuration file for mx6sabresd with spl support
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- configs/mx6sabresd_spl_defconfig | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 configs/mx6sabresd_spl_defconfig
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig new file mode 100644 index 0000000..b7b26df --- /dev/null +++ b/configs/mx6sabresd_spl_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX6SABRESD=y +
When the spl_mmc_load_image function being called, it will call mmc_initialize function. By default, it will call board_mmc_init.
The main purpose of board_mmc_init (in practice) is to initialize all the mmc ports defined by CONFIG_SYS_FSL_USDHC_NUM.
While, in spl_board_mmc_init, it will read the bootstrap to see which mmc port is active and configure it.
Then, it pass the configuration to fsl_esdhc_initialize for initialization. Finally, the spl_mmc_load_image could load and run the u-boot.img
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- drivers/mmc/mmc.c | 9 ++++++--- include/mmc.h | 3 +++ 2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 44a4feb..88c1b03 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1441,11 +1441,14 @@ int mmc_initialize(bd_t *bis) INIT_LIST_HEAD (&mmc_devices); cur_dev_num = 0;
- if (board_mmc_init(bis) < 0) +#ifdef CONFIG_SPL_BUILD + if (spl_board_mmc_init(bis) < 0) cpu_mmc_init(bis); +#else + if (board_mmc_init(bis) < 0) + cpu_mmc_init(bis);
-#ifndef CONFIG_SPL_BUILD - print_mmc_devices(','); + print_mmc_devices(','); #endif
do_preinit(); diff --git a/include/mmc.h b/include/mmc.h index d74a190..37119b8 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -388,6 +388,9 @@ int mmc_legacy_init(int verbose); int board_mmc_init(bd_t *bis); int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); +#ifdef CONFIG_SPL +int spl_board_mmc_init(bd_t *bis); +#endif
/* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
This patch will enable the support for SPL on iMX6 SabreSD. It tested on SD2 and SD3 mmc port.
It uses mx6dq_dram_iocfg and mx6_dram_cfg for ddr configuration.
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- board/freescale/mx6sabresd/mx6sabresd.c | 187 +++++++++++++++++++++++++++++++- 1 file changed, 185 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 3d81fff..16cfb44 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -27,6 +27,8 @@ #include <i2c.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include <asm/arch/mx6-ddr.h> + DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ @@ -55,8 +57,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - + gd->ram_size = imx_ddr_size(); return 0; }
@@ -607,3 +608,185 @@ int checkboard(void) puts("Board: MX6-SabreSD\n"); return 0; } + +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#include <libfdt.h> + +#define BOOT_CFG 0x020D8004 +struct fsl_esdhc_cfg spl_usdhc_cfg; + +const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x001F001F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + .p0_mpdgctrl0 = 0x434B0350, + .p0_mpdgctrl1 = 0x034C0359, + .p1_mpdgctrl0 = 0x434B0350, + .p1_mpdgctrl1 = 0x03650348, + .p0_mprddlctl = 0x4436383B, + .p1_mprddlctl = 0x39393341, + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254A36, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 64, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* + * This section require the differentiation + * between iMX6 Sabre Families. + * But for now, it will configure only for + * SabreSD. + */ +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = mem_ddr.width/32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 2, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +int spl_board_mmc_init(bd_t *bis) +{ + unsigned reg = readl(BOOT_CFG) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + switch (reg & 0x3) { + case 0x1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + spl_usdhc_cfg.esdhc_base = USDHC2_BASE_ADDR; + spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk; + break; + case 0x2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + spl_usdhc_cfg.esdhc_base = USDHC3_BASE_ADDR; + spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk; + break; + case 0x3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + spl_usdhc_cfg.esdhc_base = USDHC4_BASE_ADDR; + spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = spl_usdhc_cfg.sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bis, &spl_usdhc_cfg); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif
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John Tobias