[U-Boot] [PATCH 0/9] ARM: sunxi: Add Allwinner A23 (sun8i) support
Hi everyone,
This series adds support for Allwinner's A23 SoC. All the patches are either direct cherry-picks or changes manually merged from u-boot-sunxi.
Patch 1 fixes build breaks when CONFIG_MMC is not set. This happens when we use port F for uart0.
Patch 2 adds uart0 pinmux values for A23.
Patch 3 adds support for using uart0 on port F, either using a breakout board or soldering wires to exposed pads. At least one version of A23 tablets requires this, as no other uarts are exposed.
Patch 4 adds support for sun8i in the mmc driver. This is the same as sun6i.
Patch 5 adds machine support for sun8i.
Patch 6 adds support for gpio banks L and beyond, which is used by r_uart, p2wi (on sun6i) and rsb (on sun8i).
Patch 7 makes the prcm apb0 clock enabling function to take an argument for which modules should be enabled.
Patch 8 adds support for using r_uart as a console (with CONS_INDEX=5).
Patch 9 adds a defconfig for the Ippo Q8H A23 tablet board.
Cheers ChenYu
Chen-Yu Tsai (8): ARM: sunxi: Fix build break when CONFIG_MMC is not defined ARM: sunxi: Add sun8i (A23) UART0 pin mux support ARM: sunxi: Add support for uart0 on port F (mmc0) mmc: sunxi: Add support for sun8i (A23) ARM: sunxi: Add basic A23 support ARM: sunxi: Allow specifying module in prcm apb0 init function ARM: sunxi: Add support for using R_UART as console ARM: sunxi: Add Ippo-q8h-v5 A23 tablet board defconfig
Hans de Goede (1): ARM: sunxi: Add support for R_PIO gpio banks
arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv7/sunxi/Makefile | 2 ++ arch/arm/cpu/armv7/sunxi/board.c | 18 +++++++++++++++-- arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 ++++++ arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++ arch/arm/cpu/armv7/sunxi/prcm.c | 12 +++++++----- arch/arm/include/asm/arch-sunxi/clock.h | 2 +- arch/arm/include/asm/arch-sunxi/cpu.h | 1 + arch/arm/include/asm/arch-sunxi/gpio.h | 34 +++++++++++++++++++++++++++++++-- arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- board/sunxi/Kconfig | 9 ++++++++- board/sunxi/MAINTAINERS | 5 +++++ configs/Ippo_q8h_defconfig | 4 ++++ drivers/mmc/sunxi_mmc.c | 2 +- include/configs/sun8i.h | 23 ++++++++++++++++++++++ include/configs/sunxi-common.h | 11 ++++++++++- 17 files changed, 123 insertions(+), 15 deletions(-) create mode 100644 configs/Ippo_q8h_defconfig create mode 100644 include/configs/sun8i.h
BOOT_TARGET_DEVICES includes MMC unconditionally. This breaks when CONFIG_CMD_MMC is not defined. Use a secondary macro to conditionally include it when CONFIG_MMC is enabled, as we do for CONFIG_AHCI.
This is used when we want to use uart0 from port F, which conflicts with mmc0.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- include/configs/sunxi-common.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index a31656e..7571e0e 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -227,6 +227,12 @@ "pxefile_addr_r=0x43200000\0" \ "ramdisk_addr_r=0x43300000\0"
+#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + #ifdef CONFIG_AHCI #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) #else @@ -240,7 +246,7 @@ #endif
#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ + BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
BOOT_TARGET_DEVICES includes MMC unconditionally. This breaks when CONFIG_CMD_MMC is not defined. Use a secondary macro to conditionally include it when CONFIG_MMC is enabled, as we do for CONFIG_AHCI.
This is used when we want to use uart0 from port F, which conflicts with mmc0.
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Ian Campbell ijc@hellion.org.uk
Hans, this made me think back to your " Enable second sdcard slot found on some boards" series -- do you not want to add mmc1 as a boot target device when MMC_SUNXI_SLOT_EXTRA is enabled?
include/configs/sunxi-common.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index a31656e..7571e0e 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -227,6 +227,12 @@ "pxefile_addr_r=0x43200000\0" \ "ramdisk_addr_r=0x43300000\0"
+#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif
#ifdef CONFIG_AHCI #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) #else @@ -240,7 +246,7 @@ #endif
#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \
Hi,
On 10/11/2014 05:50 PM, Ian Campbell wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
BOOT_TARGET_DEVICES includes MMC unconditionally. This breaks when CONFIG_CMD_MMC is not defined. Use a secondary macro to conditionally include it when CONFIG_MMC is enabled, as we do for CONFIG_AHCI.
This is used when we want to use uart0 from port F, which conflicts with mmc0.
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Ian Campbell ijc@hellion.org.uk
Hans, this made me think back to your " Enable second sdcard slot found on some boards" series -- do you not want to add mmc1 as a boot target device when MMC_SUNXI_SLOT_EXTRA is enabled?
An interesting question. u-boot itself is always running of mmc 0, or loaded through FEL, but that does not mean that e.g. extlinux.conf + the kernel and dts could not be on mmc 1. So yes I guess we do want to add mmc 1 as boot target.
First lets get Chen's patches + my existing second mmc slot set merged into u-boot-sunxi next, and then I'll do a patch on top of that.
Regards,
Hans
include/configs/sunxi-common.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index a31656e..7571e0e 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -227,6 +227,12 @@ "pxefile_addr_r=0x43200000\0" \ "ramdisk_addr_r=0x43300000\0"
+#ifdef CONFIG_MMC +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif
#ifdef CONFIG_AHCI #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) #else @@ -240,7 +246,7 @@ #endif
#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0) \
- BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_SCSI(func) \ BOOT_TARGET_DEVICES_USB(func) \ func(PXE, pxe, na) \
UART0 pin muxes on the A23 have a different function value.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/include/asm/arch-sunxi/gpio.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index ba7e69b..b94ec4d 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -125,8 +125,14 @@ enum sunxi_gpio_number { #define SUNXI_GPF0_SDC0 2
#define SUNXI_GPF2_SDC0 2 + +#ifdef CONFIG_SUN8I +#define SUNXI_GPF2_UART0_TX 3 +#define SUNXI_GPF4_UART0_RX 3 +#else #define SUNXI_GPF2_UART0_TX 4 #define SUNXI_GPF4_UART0_RX 4 +#endif
#define SUN4I_GPG0_SDC1 4
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
UART0 pin muxes on the A23 have a different function value.
Signed-off-by: Chen-Yu Tsai wens@csie.org
Sigh, why can't silicon folks resist fiddling with stuff ;-)
Acked-by: Ian Campbell ijc@hellion.org.uk
arch/arm/include/asm/arch-sunxi/gpio.h | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index ba7e69b..b94ec4d 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -125,8 +125,14 @@ enum sunxi_gpio_number { #define SUNXI_GPF0_SDC0 2
#define SUNXI_GPF2_SDC0 2
+#ifdef CONFIG_SUN8I +#define SUNXI_GPF2_UART0_TX 3 +#define SUNXI_GPF4_UART0_RX 3 +#else #define SUNXI_GPF2_UART0_TX 4 #define SUNXI_GPF4_UART0_RX 4 +#endif
#define SUN4I_GPG0_SDC1 4
Allwinner SoCs provide uart0 muxed with mmc0, which can then be used with a micro SD breakout board. On the A23, this is the only way to use uart0.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/cpu/armv7/sunxi/board.c | 11 ++++++++++- include/configs/sunxi-common.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index b6d63db..29d45b6 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -50,7 +50,16 @@ u32 spl_boot_mode(void)
int gpio_init(void) { -#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) +#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I) + /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); +#endif + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPF(4), 1); +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 7571e0e..7857a56 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -77,6 +77,7 @@ #define CONFIG_INITRD_TAG
/* mmc config */ +#if !defined(CONFIG_UART0_PORT_F) #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_CMD_MMC @@ -84,6 +85,7 @@ #define CONFIG_MMC_SUNXI_SLOT 0 #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ +#endif
/* 4MB of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
Allwinner SoCs provide uart0 muxed with mmc0, which can then be used with a micro SD breakout board. On the A23, this is the only way to use uart0.
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Ian Campbell ijc@hellion.org.uk
arch/arm/cpu/armv7/sunxi/board.c | 11 ++++++++++- include/configs/sunxi-common.h | 2 ++ 2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index b6d63db..29d45b6 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -50,7 +50,16 @@ u32 spl_boot_mode(void)
int gpio_init(void) { -#if CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) +#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
- /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
- sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
+#endif
- sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
- sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
+#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP); diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 7571e0e..7857a56 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -77,6 +77,7 @@ #define CONFIG_INITRD_TAG
/* mmc config */ +#if !defined(CONFIG_UART0_PORT_F) #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_CMD_MMC @@ -84,6 +85,7 @@ #define CONFIG_MMC_SUNXI_SLOT 0 #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ +#endif
/* 4MB of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
The Allwinner A23 SoC has reset controls like the A31 (sun6i). The FIFO address is also the same as sun6i.
Re-use code added for sun6i.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- drivers/mmc/sunxi_mmc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index 6a31184..5836ae9 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -43,7 +43,7 @@ struct sunxi_mmc { u32 chda; /* 0x90 */ u32 cbda; /* 0x94 */ u32 res1[26]; -#if defined(CONFIG_SUN6I) +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) u32 res2[64]; #endif u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */ diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 8f4b50b..23a2ec0 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -73,7 +73,7 @@ static int mmc_clk_io_on(int sdc_no) /* config ahb clock */ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
-#if defined(CONFIG_SUN6I) +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) /* unassert reset */ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); #endif
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The Allwinner A23 SoC has reset controls like the A31 (sun6i). The FIFO address is also the same as sun6i.
Re-use code added for sun6i.
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Ian Campbell ijc@hellion.org.uk
arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- drivers/mmc/sunxi_mmc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index 6a31184..5836ae9 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -43,7 +43,7 @@ struct sunxi_mmc { u32 chda; /* 0x90 */ u32 cbda; /* 0x94 */ u32 res1[26]; -#if defined(CONFIG_SUN6I) +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) u32 res2[64]; #endif u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */ diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 8f4b50b..23a2ec0 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -73,7 +73,7 @@ static int mmc_clk_io_on(int sdc_no) /* config ahb clock */ setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
-#if defined(CONFIG_SUN6I) +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) /* unassert reset */ setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); #endif
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv7/sunxi/Makefile | 2 ++ arch/arm/cpu/armv7/sunxi/board.c | 3 ++- arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++ arch/arm/include/asm/arch-sunxi/clock.h | 2 +- board/sunxi/Kconfig | 9 ++++++++- include/configs/sun8i.h | 23 +++++++++++++++++++++++ 7 files changed, 41 insertions(+), 3 deletions(-) create mode 100644 include/configs/sun8i.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e3e7e78..cb691b2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -450,6 +450,9 @@ config TARGET_SUN6I config TARGET_SUN7I bool "Support sun7i"
+config TARGET_SUN8I + bool "Support sun8i" + config TARGET_SNOWBALL bool "Support snowball"
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 2a42dca..24f1dae 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -12,10 +12,12 @@ obj-y += board.o obj-y += clock.o obj-y += pinmux.o obj-$(CONFIG_SUN6I) += prcm.o +obj-$(CONFIG_SUN8I) += prcm.o obj-$(CONFIG_SUN4I) += clock_sun4i.o obj-$(CONFIG_SUN5I) += clock_sun4i.o obj-$(CONFIG_SUN6I) += clock_sun6i.o obj-$(CONFIG_SUN7I) += clock_sun4i.o +obj-$(CONFIG_SUN8I) += clock_sun6i.o
ifndef CONFIG_SPL_BUILD obj-y += cpu_info.o diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 29d45b6..61c1ba9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -100,7 +100,8 @@ void reset_cpu(ulong addr) /* do some early init */ void s_init(void) { -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I) +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \ + defined CONFIG_SUN6I || defined CONFIG_SUN8I) /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n" diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index 40c4e13..4f2a09c 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -27,6 +27,8 @@ int print_cpuinfo(void) puts("CPU: Allwinner A31 (SUN6I)\n"); #elif defined CONFIG_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); +#elif defined CONFIG_SUN8I + puts("CPU: Allwinner A23 (SUN8I)\n"); #else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 8f5d860..012c2af 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -15,7 +15,7 @@ #define CLK_GATE_CLOSE 0x0
/* clock control module regs definition */ -#ifdef CONFIG_SUN6I +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) #include <asm/arch/clock_sun6i.h> #else #include <asm/arch/clock_sun4i.h> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 05defac..16f6db4 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -27,7 +27,14 @@ config SYS_CONFIG_NAME
endif
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I +if TARGET_SUN8I + +config SYS_CONFIG_NAME + default "sun8i" + +endif + +if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I || TARGET_SUN8I
config SYS_CPU default "armv7" diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h new file mode 100644 index 0000000..1c1a7cd --- /dev/null +++ b/include/configs/sun8i.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2014 Chen-Yu Tsai wens@csie.org + * + * Configuration settings for the Allwinner A23 (sun8i) CPU + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * A23 specific configuration + */ +#define CONFIG_SUN8I /* sun8i SoC generation */ +#define CONFIG_SYS_PROMPT "sun8i# " + +/* + * Include common sunxi configuration where most the settings are + */ +#include <configs/sunxi-common.h> + +#endif /* __CONFIG_H */
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup.
Do I take it that sun8i is also in the same position wrt DRAM bring up code not existing yet and there therefore being no SPL yet?
Signed-off-by: Chen-Yu Tsai wens@csie.org
arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv7/sunxi/Makefile | 2 ++ arch/arm/cpu/armv7/sunxi/board.c | 3 ++- arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++ arch/arm/include/asm/arch-sunxi/clock.h | 2 +- board/sunxi/Kconfig | 9 ++++++++- include/configs/sun8i.h | 23 +++++++++++++++++++++++ 7 files changed, 41 insertions(+), 3 deletions(-) create mode 100644 include/configs/sun8i.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e3e7e78..cb691b2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -450,6 +450,9 @@ config TARGET_SUN6I config TARGET_SUN7I bool "Support sun7i"
+config TARGET_SUN8I
- bool "Support sun8i"
config TARGET_SNOWBALL bool "Support snowball"
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 2a42dca..24f1dae 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -12,10 +12,12 @@ obj-y += board.o obj-y += clock.o obj-y += pinmux.o obj-$(CONFIG_SUN6I) += prcm.o +obj-$(CONFIG_SUN8I) += prcm.o obj-$(CONFIG_SUN4I) += clock_sun4i.o obj-$(CONFIG_SUN5I) += clock_sun4i.o obj-$(CONFIG_SUN6I) += clock_sun6i.o obj-$(CONFIG_SUN7I) += clock_sun4i.o +obj-$(CONFIG_SUN8I) += clock_sun6i.o
ifndef CONFIG_SPL_BUILD obj-y += cpu_info.o diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 29d45b6..61c1ba9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -100,7 +100,8 @@ void reset_cpu(ulong addr) /* do some early init */ void s_init(void) { -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I) +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \
defined CONFIG_SUN6I || defined CONFIG_SUN8I)
At some point we should refactor this to use a common Kconfig thing (SUNXI_SMP etc) which the relevant targets select.
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n" diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index 40c4e13..4f2a09c 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -27,6 +27,8 @@ int print_cpuinfo(void) puts("CPU: Allwinner A31 (SUN6I)\n"); #elif defined CONFIG_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); +#elif defined CONFIG_SUN8I
- puts("CPU: Allwinner A23 (SUN8I)\n");
#else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 8f5d860..012c2af 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -15,7 +15,7 @@ #define CLK_GATE_CLOSE 0x0
/* clock control module regs definition */ -#ifdef CONFIG_SUN6I +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) #include <asm/arch/clock_sun6i.h> #else #include <asm/arch/clock_sun4i.h> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 05defac..16f6db4 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -27,7 +27,14 @@ config SYS_CONFIG_NAME
endif
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I +if TARGET_SUN8I
+config SYS_CONFIG_NAME
- default "sun8i"
+endif
+if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I || TARGET_SUN8I
config SYS_CPU default "armv7" diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h new file mode 100644 index 0000000..1c1a7cd --- /dev/null +++ b/include/configs/sun8i.h @@ -0,0 +1,23 @@ +/*
- (C) Copyright 2014 Chen-Yu Tsai wens@csie.org
- Configuration settings for the Allwinner A23 (sun8i) CPU
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+/*
- A23 specific configuration
- */
+#define CONFIG_SUN8I /* sun8i SoC generation */ +#define CONFIG_SYS_PROMPT "sun8i# "
+/*
- Include common sunxi configuration where most the settings are
- */
+#include <configs/sunxi-common.h>
+#endif /* __CONFIG_H */
On Sat, Oct 11, 2014 at 11:58 PM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup.
Do I take it that sun8i is also in the same position wrt DRAM bring up code not existing yet and there therefore being no SPL yet?
That is correct.
Signed-off-by: Chen-Yu Tsai wens@csie.org
arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv7/sunxi/Makefile | 2 ++ arch/arm/cpu/armv7/sunxi/board.c | 3 ++- arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++ arch/arm/include/asm/arch-sunxi/clock.h | 2 +- board/sunxi/Kconfig | 9 ++++++++- include/configs/sun8i.h | 23 +++++++++++++++++++++++ 7 files changed, 41 insertions(+), 3 deletions(-) create mode 100644 include/configs/sun8i.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e3e7e78..cb691b2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -450,6 +450,9 @@ config TARGET_SUN6I config TARGET_SUN7I bool "Support sun7i"
+config TARGET_SUN8I
bool "Support sun8i"config TARGET_SNOWBALL bool "Support snowball"
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 2a42dca..24f1dae 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -12,10 +12,12 @@ obj-y += board.o obj-y += clock.o obj-y += pinmux.o obj-$(CONFIG_SUN6I) += prcm.o +obj-$(CONFIG_SUN8I) += prcm.o obj-$(CONFIG_SUN4I) += clock_sun4i.o obj-$(CONFIG_SUN5I) += clock_sun4i.o obj-$(CONFIG_SUN6I) += clock_sun6i.o obj-$(CONFIG_SUN7I) += clock_sun4i.o +obj-$(CONFIG_SUN8I) += clock_sun6i.o
ifndef CONFIG_SPL_BUILD obj-y += cpu_info.o diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 29d45b6..61c1ba9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -100,7 +100,8 @@ void reset_cpu(ulong addr) /* do some early init */ void s_init(void) { -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I) +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \
defined CONFIG_SUN6I || defined CONFIG_SUN8I)At some point we should refactor this to use a common Kconfig thing (SUNXI_SMP etc) which the relevant targets select.
I agree. We can do this as we move further to Kconfig.
ChenYu
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n"diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index 40c4e13..4f2a09c 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -27,6 +27,8 @@ int print_cpuinfo(void) puts("CPU: Allwinner A31 (SUN6I)\n"); #elif defined CONFIG_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); +#elif defined CONFIG_SUN8I
puts("CPU: Allwinner A23 (SUN8I)\n");#else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 8f5d860..012c2af 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -15,7 +15,7 @@ #define CLK_GATE_CLOSE 0x0
/* clock control module regs definition */ -#ifdef CONFIG_SUN6I +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) #include <asm/arch/clock_sun6i.h> #else #include <asm/arch/clock_sun4i.h> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 05defac..16f6db4 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -27,7 +27,14 @@ config SYS_CONFIG_NAME
endif
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I +if TARGET_SUN8I
+config SYS_CONFIG_NAME
default "sun8i"+endif
+if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I || TARGET_SUN8I
config SYS_CPU default "armv7" diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h new file mode 100644 index 0000000..1c1a7cd --- /dev/null +++ b/include/configs/sun8i.h @@ -0,0 +1,23 @@ +/*
- (C) Copyright 2014 Chen-Yu Tsai wens@csie.org
- Configuration settings for the Allwinner A23 (sun8i) CPU
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+/*
- A23 specific configuration
- */
+#define CONFIG_SUN8I /* sun8i SoC generation */ +#define CONFIG_SYS_PROMPT "sun8i# "
+/*
- Include common sunxi configuration where most the settings are
- */
+#include <configs/sunxi-common.h>
+#endif /* __CONFIG_H */
On Sun, 2014-10-12 at 10:43 +0800, Chen-Yu Tsai wrote:
On Sat, Oct 11, 2014 at 11:58 PM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The basic blocks of the A23 are similar to the A31 (sun6i). Re-use sun6i code for initial clock, gpio, and uart setup.
Do I take it that sun8i is also in the same position wrt DRAM bring up code not existing yet and there therefore being no SPL yet?
That is correct.
Please could you add a sentence to the commit message.
Apart from that: Acked-by: Ian Campbell ijc@hellion.org.uk
Signed-off-by: Chen-Yu Tsai wens@csie.org
arch/arm/Kconfig | 3 +++ arch/arm/cpu/armv7/sunxi/Makefile | 2 ++ arch/arm/cpu/armv7/sunxi/board.c | 3 ++- arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++ arch/arm/include/asm/arch-sunxi/clock.h | 2 +- board/sunxi/Kconfig | 9 ++++++++- include/configs/sun8i.h | 23 +++++++++++++++++++++++ 7 files changed, 41 insertions(+), 3 deletions(-) create mode 100644 include/configs/sun8i.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e3e7e78..cb691b2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -450,6 +450,9 @@ config TARGET_SUN6I config TARGET_SUN7I bool "Support sun7i"
+config TARGET_SUN8I
bool "Support sun8i"config TARGET_SNOWBALL bool "Support snowball"
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 2a42dca..24f1dae 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -12,10 +12,12 @@ obj-y += board.o obj-y += clock.o obj-y += pinmux.o obj-$(CONFIG_SUN6I) += prcm.o +obj-$(CONFIG_SUN8I) += prcm.o obj-$(CONFIG_SUN4I) += clock_sun4i.o obj-$(CONFIG_SUN5I) += clock_sun4i.o obj-$(CONFIG_SUN6I) += clock_sun6i.o obj-$(CONFIG_SUN7I) += clock_sun4i.o +obj-$(CONFIG_SUN8I) += clock_sun6i.o
ifndef CONFIG_SPL_BUILD obj-y += cpu_info.o diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 29d45b6..61c1ba9 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -100,7 +100,8 @@ void reset_cpu(ulong addr) /* do some early init */ void s_init(void) { -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I) +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || \
defined CONFIG_SUN6I || defined CONFIG_SUN8I)At some point we should refactor this to use a common Kconfig thing (SUNXI_SMP etc) which the relevant targets select.
I agree. We can do this as we move further to Kconfig.
ChenYu
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ asm volatile( "mrc p15, 0, r0, c1, c0, 1\n"diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c index 40c4e13..4f2a09c 100644 --- a/arch/arm/cpu/armv7/sunxi/cpu_info.c +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -27,6 +27,8 @@ int print_cpuinfo(void) puts("CPU: Allwinner A31 (SUN6I)\n"); #elif defined CONFIG_SUN7I puts("CPU: Allwinner A20 (SUN7I)\n"); +#elif defined CONFIG_SUN8I
puts("CPU: Allwinner A23 (SUN8I)\n");#else #warning Please update cpu_info.c with correct CPU information puts("CPU: SUNXI Family\n"); diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 8f5d860..012c2af 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -15,7 +15,7 @@ #define CLK_GATE_CLOSE 0x0
/* clock control module regs definition */ -#ifdef CONFIG_SUN6I +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) #include <asm/arch/clock_sun6i.h> #else #include <asm/arch/clock_sun4i.h> diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 05defac..16f6db4 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -27,7 +27,14 @@ config SYS_CONFIG_NAME
endif
-if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I +if TARGET_SUN8I
+config SYS_CONFIG_NAME
default "sun8i"+endif
+if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I || TARGET_SUN8I
config SYS_CPU default "armv7" diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h new file mode 100644 index 0000000..1c1a7cd --- /dev/null +++ b/include/configs/sun8i.h @@ -0,0 +1,23 @@ +/*
- (C) Copyright 2014 Chen-Yu Tsai wens@csie.org
- Configuration settings for the Allwinner A23 (sun8i) CPU
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+/*
- A23 specific configuration
- */
+#define CONFIG_SUN8I /* sun8i SoC generation */ +#define CONFIG_SYS_PROMPT "sun8i# "
+/*
- Include common sunxi configuration where most the settings are
- */
+#include <configs/sunxi-common.h>
+#endif /* __CONFIG_H */
From: Hans de Goede hdegoede@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.
Signed-off-by: Hans de Goede hdegoede@redhat.com [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/include/asm/arch-sunxi/gpio.h | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index b94ec4d..bbe815a 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -10,6 +10,7 @@ #define _SUNXI_GPIO_H
#include <linux/types.h> +#include <asm/arch/cpu.h>
/* * sunxi has 9 banks of gpio, they are: @@ -29,6 +30,19 @@ #define SUNXI_GPIO_I 8 #define SUNXI_GPIO_BANKS 9
+/* + * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) + * at a different register offset. + * + * sun6i has 2 banks: + * PL0 - PL8 | PM0 - PM7 + * + * sun8i has 1 bank: + * PL0 - PL11 + */ +#define SUNXI_GPIO_L 9 +#define SUNXI_GPIO_M 10 + struct sunxi_gpio { u32 cfg[4]; u32 dat; @@ -50,8 +64,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; };
-#define BANK_TO_GPIO(bank) \ - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] +#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_BANKS) ? \ + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ + &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_BANKS])
#define GPIO_BANK(pin) ((pin) >> 5) #define GPIO_NUM(pin) ((pin) & 0x1f) @@ -75,6 +90,8 @@ struct sunxi_gpio_reg { #define SUNXI_GPIO_G_NR 32 #define SUNXI_GPIO_H_NR 32 #define SUNXI_GPIO_I_NR 32 +#define SUNXI_GPIO_L_NR 32 +#define SUNXI_GPIO_M_NR 32
#define SUNXI_GPIO_NEXT(__gpio) \ ((__gpio##_START) + (__gpio##_NR) + 0) @@ -89,6 +106,8 @@ enum sunxi_gpio_number { SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), + SUNXI_GPIO_L_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_I), + SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), };
/* SUNXI GPIO number definitions */ @@ -101,6 +120,8 @@ enum sunxi_gpio_number { #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
/* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdegoede@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.
Does it also have enough space for 9 banks? Since you overlay a struct sunxi_gpio_reg on it which has a gpio_bank[SUNXI_GPIO_BANKS] over it.
SUNXI_GPIO_BANKS is now also confusingly named since it is really "number of banks on the first/original GPIO controller". Eventually someone will use it as the actual total and be very sad.
I think it might be best if we retcon some distinct name onto the original GPIO controller so we can have SUNXIO_GPIO_BLA_BANKS and SUNXI_GPIO_R_BANKS (or even just call them controller 0 and 1 and have SUNXI_GPIO0_BANKS and SUNXI_GPIO1_BANKS, if that's not too confusing)
If we still need SUNXI_GPIO_BANKS after that then it would be the sum of those two.
Signed-off-by: Hans de Goede hdegoede@redhat.com [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] Signed-off-by: Chen-Yu Tsai wens@csie.org
arch/arm/include/asm/arch-sunxi/gpio.h | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index b94ec4d..bbe815a 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -10,6 +10,7 @@ #define _SUNXI_GPIO_H
#include <linux/types.h> +#include <asm/arch/cpu.h>
/*
- sunxi has 9 banks of gpio, they are:
@@ -29,6 +30,19 @@ #define SUNXI_GPIO_I 8 #define SUNXI_GPIO_BANKS 9
+/*
- sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
- at a different register offset.
- sun6i has 2 banks:
- PL0 - PL8 | PM0 - PM7
- sun8i has 1 bank:
- PL0 - PL11
- */
+#define SUNXI_GPIO_L 9 +#define SUNXI_GPIO_M 10
struct sunxi_gpio { u32 cfg[4]; u32 dat; @@ -50,8 +64,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; };
-#define BANK_TO_GPIO(bank) \
- &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]
+#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_BANKS) ? \
- &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
- &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_BANKS])
#define GPIO_BANK(pin) ((pin) >> 5) #define GPIO_NUM(pin) ((pin) & 0x1f) @@ -75,6 +90,8 @@ struct sunxi_gpio_reg { #define SUNXI_GPIO_G_NR 32 #define SUNXI_GPIO_H_NR 32 #define SUNXI_GPIO_I_NR 32 +#define SUNXI_GPIO_L_NR 32 +#define SUNXI_GPIO_M_NR 32
#define SUNXI_GPIO_NEXT(__gpio) \ ((__gpio##_START) + (__gpio##_NR) + 0) @@ -89,6 +106,8 @@ enum sunxi_gpio_number { SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
- SUNXI_GPIO_L_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_I),
- SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),
};
/* SUNXI GPIO number definitions */ @@ -101,6 +120,8 @@ enum sunxi_gpio_number { #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
/* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0
On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdegoede@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.
Does it also have enough space for 9 banks? Since you overlay a struct sunxi_gpio_reg on it which has a gpio_bank[SUNXI_GPIO_BANKS] over it.
Yes it does, as seen in the latest A31 manuals released by Allwinner.
SUNXI_GPIO_BANKS is now also confusingly named since it is really "number of banks on the first/original GPIO controller". Eventually someone will use it as the actual total and be very sad.
I think it might be best if we retcon some distinct name onto the original GPIO controller so we can have SUNXIO_GPIO_BLA_BANKS and SUNXI_GPIO_R_BANKS (or even just call them controller 0 and 1 and have SUNXI_GPIO0_BANKS and SUNXI_GPIO1_BANKS, if that's not too confusing)
The latest manuals have "CPUx-PORT" and "CPUs-PORT" for the respective chapters. I'm guessing "x" is for 0~3 cores, and s is for standby or something.
Of course it's also confusing that Allwinner's sources use the "R_" prefix for all hardware in that address range, while the datasheet lists the GPIO function names as "s_something".
We might want to make sure the naming is consistent with the kernel as well. (+CC Maxime)
ChenYu
If we still need SUNXI_GPIO_BANKS after that then it would be the sum of those two.
Signed-off-by: Hans de Goede hdegoede@redhat.com [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] Signed-off-by: Chen-Yu Tsai wens@csie.org
arch/arm/include/asm/arch-sunxi/gpio.h | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index b94ec4d..bbe815a 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -10,6 +10,7 @@ #define _SUNXI_GPIO_H
#include <linux/types.h> +#include <asm/arch/cpu.h>
/*
- sunxi has 9 banks of gpio, they are:
@@ -29,6 +30,19 @@ #define SUNXI_GPIO_I 8 #define SUNXI_GPIO_BANKS 9
+/*
- sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
- at a different register offset.
- sun6i has 2 banks:
- PL0 - PL8 | PM0 - PM7
- sun8i has 1 bank:
- PL0 - PL11
- */
+#define SUNXI_GPIO_L 9 +#define SUNXI_GPIO_M 10
struct sunxi_gpio { u32 cfg[4]; u32 dat; @@ -50,8 +64,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; };
-#define BANK_TO_GPIO(bank) \
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]+#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_BANKS) ? \
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_BANKS])#define GPIO_BANK(pin) ((pin) >> 5) #define GPIO_NUM(pin) ((pin) & 0x1f) @@ -75,6 +90,8 @@ struct sunxi_gpio_reg { #define SUNXI_GPIO_G_NR 32 #define SUNXI_GPIO_H_NR 32 #define SUNXI_GPIO_I_NR 32 +#define SUNXI_GPIO_L_NR 32 +#define SUNXI_GPIO_M_NR 32
#define SUNXI_GPIO_NEXT(__gpio) \ ((__gpio##_START) + (__gpio##_NR) + 0) @@ -89,6 +106,8 @@ enum sunxi_gpio_number { SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
SUNXI_GPIO_L_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_I),SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),};
/* SUNXI GPIO number definitions */ @@ -101,6 +120,8 @@ enum sunxi_gpio_number { #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
/* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0
On Sun, 2014-10-12 at 16:23 +0800, Chen-Yu Tsai wrote:
On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdegoede@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.
Does it also have enough space for 9 banks? Since you overlay a struct sunxi_gpio_reg on it which has a gpio_bank[SUNXI_GPIO_BANKS] over it.
Yes it does, as seen in the latest A31 manuals released by Allwinner.
SUNXI_GPIO_BANKS is now also confusingly named since it is really "number of banks on the first/original GPIO controller". Eventually someone will use it as the actual total and be very sad.
I think it might be best if we retcon some distinct name onto the original GPIO controller so we can have SUNXIO_GPIO_BLA_BANKS and SUNXI_GPIO_R_BANKS (or even just call them controller 0 and 1 and have SUNXI_GPIO0_BANKS and SUNXI_GPIO1_BANKS, if that's not too confusing)
The latest manuals have "CPUx-PORT" and "CPUs-PORT" for the respective chapters. I'm guessing "x" is for 0~3 cores, and s is for standby or something.
Of course it's also confusing that Allwinner's sources use the "R_" prefix for all hardware in that address range, while the datasheet lists the GPIO function names as "s_something".
We might want to make sure the naming is consistent with the kernel as well. (+CC Maxime)
Good idea, last thing we want to do is introduce yet another "standard" ;-)
ChenYu
If we still need SUNXI_GPIO_BANKS after that then it would be the sum of those two.
Signed-off-by: Hans de Goede hdegoede@redhat.com [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] Signed-off-by: Chen-Yu Tsai wens@csie.org
arch/arm/include/asm/arch-sunxi/gpio.h | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index b94ec4d..bbe815a 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -10,6 +10,7 @@ #define _SUNXI_GPIO_H
#include <linux/types.h> +#include <asm/arch/cpu.h>
/*
- sunxi has 9 banks of gpio, they are:
@@ -29,6 +30,19 @@ #define SUNXI_GPIO_I 8 #define SUNXI_GPIO_BANKS 9
+/*
- sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO)
- at a different register offset.
- sun6i has 2 banks:
- PL0 - PL8 | PM0 - PM7
- sun8i has 1 bank:
- PL0 - PL11
- */
+#define SUNXI_GPIO_L 9 +#define SUNXI_GPIO_M 10
struct sunxi_gpio { u32 cfg[4]; u32 dat; @@ -50,8 +64,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; };
-#define BANK_TO_GPIO(bank) \
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]+#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_BANKS) ? \
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_BANKS])#define GPIO_BANK(pin) ((pin) >> 5) #define GPIO_NUM(pin) ((pin) & 0x1f) @@ -75,6 +90,8 @@ struct sunxi_gpio_reg { #define SUNXI_GPIO_G_NR 32 #define SUNXI_GPIO_H_NR 32 #define SUNXI_GPIO_I_NR 32 +#define SUNXI_GPIO_L_NR 32 +#define SUNXI_GPIO_M_NR 32
#define SUNXI_GPIO_NEXT(__gpio) \ ((__gpio##_START) + (__gpio##_NR) + 0) @@ -89,6 +106,8 @@ enum sunxi_gpio_number { SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
SUNXI_GPIO_L_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_I),SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L),};
/* SUNXI GPIO number definitions */ @@ -101,6 +120,8 @@ enum sunxi_gpio_number { #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr))
/* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0
On Sun, Oct 12, 2014 at 04:23:05PM +0800, Chen-Yu Tsai wrote:
On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdegoede@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.
Does it also have enough space for 9 banks? Since you overlay a struct sunxi_gpio_reg on it which has a gpio_bank[SUNXI_GPIO_BANKS] over it.
Yes it does, as seen in the latest A31 manuals released by Allwinner.
SUNXI_GPIO_BANKS is now also confusingly named since it is really "number of banks on the first/original GPIO controller". Eventually someone will use it as the actual total and be very sad.
I think it might be best if we retcon some distinct name onto the original GPIO controller so we can have SUNXIO_GPIO_BLA_BANKS and SUNXI_GPIO_R_BANKS (or even just call them controller 0 and 1 and have SUNXI_GPIO0_BANKS and SUNXI_GPIO1_BANKS, if that's not too confusing)
The latest manuals have "CPUx-PORT" and "CPUs-PORT" for the respective chapters. I'm guessing "x" is for 0~3 cores, and s is for standby or something.
iirc, it was meant for "special".
Of course it's also confusing that Allwinner's sources use the "R_" prefix for all hardware in that address range, while the datasheet lists the GPIO function names as "s_something".
We use the same pin convention than in the datasheet in mainline (but starting from PL for the special pins). And it's true that we do prefix all the functions by s_, once again, just like the datasheet does.
The fact that it comes from a different controller is only expressed by where the pinctrl pins node is defined in the DT.
Maxime
Hi Ian,
On Mon, Oct 13, 2014 at 8:57 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Oct 12, 2014 at 04:23:05PM +0800, Chen-Yu Tsai wrote:
On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdegoede@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.
Does it also have enough space for 9 banks? Since you overlay a struct sunxi_gpio_reg on it which has a gpio_bank[SUNXI_GPIO_BANKS] over it.
Yes it does, as seen in the latest A31 manuals released by Allwinner.
SUNXI_GPIO_BANKS is now also confusingly named since it is really "number of banks on the first/original GPIO controller". Eventually someone will use it as the actual total and be very sad.
I think it might be best if we retcon some distinct name onto the original GPIO controller so we can have SUNXIO_GPIO_BLA_BANKS and SUNXI_GPIO_R_BANKS (or even just call them controller 0 and 1 and have SUNXI_GPIO0_BANKS and SUNXI_GPIO1_BANKS, if that's not too confusing)
The latest manuals have "CPUx-PORT" and "CPUs-PORT" for the respective chapters. I'm guessing "x" is for 0~3 cores, and s is for standby or something.
iirc, it was meant for "special".
I'd like to keep it as SUNXI_GPIO_BANKS if possible. The GPIO and R_GPIO prefixes match what we see in Allwinner's sources and what we use in the mainline kernel.
The comment section above it could be made clearer about it.
Also that number would be bumped up for A80, which has pin bank J. I will change some of the R_PIO code to check/use the starting pin bank L number instead of checking against SUNXI_GPIO_BANKS. Wonder why I didn't do it before...
Of course it's also confusing that Allwinner's sources use the "R_" prefix for all hardware in that address range, while the datasheet lists the GPIO function names as "s_something".
We use the same pin convention than in the datasheet in mainline (but starting from PL for the special pins). And it's true that we do prefix all the functions by s_, once again, just like the datasheet does.
The fact that it comes from a different controller is only expressed by where the pinctrl pins node is defined in the DT.
I'm a bit undecided about how we should name the pin definitions. In the kernel, we named the function s_uart, but the pinconf node r_uart.
In u-boot there isn't this separation. I'm wondering which would be easier to understand and relate to the underlying peripheral. At the moment I prefer R_UART.
ChenYu
On Fri, 2014-10-17 at 22:48 +0800, Chen-Yu Tsai wrote:
Hi Ian,
On Mon, Oct 13, 2014 at 8:57 PM, Maxime Ripard maxime.ripard@free-electrons.com wrote:
On Sun, Oct 12, 2014 at 04:23:05PM +0800, Chen-Yu Tsai wrote:
On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdegoede@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.
Does it also have enough space for 9 banks? Since you overlay a struct sunxi_gpio_reg on it which has a gpio_bank[SUNXI_GPIO_BANKS] over it.
Yes it does, as seen in the latest A31 manuals released by Allwinner.
SUNXI_GPIO_BANKS is now also confusingly named since it is really "number of banks on the first/original GPIO controller". Eventually someone will use it as the actual total and be very sad.
I think it might be best if we retcon some distinct name onto the original GPIO controller so we can have SUNXIO_GPIO_BLA_BANKS and SUNXI_GPIO_R_BANKS (or even just call them controller 0 and 1 and have SUNXI_GPIO0_BANKS and SUNXI_GPIO1_BANKS, if that's not too confusing)
The latest manuals have "CPUx-PORT" and "CPUs-PORT" for the respective chapters. I'm guessing "x" is for 0~3 cores, and s is for standby or something.
iirc, it was meant for "special".
I'd like to keep it as SUNXI_GPIO_BANKS if possible. The GPIO and R_GPIO prefixes match what we see in Allwinner's sources and what we use in the mainline kernel.
OK, matching the mainline kernel is a sound plan.
The comment section above it could be made clearer about it.
Also that number would be bumped up for A80, which has pin bank J. I will change some of the R_PIO code to check/use the starting pin bank L number instead of checking against SUNXI_GPIO_BANKS. Wonder why I didn't do it before...
Sounds good.
Of course it's also confusing that Allwinner's sources use the "R_" prefix for all hardware in that address range, while the datasheet lists the GPIO function names as "s_something".
We use the same pin convention than in the datasheet in mainline (but starting from PL for the special pins). And it's true that we do prefix all the functions by s_, once again, just like the datasheet does.
The fact that it comes from a different controller is only expressed by where the pinctrl pins node is defined in the DT.
I'm a bit undecided about how we should name the pin definitions. In the kernel, we named the function s_uart, but the pinconf node r_uart.
In u-boot there isn't this separation. I'm wondering which would be easier to understand and relate to the underlying peripheral. At the moment I prefer R_UART.
Either is fine for me.
Ian.
The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be reused.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/cpu/armv7/sunxi/prcm.c | 12 +++++++----- arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- 2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c index 7b3ee89..19b4938 100644 --- a/arch/arm/cpu/armv7/sunxi/prcm.c +++ b/arch/arm/cpu/armv7/sunxi/prcm.c @@ -21,13 +21,15 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h>
-void prcm_init_apb0(void) +/* APB0 clock gate and reset bit offsets are the same. */ +void prcm_apb0_enable(u32 flags) { struct sunxi_prcm_reg *prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- setbits_le32(&prcm->apb0_gate, PRCM_APB0_GATE_P2WI | - PRCM_APB0_GATE_PIO); - setbits_le32(&prcm->apb0_reset, PRCM_APB0_RESET_P2WI | - PRCM_APB0_RESET_PIO); + /* open the clock for module */ + setbits_le32(&prcm->apb0_gate, flags); + + /* deassert reset for module */ + setbits_le32(&prcm->apb0_reset, flags); } diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 1b40f09..3d3bfa6 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -233,6 +233,6 @@ struct sunxi_prcm_reg { u32 dram_tst; /* 0x190 */ };
-void prcm_init_apb0(void); +void prcm_apb0_enable(u32 flags); #endif /* __ASSEMBLY__ */ #endif /* _PRCM_H */
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be reused.
How come this isn't actually called on sun6i?
(naughty of me not to notice this when it was submitted!)
Is it going to be called by anything in this series? I have a feeling this is a precursor for SPL which should have been left out of the sun6i series, but oh well what's done is done.
Without a caller it's hard to make a judgement call on parameters vs #ifdef in the function, although my inclination would generally be towards parameters, if there's just going to be an ifdef at the call site instead it's not really buying us much.
Signed-off-by: Chen-Yu Tsai wens@csie.org
arch/arm/cpu/armv7/sunxi/prcm.c | 12 +++++++----- arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- 2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c index 7b3ee89..19b4938 100644 --- a/arch/arm/cpu/armv7/sunxi/prcm.c +++ b/arch/arm/cpu/armv7/sunxi/prcm.c @@ -21,13 +21,15 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h>
-void prcm_init_apb0(void) +/* APB0 clock gate and reset bit offsets are the same. */
Is this absolutely guaranteed?
+void prcm_apb0_enable(u32 flags) { struct sunxi_prcm_reg *prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- setbits_le32(&prcm->apb0_gate, PRCM_APB0_GATE_P2WI |
PRCM_APB0_GATE_PIO);- setbits_le32(&prcm->apb0_reset, PRCM_APB0_RESET_P2WI |
PRCM_APB0_RESET_PIO);
- /* open the clock for module */
- setbits_le32(&prcm->apb0_gate, flags);
- /* deassert reset for module */
- setbits_le32(&prcm->apb0_reset, flags);
} diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 1b40f09..3d3bfa6 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -233,6 +233,6 @@ struct sunxi_prcm_reg { u32 dram_tst; /* 0x190 */ };
-void prcm_init_apb0(void); +void prcm_apb0_enable(u32 flags); #endif /* __ASSEMBLY__ */ #endif /* _PRCM_H */
On Sat, 2014-10-11 at 17:11 +0100, Ian Campbell wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be reused.
How come this isn't actually called on sun6i?
(naughty of me not to notice this when it was submitted!)
Is it going to be called by anything in this series? I have a feeling this is a precursor for SPL which should have been left out of the sun6i series, but oh well what's done is done.
Without a caller it's hard to make a judgement call on parameters vs #ifdef in the function, although my inclination would generally be towards parameters, if there's just going to be an ifdef at the call site instead it's not really buying us much.
I should have read the next patch more carefully before commenting...
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Ian Campbell ijc@hellion.org.uk
arch/arm/cpu/armv7/sunxi/prcm.c | 12 +++++++----- arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- 2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c index 7b3ee89..19b4938 100644 --- a/arch/arm/cpu/armv7/sunxi/prcm.c +++ b/arch/arm/cpu/armv7/sunxi/prcm.c @@ -21,13 +21,15 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h>
-void prcm_init_apb0(void) +/* APB0 clock gate and reset bit offsets are the same. */
Is this absolutely guaranteed?
+void prcm_apb0_enable(u32 flags) { struct sunxi_prcm_reg *prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- setbits_le32(&prcm->apb0_gate, PRCM_APB0_GATE_P2WI |
PRCM_APB0_GATE_PIO);- setbits_le32(&prcm->apb0_reset, PRCM_APB0_RESET_P2WI |
PRCM_APB0_RESET_PIO);
- /* open the clock for module */
- setbits_le32(&prcm->apb0_gate, flags);
- /* deassert reset for module */
- setbits_le32(&prcm->apb0_reset, flags);
} diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 1b40f09..3d3bfa6 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -233,6 +233,6 @@ struct sunxi_prcm_reg { u32 dram_tst; /* 0x190 */ };
-void prcm_init_apb0(void); +void prcm_apb0_enable(u32 flags); #endif /* __ASSEMBLY__ */ #endif /* _PRCM_H */
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On Sun, Oct 12, 2014 at 12:13 AM, Ian Campbell ijc@hellion.org.uk wrote:
On Sat, 2014-10-11 at 17:11 +0100, Ian Campbell wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The prcm apb0 controls multiple modules. Allow specifying which modules to enable clocks and de-assert resets so the function can be reused.
How come this isn't actually called on sun6i?
(naughty of me not to notice this when it was submitted!)
Is it going to be called by anything in this series? I have a feeling this is a precursor for SPL which should have been left out of the sun6i series, but oh well what's done is done.
This will be used by P2WI and PMIC stuff. (series WiP)
Without a caller it's hard to make a judgement call on parameters vs #ifdef in the function, although my inclination would generally be towards parameters, if there's just going to be an ifdef at the call site instead it's not really buying us much.
I should have read the next patch more carefully before commenting...
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Ian Campbell ijc@hellion.org.uk
Thanks.
arch/arm/cpu/armv7/sunxi/prcm.c | 12 +++++++----- arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- 2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/prcm.c b/arch/arm/cpu/armv7/sunxi/prcm.c index 7b3ee89..19b4938 100644 --- a/arch/arm/cpu/armv7/sunxi/prcm.c +++ b/arch/arm/cpu/armv7/sunxi/prcm.c @@ -21,13 +21,15 @@ #include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h>
-void prcm_init_apb0(void) +/* APB0 clock gate and reset bit offsets are the same. */
Is this absolutely guaranteed?
+void prcm_apb0_enable(u32 flags) { struct sunxi_prcm_reg *prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
- setbits_le32(&prcm->apb0_gate, PRCM_APB0_GATE_P2WI |
PRCM_APB0_GATE_PIO);- setbits_le32(&prcm->apb0_reset, PRCM_APB0_RESET_P2WI |
PRCM_APB0_RESET_PIO);
- /* open the clock for module */
- setbits_le32(&prcm->apb0_gate, flags);
- /* deassert reset for module */
- setbits_le32(&prcm->apb0_reset, flags);
} diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 1b40f09..3d3bfa6 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -233,6 +233,6 @@ struct sunxi_prcm_reg { u32 dram_tst; /* 0x190 */ };
-void prcm_init_apb0(void); +void prcm_apb0_enable(u32 flags); #endif /* __ASSEMBLY__ */ #endif /* _PRCM_H */
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
The A23 only has UART0 muxed with MMC0. Some of the boards we encountered expose R_UART as a set of pads.
Add support for R_UART so we can have a console while using mmc.
Signed-off-by: Chen-Yu Tsai wens@csie.org --- arch/arm/cpu/armv7/sunxi/board.c | 4 ++++ arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 ++++++ arch/arm/include/asm/arch-sunxi/cpu.h | 1 + arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ include/configs/sunxi-common.h | 1 + 5 files changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 61c1ba9..aeb2c2f 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -75,6 +75,10 @@ int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I) + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX); + sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP); #else #error Unsupported console port number. Please fix pin mux settings in board.c #endif diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 8387b93..1eae976 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -13,6 +13,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h>
void clock_init_uart(void) @@ -20,6 +21,7 @@ void clock_init_uart(void) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#if CONFIG_CONS_INDEX < 5 /* uart clock source is apb2 */ writel(APB2_CLK_SRC_OSC24M| APB2_CLK_RATE_N_1| @@ -35,6 +37,10 @@ void clock_init_uart(void) setbits_le32(&ccm->apb2_reset_cfg, 1 << (APB2_RESET_UART_SHIFT + CONFIG_CONS_INDEX - 1)); +#else + /* enable R_PIO and R_UART clocks, and de-assert resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); +#endif
/* Dup with clock_init_safe(), drop once sun6i SPL support lands */ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 313e6c8..0de79a0 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -111,6 +111,7 @@ #define SUNXI_AVG_BASE 0x01ea0000
#define SUNXI_PRCM_BASE 0x01f01400 +#define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 #define SUNXI_P2WI_BASE 0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index bbe815a..c216960 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -164,6 +164,9 @@ enum sunxi_gpio_number {
#define SUN4I_GPI4_SDC3 2
+#define SUN8I_GPL2_R_UART_TX 2 +#define SUN8I_GPL3_R_UART_RX 2 + /* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 #define SUNXI_GPIO_PULL_UP 1 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 7857a56..7e54296 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -42,6 +42,7 @@ #define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE #define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE #define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE +#define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
/* DRAM Base */ #define CONFIG_SYS_SDRAM_BASE 0x40000000
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
The A23 only has UART0 muxed with MMC0. Some of the boards we encountered expose R_UART as a set of pads.
Add support for R_UART so we can have a console while using mmc.
I suppose R_UART is the h/w doc name. UARTR would fit the code better but I suppose sticking with the h/w names is fine.
CONFIG_CONS_INDEX is also getting a bit out of hand, eventually we should make it a Kconfig choice option.
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Ian Campbell ijc@hellion.org.uk
arch/arm/cpu/armv7/sunxi/board.c | 4 ++++ arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 6 ++++++ arch/arm/include/asm/arch-sunxi/cpu.h | 1 + arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++ include/configs/sunxi-common.h | 1 + 5 files changed, 15 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 61c1ba9..aeb2c2f 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -75,6 +75,10 @@ int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX); sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX); sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
- sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
- sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else #error Unsupported console port number. Please fix pin mux settings in board.c #endif diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index 8387b93..1eae976 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -13,6 +13,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/prcm.h> #include <asm/arch/sys_proto.h>
void clock_init_uart(void) @@ -20,6 +21,7 @@ void clock_init_uart(void) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#if CONFIG_CONS_INDEX < 5 /* uart clock source is apb2 */ writel(APB2_CLK_SRC_OSC24M| APB2_CLK_RATE_N_1| @@ -35,6 +37,10 @@ void clock_init_uart(void) setbits_le32(&ccm->apb2_reset_cfg, 1 << (APB2_RESET_UART_SHIFT + CONFIG_CONS_INDEX - 1)); +#else
- /* enable R_PIO and R_UART clocks, and de-assert resets */
- prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
+#endif
/* Dup with clock_init_safe(), drop once sun6i SPL support lands */ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 313e6c8..0de79a0 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -111,6 +111,7 @@ #define SUNXI_AVG_BASE 0x01ea0000
#define SUNXI_PRCM_BASE 0x01f01400 +#define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 #define SUNXI_P2WI_BASE 0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index bbe815a..c216960 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -164,6 +164,9 @@ enum sunxi_gpio_number {
#define SUN4I_GPI4_SDC3 2
+#define SUN8I_GPL2_R_UART_TX 2 +#define SUN8I_GPL3_R_UART_RX 2
/* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 #define SUNXI_GPIO_PULL_UP 1 diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 7857a56..7e54296 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -42,6 +42,7 @@ #define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE #define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE #define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE +#define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
/* DRAM Base */ #define CONFIG_SYS_SDRAM_BASE 0x40000000
Ippo q8h is a series of A23 tablet boards. This defconfig is for v5 of these boards, though for u-boot purposes they are mostly the same.
See: http://linux-sunxi.org/Ippo_q8h
Signed-off-by: Chen-Yu Tsai wens@csie.org --- board/sunxi/MAINTAINERS | 5 +++++ configs/Ippo_q8h_defconfig | 4 ++++ 2 files changed, 9 insertions(+) create mode 100644 configs/Ippo_q8h_defconfig
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 7afe45e..febd126 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -50,3 +50,8 @@ COLOMBUS BOARD M: Maxime Ripard maxime.ripard@free-electrons.com S: Maintained F: configs/Colombus_defconfig + +IPPO-Q8H-V5 BOARD +M: CHen-Yu Tsai wens@csie.org +S: Maintained +F: configs/Ippo_q8h_v5_defconfig diff --git a/configs/Ippo_q8h_defconfig b/configs/Ippo_q8h_defconfig new file mode 100644 index 0000000..781f137 --- /dev/null +++ b/configs/Ippo_q8h_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="IPPO_Q8H_V5,CONS_INDEX=5" +CONFIG_ARM=y +CONFIG_TARGET_SUN8I=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
Ippo q8h is a series of A23 tablet boards. This defconfig is for v5 of these boards, though for u-boot purposes they are mostly the same.
Any differences worth mentioning?
BTW, this says "The port is then used by the OpenRISC core to dump debug messages. Whether this port can be used by the primary system is still unknown." but your previous patches suggest this is now known?
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Ian Campbell ijc@hellion.org.uk
board/sunxi/MAINTAINERS | 5 +++++ configs/Ippo_q8h_defconfig | 4 ++++ 2 files changed, 9 insertions(+) create mode 100644 configs/Ippo_q8h_defconfig
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 7afe45e..febd126 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -50,3 +50,8 @@ COLOMBUS BOARD M: Maxime Ripard maxime.ripard@free-electrons.com S: Maintained F: configs/Colombus_defconfig
+IPPO-Q8H-V5 BOARD +M: CHen-Yu Tsai wens@csie.org +S: Maintained +F: configs/Ippo_q8h_v5_defconfig diff --git a/configs/Ippo_q8h_defconfig b/configs/Ippo_q8h_defconfig new file mode 100644 index 0000000..781f137 --- /dev/null +++ b/configs/Ippo_q8h_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="IPPO_Q8H_V5,CONS_INDEX=5" +CONFIG_ARM=y +CONFIG_TARGET_SUN8I=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
On Sun, Oct 12, 2014 at 12:17 AM, Ian Campbell ijc@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
Ippo q8h is a series of A23 tablet boards. This defconfig is for v5 of these boards, though for u-boot purposes they are mostly the same.
Any differences worth mentioning?
AFAIK, the boards have different wifi modules, which u-boot doesn't use anyway.
BTW, this says "The port is then used by the OpenRISC core to dump debug messages. Whether this port can be used by the primary system is still unknown." but your previous patches suggest this is now known?
Updated. This was written before I started mainline kernel work.
Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Ian Campbell ijc@hellion.org.uk
Thanks.
board/sunxi/MAINTAINERS | 5 +++++ configs/Ippo_q8h_defconfig | 4 ++++ 2 files changed, 9 insertions(+) create mode 100644 configs/Ippo_q8h_defconfig
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 7afe45e..febd126 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -50,3 +50,8 @@ COLOMBUS BOARD M: Maxime Ripard maxime.ripard@free-electrons.com S: Maintained F: configs/Colombus_defconfig
+IPPO-Q8H-V5 BOARD +M: CHen-Yu Tsai wens@csie.org +S: Maintained +F: configs/Ippo_q8h_v5_defconfig diff --git a/configs/Ippo_q8h_defconfig b/configs/Ippo_q8h_defconfig new file mode 100644 index 0000000..781f137 --- /dev/null +++ b/configs/Ippo_q8h_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="IPPO_Q8H_V5,CONS_INDEX=5" +CONFIG_ARM=y +CONFIG_TARGET_SUN8I=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5.dtb"
participants (4)
-
Chen-Yu Tsai -
Hans de Goede -
Ian Campbell -
Maxime Ripard