[U-Boot] [PATCH 00/11] Add support for booting multiple cores
This patch series introduces changes for booting secondary CPUs on Exynos5420 and Exynos5800.
Akshay Saraswat (10): Exynos542x: Config: Add various configs Exynos542x: CPU: Power down all secondary cores Exynos542x: Add workaround for ARM errata 798870 Exynos542x: Add workaround for ARM errata 799270 Exynos542x: Add workaround for exynos iROM errata Exynos542x: Change ambiguous function name set_l2cache Exynos542x: cache: Disable clean/evict push to external Exynos542x: add L2 control register configuration Exynos542x: Fix secondary core booting for thumb Exynos542x: Make A7s boot with thumb-mode U-Boot on warm reset
Doug Anderson (1): Exynos: Fix L2 cache timings on Exynos5420 and Exynos5800
arch/arm/cpu/armv7/exynos/Makefile | 2 + arch/arm/cpu/armv7/exynos/common_setup.h | 55 +++++++++++ arch/arm/cpu/armv7/exynos/lowlevel_init.c | 159 ++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/exynos/sec_boot.S | 145 +++++++++++++++++++++++++++ arch/arm/cpu/armv7/exynos/soc.c | 35 ------- arch/arm/include/asm/arch-exynos/cpu.h | 30 ++++++ arch/arm/include/asm/arch-exynos/system.h | 90 +++++++++++++++++ include/configs/exynos5-common.h | 28 ++++++ 8 files changed, 509 insertions(+), 35 deletions(-) create mode 100644 arch/arm/cpu/armv7/exynos/sec_boot.S
This patch adds "iRAM, CPU state and low power" configs which are the addresses acting as flag registers.
iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal to CONFIG_LOWPOWER_EN then it jumps to the address (0x02020000+CPUID*4). This is a part of iROM logic. Rest other flags are being used at various places during kernel switching and reset. They are nowhere documented because they are part programming. These configs are serving as flags for us because they are representing the addresses in iRAM which we are using for storing and extracting CPU Status and GIC status.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com --- include/configs/exynos5-common.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ad63f3c..831bfd3 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -231,4 +231,32 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV
+/* iRAM */ +#define CONFIG_PHY_IRAM_BASE 0x02020000 +#define CONFIG_SEC_IRAM_SIZE 0x53000 /* 332KB */ + +#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_PHY_IRAM_BASE \ + + CONFIG_SEC_IRAM_SIZE) + +/* + * Low Power settings + */ +#define CONFIG_LOWPOWER_FLAG 0x02020028 +#define CONFIG_LOWPOWER_ADDR 0x0202002C +#define CONFIG_LOWPOWER_EN 0xc9cfcfcf + +/* + * CPU State Settings + */ +#define CONFIG_CPU_STATE (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x28) +#define CONFIG_GIC_STATE (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x38) + +#define CONFIG_CPU0_STATE (CONFIG_CPU_STATE + 0x0) +#define CONFIG_CPU1_STATE (CONFIG_CPU_STATE + 0x4) +#define CONFIG_CPU2_STATE (CONFIG_CPU_STATE + 0x8) +#define CONFIG_CPU3_STATE (CONFIG_CPU_STATE + 0xC) + +#define RESET (1 << 0) +#define SECONDARY_RESET (1 << 1) + #endif /* __CONFIG_EXYNOS5_COMMON_H */
On 15/01/15 22:33, Akshay Saraswat wrote:
This patch adds "iRAM, CPU state and low power" configs which are the addresses acting as flag registers.
iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal to CONFIG_LOWPOWER_EN then it jumps to the address (0x02020000+CPUID*4). This is a part of iROM logic. Rest other flags are being used at various places during kernel switching and reset. They are nowhere documented because they are part programming. These configs are serving as flags for us because they are representing the addresses in iRAM which we are using for storing and extracting CPU Status and GIC status.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com
include/configs/exynos5-common.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index ad63f3c..831bfd3 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -231,4 +231,32 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTENV
+/* iRAM */ +#define CONFIG_PHY_IRAM_BASE 0x02020000 +#define CONFIG_SEC_IRAM_SIZE 0x53000 /* 332KB */
+#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_PHY_IRAM_BASE \
+ CONFIG_SEC_IRAM_SIZE)+/*
- Low Power settings
- */
+#define CONFIG_LOWPOWER_FLAG 0x02020028 +#define CONFIG_LOWPOWER_ADDR 0x0202002C +#define CONFIG_LOWPOWER_EN 0xc9cfcfcf
+/*
- CPU State Settings
- */
+#define CONFIG_CPU_STATE (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x28) +#define CONFIG_GIC_STATE (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x38)
+#define CONFIG_CPU0_STATE (CONFIG_CPU_STATE + 0x0) +#define CONFIG_CPU1_STATE (CONFIG_CPU_STATE + 0x4) +#define CONFIG_CPU2_STATE (CONFIG_CPU_STATE + 0x8) +#define CONFIG_CPU3_STATE (CONFIG_CPU_STATE + 0xC)
+#define RESET (1 << 0) +#define SECONDARY_RESET (1 << 1)
These two defines looks very common. Please modify the name.
Thanks, Minkyu Kang.
On 15 January 2015 at 06:33, Akshay Saraswat akshay.s@samsung.com wrote:
This patch adds "iRAM, CPU state and low power" configs which are the addresses acting as flag registers.
iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal to CONFIG_LOWPOWER_EN then it jumps to the address (0x02020000+CPUID*4). This is a part of iROM logic. Rest other flags are being used at various places during kernel switching and reset. They are nowhere documented because they are part programming. These configs are serving as flags for us because they are representing the addresses in iRAM which we are using for storing and extracting CPU Status and GIC status.
Signed-off-by: Akshay Saraswat akshay.s@samsung.com
include/configs/exynos5-common.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
Tested on snow, pit, pi Tested-by: Simon Glass sjg@chromium.org
Akshay Saraswat akshay.s@samsung.com writes:
This patch series introduces changes for booting secondary CPUs on Exynos5420 and Exynos5800.
Thanks for this series. I think this should help get the odroid-xu3 behave better with the mainline linux kernel (assuming I can get it working with mainline u-boot/SPL.)
Are you testing this on mainline u-boot?
Can you describe what platforms you've tested this on and whether or not those platforms are using secure firmware?
Kevin
participants (4)
-
Akshay Saraswat -
Kevin Hilman -
Minkyu Kang -
Simon Glass