From: Stefan Agner stefan.agner@toradex.com

Flush operations need to be cacheline aligned to take effect, make sure to flush always complete cachelines. This avoids messages such as: CACHE: Misaligned operation at range [00900000, 009004d9]

Signed-off-by: Stefan Agner stefan.agner@toradex.com ---

arch/arm/cpu/armv7/virt-v7.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 9c53306..d33e5c6 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -54,10 +54,12 @@ static void relocate_secure_section(void) { #ifdef CONFIG_ARMV7_SECURE_BASE size_t sz = __secure_end - __secure_start; + unsigned long szflush = ALIGN(sz + 1, CONFIG_SYS_CACHELINE_SIZE);

memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz); + flush_dcache_range(CONFIG_ARMV7_SECURE_BASE, - CONFIG_ARMV7_SECURE_BASE + sz + 1); + CONFIG_ARMV7_SECURE_BASE + szflush); protect_secure_section(); invalidate_icache_all(); #endif