This is a patch containing all board specific files for the board directory tree.

Signed off by: Ron Madrid ron_madrid@sbcglobal.net

diff --git a/board/sheldon/simpc8313/Makefile b/board/sheldon/simpc8313/Makefile new file mode 100644 index 0000000..7c34c5e --- /dev/null +++ b/board/sheldon/simpc8313/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o sdram.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/sheldon/simpc8313/config.mk b/board/sheldon/simpc8313/config.mk new file mode 100644 index 0000000..95f6481 --- /dev/null +++ b/board/sheldon/simpc8313/config.mk @@ -0,0 +1,13 @@ +ifndef NAND_SPL +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp +endif + +ifndef TEXT_BASE +TEXT_BASE = 0xFE000000 +endif + +ifdef CONFIG_NAND_LP +PAD_TO = 0xFFF20000 +else +PAD_TO = 0xFFF04000 +endif diff --git a/board/sheldon/simpc8313/sdram.c b/board/sheldon/simpc8313/sdram.c new file mode 100644 index 0000000..4af29e2 --- /dev/null +++ b/board/sheldon/simpc8313/sdram.c @@ -0,0 +1,206 @@ +/* + * Copyright (C) Sheldon Instruments, Inc. 2008 + * + * Author: Ron Madrid info@sheldoninst.com + * Adapted from ../freescale/mpc8313erdb/sdram.c + * + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + */ + +#include <common.h> +#include <mpc83xx.h> +#include <spd_sdram.h> + +#include <asm/bitops.h> +#include <asm/io.h> + +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +static long fixed_sdram(void); + +#if defined(CONFIG_NAND_SPL) +#define puts(v) {} +void si_read_i2c(int, int, u8*); +void si_wait_i2c(void); +#endif + +#define DDRLAWAR_SIZE 0x0000003F + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile lbus83xx_t *lbc= &im->lbus; + + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + puts("Initializing\n"); + + /* DDR SDRAM - Main SODIMM */ + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + + msize = fixed_sdram(); + + /* Local Bus setup lbcr and mrtpr */ + lbc->lbcr = CFG_LBC_LBCR; + lbc->mrtpr = CFG_LBC_MRTPR; + sync(); + + puts(" DDR RAM: "); + /* return total bus SDRAM size(bytes) -- DDR */ + return (msize * 1024 * 1024); +} + +/************************************************************************* + * fixed sdram init -- reads values from boot sequencer I2C + ************************************************************************/ +static long fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msizelog2, msize = 1; +#if defined(CONFIG_NAND_SPL) + u32 i; + u8 buffer[135]; + u32 lbyte = 0, count = 135; + u32 addr = 0, data = 0; + + si_read_i2c(lbyte, count, buffer); + + for (i = 18; i < count; i+=7){ + addr = (u32)buffer[i]; + addr <<= 8; + addr |= (u32)buffer[i + 1]; + addr <<= 2; + data = (u32)buffer[i + 2]; + data <<= 8; + data |= (u32)buffer[i + 3]; + data <<= 8; + data |= (u32)buffer[i + 4]; + data <<= 8; + data |= (u32)buffer[i + 5]; + + *((u32 *)(CFG_IMMR + addr)) = data; + } + + sync(); + + /* enable DDR controller */ + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; +#endif /* (CONFIG_NAND_SPL) */ + + msizelog2 = ((im->sysconf.ddrlaw[0].ar & DDRLAWAR_SIZE) + 1); + msize <<= (msizelog2 - 20); + + return msize; +} + +#if defined(CONFIG_NAND_SPL) +void si_read_i2c(int lbyte, int count, u8 *buffer) +{ + u8 chip = 0x50; /* boot sequencer I2C */ + u8 ubyte; + u8 dummy; + u32 i; + volatile immap_t *im = (immap_t *) CFG_IMMR; + + chip <<= 1; + ubyte = (lbyte&0xff00)>>8; + lbyte &= 0xff; + + /* + * Set up controller + */ + im->i2c[0].cr = 0x00; + im->i2c[0].fdr = 0x3f; + im->i2c[0].dfsrr = 0x10; + im->i2c[0].adr = 0x00; + im->i2c[0].sr = 0x80; + im->i2c[0].dr = 0; + + while (im->i2c[0].sr & 0x20) + ; + + /* + * Writing address to device + */ + im->i2c[0].cr = 0xb0; + im->i2c[0].dr = chip; + si_wait_i2c(); + + im->i2c[0].cr = 0xb0; + im->i2c[0].dr = ubyte; + + si_wait_i2c(); + im->i2c[0].dr = lbyte; + si_wait_i2c(); + im->i2c[0].cr = 0xb4; + im->i2c[0].dr = chip + 1; + si_wait_i2c(); + im->i2c[0].cr = 0xa0; + + /* + * Dummy read + */ + dummy = im->i2c[0].dr; + + si_wait_i2c(); + + /* + * Read actual data + */ + for (i = 0; i < count; i++) + { + if (i == (count - 2)) /* Reached next to last byte */ + im->i2c[0].cr = 0xa8; + if (i == (count - 1)) /* Reached last byte */ + im->i2c[0].cr = 0x88; + + /* Read byte of data */ + buffer[i] = im->i2c[0].dr; + + if (i ==(count - 1)) + break; + si_wait_i2c(); + + } + + /* + * Reset controller + */ + im->i2c[0].cr = 0x80; + im->i2c[0].sr = 0x00; + + return; +} + +void si_wait_i2c(void){ + volatile immap_t *im = (immap_t *) CFG_IMMR; + + while (!(im->i2c[0].sr & 0x02)) + ; + im->i2c[0].sr = 0; + return; +} +#endif /* CONFIG_NAND_SPL */ diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c new file mode 100644 index 0000000..b810a20 --- /dev/null +++ b/board/sheldon/simpc8313/simpc8313.c @@ -0,0 +1,147 @@ +/* + * Copyright (C) Sheldon Instruments, Inc. 2008 + * + * Author: Ron Madrid info@sheldoninst.com + * Adapted from ../freescale/mpc8313erdb/mpc8313erdb.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif +#include <pci.h> +#include <mpc83xx.h> +#include <ns16550.h> +#include <nand.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + + if (im->pmc.pmccr1 & PMCCR1_POWER_OFF) + gd->flags |= GD_FLG_SILENT; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Sheldon Instruments SIMPC8313\n"); + return 0; +} + +#ifndef CONFIG_NAND_SPL +static struct pci_region pci_regions[] = { + { + bus_start: CFG_PCI1_MEM_BASE, + phys_start: CFG_PCI1_MEM_PHYS, + size: CFG_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI1_MMIO_BASE, + phys_start: CFG_PCI1_MMIO_PHYS, + size: CFG_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCI1_IO_BASE, + phys_start: CFG_PCI1_IO_PHYS, + size: CFG_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + struct pci_region *reg[] = { pci_regions }; + int warmboot; + + /* Enable all 3 PCI_CLK_OUTPUTs. */ + clk->occr |= 0xe0000000; + + /* + * Configure PCI Local Access Windows + */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; + + mpc83xx_pci_init(1, reg, warmboot); +} + +/* + * Miscellaneous late-boot configurations + */ +int misc_init_r(void) +{ + int rc = 0; + + return rc; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} +#endif +#else /* CONFIG_NAND_SPL */ +void board_init_f(ulong bootflag) +{ + board_early_init_f(); + NS16550_init((NS16550_t)(CFG_IMMR + 0x4500), + CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE); + puts("NAND boot... "); + init_timebase(); + initdram(0); + relocate_code(CFG_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd, + CFG_NAND_U_BOOT_RELOC); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (gd->flags & GD_FLG_SILENT) + return; + + if (c == '\n') + NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), '\r'); + + NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), c); +} +#endif