[U-Boot] [PATCHv2 1/3] arm: socfpga: add reset manager defines for Arria10
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- v2: Add commit hash-id for original commit from Linux kernel --- include/dt-bindings/reset/altr,rst-mgr-a10.h | 103 +++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) create mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h
diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h new file mode 100644 index 0000000..7619ca2 --- /dev/null +++ b/include/dt-bindings/reset/altr,rst-mgr-a10.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014, Steffen Trumtrar s.trumtrar@pengutronix.de + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H + +/* MPUMODRST */ +#define CPU0_RESET 0 +#define CPU1_RESET 1 +#define WDS_RESET 2 +#define SCUPER_RESET 3 + +/* PER0MODRST */ +#define EMAC0_RESET 32 +#define EMAC1_RESET 33 +#define EMAC2_RESET 34 +#define USB0_RESET 35 +#define USB1_RESET 36 +#define NAND_RESET 37 +#define QSPI_RESET 38 +#define SDMMC_RESET 39 +#define EMAC0_OCP_RESET 40 +#define EMAC1_OCP_RESET 41 +#define EMAC2_OCP_RESET 42 +#define USB0_OCP_RESET 43 +#define USB1_OCP_RESET 44 +#define NAND_OCP_RESET 45 +#define QSPI_OCP_RESET 46 +#define SDMMC_OCP_RESET 47 +#define DMA_RESET 48 +#define SPIM0_RESET 49 +#define SPIM1_RESET 50 +#define SPIS0_RESET 51 +#define SPIS1_RESET 52 +#define DMA_OCP_RESET 53 +#define EMAC_PTP_RESET 54 +/* 55 is empty*/ +#define DMAIF0_RESET 56 +#define DMAIF1_RESET 57 +#define DMAIF2_RESET 58 +#define DMAIF3_RESET 59 +#define DMAIF4_RESET 60 +#define DMAIF5_RESET 61 +#define DMAIF6_RESET 62 +#define DMAIF7_RESET 63 + +/* PER1MODRST */ +#define L4WD0_RESET 64 +#define L4WD1_RESET 65 +#define L4SYSTIMER0_RESET 66 +#define L4SYSTIMER1_RESET 67 +#define SPTIMER0_RESET 68 +#define SPTIMER1_RESET 69 +/* 70-71 is reserved */ +#define I2C0_RESET 72 +#define I2C1_RESET 73 +#define I2C2_RESET 74 +#define I2C3_RESET 75 +#define I2C4_RESET 76 +/* 77-79 is reserved */ +#define UART0_RESET 80 +#define UART1_RESET 81 +/* 82-87 is reserved */ +#define GPIO0_RESET 88 +#define GPIO1_RESET 89 +#define GPIO2_RESET 90 + +/* BRGMODRST */ +#define HPS2FPGA_RESET 96 +#define LWHPS2FPGA_RESET 97 +#define FPGA2HPS_RESET 98 +#define F2SSDRAM0_RESET 99 +#define F2SSDRAM1_RESET 100 +#define F2SSDRAM2_RESET 101 +#define DDRSCH_RESET 102 + +/* SYSMODRST*/ +#define ROM_RESET 128 +#define OCRAM_RESET 129 +/* 130 is reserved */ +#define FPGAMGR_RESET 131 +#define S2F_RESET 132 +#define SYSDBG_RESET 133 +#define OCRAM_OCP_RESET 134 + +/* COLDMODRST */ +#define CLKMGRCOLD_RESET 160 +/* 161-162 is reserved */ +#define S2FCOLD_RESET 163 +#define TIMESTAMPCOLD_RESET 164 +#define TAPCOLD_RESET 165 +#define HMCCOLD_RESET 166 +#define IOMGRCOLD_RESET 167 + +/* NRSTMODRST */ +#define NRSTPINOE_RESET 192 + +/* DBGMODRST */ +#define DBG_RESET 224 +#endif
From: Dinh Nguyen dinguyen@kernel.org
There is no dependency on doing a separate clrbits first in the dwmac_deassert_reset function. Combine them into a single clrsetbits call.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- arch/arm/mach-socfpga/misc.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 517f629..e8bd3cf 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -100,13 +100,10 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id) return; }
- /* Clearing emac0 PHY interface select to 0 */ - clrbits_le32(&sysmgr_regs->emacgrp_ctrl, - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); - /* configure to PHY interface select choosed */ - setbits_le32(&sysmgr_regs->emacgrp_ctrl, - SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); + clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, + SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
/* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0);
From: Dinh Nguyen dinguyen@kernel.org
On the Arria10, the EMAC phy mode configuration for each EMACs is located in separate registers versus being in 1 register for the GEN5 devices. The Arria10 also has 3 EMACs compared to 2 for the GEN5 devices.
Update the dwmac_deassert_reset function to support both GEN5 and Arria10 devices.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com --- v2: simplify the implementation a bit --- arch/arm/mach-socfpga/include/mach/system_manager.h | 4 +--- arch/arm/mach-socfpga/misc.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 9ca889a..831ba4a 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -133,9 +133,7 @@ struct socfpga_system_manager { u32 usb0_l3master; u32 usb1_l3master; u32 emac_global; - u32 emac0; - u32 emac1; - u32 emac2; + u32 emac[3]; u32 _pad_0x50_0x5f[4]; u32 fpgaintf_en_global; u32 fpgaintf_en_0; diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index e8bd3cf..5ae1d7d 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -22,7 +22,11 @@ #include <asm/arch/scu.h> #include <asm/pl310.h>
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #include <dt-bindings/reset/altr,rst-mgr.h> +#else +#include <dt-bindings/reset/altr,rst-mgr-a10.h> +#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -95,15 +99,25 @@ static void dwmac_deassert_reset(const unsigned int of_reset_id) } else if (of_reset_id == EMAC1_RESET) { physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; reset = SOCFPGA_RESET(EMAC1); +#ifndef CONFIG_TARGET_SOCFPGA_GEN5 + } else if (of_reset_id == EMAC2_RESET) { + reset = SOCFPGA_RESET(EMAC2); +#endif } else { printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id); return; }
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* configure to PHY interface select choosed */ clrsetbits_le32(&sysmgr_regs->emacgrp_ctrl, SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift, SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); +#else + clrsetbits_le32(&sysmgr_regs->emac[of_reset_id - EMAC0_RESET], + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, + SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII); +#endif
/* Release the EMAC controller from reset */ socfpga_per_reset(reset, 0);
On Tuesday, January 12, 2016 at 09:56:42 PM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Applied all three to u-boot-socfpga/02-arria10 , thanks!
btw what's the status of A10 ? What will I be able to compile it (and thus merge the stuff into mainline and ev. use it on actual A10) ? A board would be nice too ;-)
Best regards, Marek Vasut
On 01/12/2016 04:02 PM, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 09:56:42 PM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Applied all three to u-boot-socfpga/02-arria10 , thanks!
btw what's the status of A10 ? What will I be able to compile it (and thus merge the stuff into mainline and ev. use it on actual A10) ? A board would be nice too ;-)
Here is my list of to-do that is left for A10:
- submit SDRAM controller - rework FPGA manager for A10 - port an SPL for A10
I think the most work will be the SDRAM controller as it needs quite a bit of cleanup. I'm about ~25% through with that.
As for HW, I'll see what I can do.
Dinh
On Tuesday, January 12, 2016 at 11:11:42 PM, Dinh Nguyen wrote:
On 01/12/2016 04:02 PM, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 09:56:42 PM, dinguyen@opensource.altera.com
wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Applied all three to u-boot-socfpga/02-arria10 , thanks!
btw what's the status of A10 ? What will I be able to compile it (and thus merge the stuff into mainline and ev. use it on actual A10) ? A board would be nice too ;-)
Here is my list of to-do that is left for A10:
- submit SDRAM controller
- rework FPGA manager for A10
- port an SPL for A10
I think the most work will be the SDRAM controller as it needs quite a bit of cleanup. I'm about ~25% through with that.
Didn't you mention that you use nios2 that magically does that init for you? Shall I expect thousands of LoC SDRAM controller driver again or is there something "lighter" coming up ? ;-)
As for HW, I'll see what I can do.
Don't worry about it too much. I also poked Chin about it some time ago, but I dunno where he got with this.
Thanks!
Best regards, Marek Vasut
On Tue, 2016-01-12 at 23:16 +0100, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 11:11:42 PM, Dinh Nguyen wrote:
On 01/12/2016 04:02 PM, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 09:56:42 PM, dinguyen@opensource.altera.com
wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Applied all three to u-boot-socfpga/02-arria10 , thanks!
btw what's the status of A10 ? What will I be able to compile it (and thus merge the stuff into mainline and ev. use it on actual A10) ? A board would be nice too ;-)
Here is my list of to-do that is left for A10:
- submit SDRAM controller
- rework FPGA manager for A10
- port an SPL for A10
I think the most work will be the SDRAM controller as it needs quite a bit of cleanup. I'm about ~25% through with that.
Didn't you mention that you use nios2 that magically does that init for you? Shall I expect thousands of LoC SDRAM controller driver again or is there something "lighter" coming up ? ;-)
Yah it should be lighter as all SDRAM configuration now part of bitstream. Driver just need to derive the value from bitstream register and setup the DDR controller. No more DDR handoff.
As for HW, I'll see what I can do.
Don't worry about it too much. I also poked Chin about it some time ago, but I dunno where he got with this.
I am still working on this. We have limited boards as we will be getting production board in a month time. Dinh, you have any boards to spare? Most of boards here already went into test farms.
Thanks Chin Liang
Thanks!
Best regards, Marek Vasut
On Wednesday, January 13, 2016 at 02:58:42 AM, Chin Liang See wrote:
On Tue, 2016-01-12 at 23:16 +0100, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 11:11:42 PM, Dinh Nguyen wrote:
On 01/12/2016 04:02 PM, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 09:56:42 PM, dinguyen@opensource.altera.com
wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Applied all three to u-boot-socfpga/02-arria10 , thanks!
btw what's the status of A10 ? What will I be able to compile it (and thus merge the stuff into mainline and ev. use it on actual A10) ? A board would be nice too ;-)
Here is my list of to-do that is left for A10:
- submit SDRAM controller
- rework FPGA manager for A10
- port an SPL for A10
I think the most work will be the SDRAM controller as it needs quite a bit of cleanup. I'm about ~25% through with that.
Didn't you mention that you use nios2 that magically does that init for you? Shall I expect thousands of LoC SDRAM controller driver again or is there something "lighter" coming up ? ;-)
Yah it should be lighter as all SDRAM configuration now part of bitstream. Driver just need to derive the value from bitstream register and setup the DDR controller. No more DDR handoff.
Whew :)
As for HW, I'll see what I can do.
Don't worry about it too much. I also poked Chin about it some time ago, but I dunno where he got with this.
I am still working on this. We have limited boards as we will be getting production board in a month time. Dinh, you have any boards to spare? Most of boards here already went into test farms.
I'll wait for the production ones , no need to hurry :)
Best regards, Marek Vasut
On 01/12/2016 08:04 PM, Marek Vasut wrote:
On Wednesday, January 13, 2016 at 02:58:42 AM, Chin Liang See wrote:
On Tue, 2016-01-12 at 23:16 +0100, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 11:11:42 PM, Dinh Nguyen wrote:
On 01/12/2016 04:02 PM, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 09:56:42 PM, dinguyen@opensource.altera.com
wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Applied all three to u-boot-socfpga/02-arria10 , thanks!
btw what's the status of A10 ? What will I be able to compile it (and thus merge the stuff into mainline and ev. use it on actual A10) ? A board would be nice too ;-)
Here is my list of to-do that is left for A10:
- submit SDRAM controller
- rework FPGA manager for A10
- port an SPL for A10
I think the most work will be the SDRAM controller as it needs quite a bit of cleanup. I'm about ~25% through with that.
Didn't you mention that you use nios2 that magically does that init for you? Shall I expect thousands of LoC SDRAM controller driver again or is there something "lighter" coming up ? ;-)
Yah it should be lighter as all SDRAM configuration now part of bitstream. Driver just need to derive the value from bitstream register and setup the DDR controller. No more DDR handoff.
Whew :)
While all of the above is true, the *crap* that is in the current implementation needs to get cleaned up. It's amazing to me how we(Altera) continue to go down this path of having to do things twice, instead of trying to upstream first!
As for HW, I'll see what I can do.
Don't worry about it too much. I also poked Chin about it some time ago, but I dunno where he got with this.
I am still working on this. We have limited boards as we will be getting production board in a month time. Dinh, you have any boards to spare? Most of boards here already went into test farms.
I'll wait for the production ones , no need to hurry :)
That's probably best. I do have an extra Rev A hardware, but trust me, you don't want to have anything do with that hardware.
Dinh
On Wednesday, January 13, 2016 at 06:28:36 PM, Dinh Nguyen wrote:
On 01/12/2016 08:04 PM, Marek Vasut wrote:
On Wednesday, January 13, 2016 at 02:58:42 AM, Chin Liang See wrote:
On Tue, 2016-01-12 at 23:16 +0100, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 11:11:42 PM, Dinh Nguyen wrote:
On 01/12/2016 04:02 PM, Marek Vasut wrote:
On Tuesday, January 12, 2016 at 09:56:42 PM, dinguyen@opensource.altera.com
wrote: > From: Dinh Nguyen dinguyen@opensource.altera.com > > Add the Arria10 reset manager defines that is used in Linux. > Change the > license to SPDX. > > [commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux > kernel] > > Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Applied all three to u-boot-socfpga/02-arria10 , thanks!
btw what's the status of A10 ? What will I be able to compile it (and thus merge the stuff into mainline and ev. use it on actual A10) ? A board would be nice too ;-)
Here is my list of to-do that is left for A10:
- submit SDRAM controller
- rework FPGA manager for A10
- port an SPL for A10
I think the most work will be the SDRAM controller as it needs quite a bit of cleanup. I'm about ~25% through with that.
Didn't you mention that you use nios2 that magically does that init for you? Shall I expect thousands of LoC SDRAM controller driver again or is there something "lighter" coming up ? ;-)
Yah it should be lighter as all SDRAM configuration now part of bitstream. Driver just need to derive the value from bitstream register and setup the DDR controller. No more DDR handoff.
Whew :)
While all of the above is true, the *crap* that is in the current implementation needs to get cleaned up. It's amazing to me how we(Altera) continue to go down this path of having to do things twice, instead of trying to upstream first!
You'll soon be doing them thrice *smirk* , or maybe you already do ;-)
As for HW, I'll see what I can do.
Don't worry about it too much. I also poked Chin about it some time ago, but I dunno where he got with this.
I am still working on this. We have limited boards as we will be getting production board in a month time. Dinh, you have any boards to spare? Most of boards here already went into test farms.
I'll wait for the production ones , no need to hurry :)
That's probably best. I do have an extra Rev A hardware, but trust me, you don't want to have anything do with that hardware.
You can save one collector's edition for me, it'd look nice right next to the Excalibur XA10 ;-D
On Tuesday, January 12, 2016 at 09:56:42 PM, dinguyen@opensource.altera.com wrote:
From: Dinh Nguyen dinguyen@opensource.altera.com
Add the Arria10 reset manager defines that is used in Linux. Change the license to SPDX.
[commit 007bb689b3dbad83cdab0ad192bc6ed0162451e0 from the Linux kernel]
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com
Hi!
A10 branch is now u-boot-socfpga/01-arria10 .
What is the current status of Arria10 please ?
Best regards, Marek Vasut
On 02/04/2016 05:46 AM, Marek Vasut wrote:
A10 branch is now u-boot-socfpga/01-arria10 .
Thanks for carrying this.
What is the current status of Arria10 please ?
I haven't had time to work on Arria10 in the last 2 weeks. I hope to get back to it next week. I think I may have to slim the patches down to just fixing building for it.
Dinh
On Thursday, February 04, 2016 at 09:59:28 PM, Dinh Nguyen wrote:
On 02/04/2016 05:46 AM, Marek Vasut wrote:
A10 branch is now u-boot-socfpga/01-arria10 .
Thanks for carrying this.
What is the current status of Arria10 please ?
I haven't had time to work on Arria10 in the last 2 weeks. I hope to get back to it next week. I think I may have to slim the patches down to just fixing building for it.
Got it, thanks
Best regards, Marek Vasut
participants (5)
-
Chin Liang See -
dinguyen＠opensource.altera.com -
Dinh Nguyen -
Dinh Nguyen
-
Marek Vasut