[PATCH v1 0/2] Add bitbang feature for npcm8xx and driver
Driver didn't support bitbang feature. Add bb_miiphy_bus function for driver and open feature for npcm8xx
the log is as below: ------------------------------------- U-Boot 2023.04-rc2-dirty (Feb 14 2023 - 15:01:17 +0800)
CPU-0: NPCM845 A1 @ Model: Nuvoton npcm845 Development Board (Device Tree) DRAM: 848 MiB RNG: NPCM RNG module bind OK OTP: NPCM OTP module bind OK AES: NPCM AES module bind OK SHA: NPCM SHA module bind OK Core: 617 devices, 23 uclasses, devicetree: separate MMC: sdhci@f0842000: 0 Loading Environment from SPIFlash... SF: Detected mx66l1g45g with page size 256 Bytes, erase size 4 KiB, total 128 MiB OK In: serial@0 Out: serial@0 Err: serial@0 Net: eth0: eth@f0802000, eth1: eth@f0804000 eth@f0808000: use bitbang mii.. , eth3: eth@f0808000 Hit any key to stop autoboot: 0 U-Boot>ping 192.168.0.5 eth@f0804000 Waiting for PHY auto negotiation to complete......... TIMEOUT ! Could not initialize PHY eth@f0804000 Speed: 100, full duplex Using eth@f0808000 device host 192.168.0.5 is alive -------------------------------------------------
Jim Liu (2): ARM: configs: add bitbang feature for npcm8xx net: designware: add bitbang feature for designware driver
configs/arbel_evb_defconfig | 3 + drivers/net/designware.c | 109 +++++++++++++++++++++++++++++++++++- drivers/net/designware.h | 3 + include/configs/arbel.h | 1 + 4 files changed, 115 insertions(+), 1 deletion(-)
Signed-off-by: Jim Liu JJLIU0@nuvoton.com --- configs/arbel_evb_defconfig | 3 +++ include/configs/arbel.h | 1 + 2 files changed, 4 insertions(+)
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 8f8a603b50..ac4bb40193 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -92,3 +92,6 @@ CONFIG_NPCM_AES=y CONFIG_NPCM_OTP=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_NPCM8XX=y +CONFIG_BITBANGMII=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=0 diff --git a/include/configs/arbel.h b/include/configs/arbel.h index 8e27fb52a1..d009543ff5 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -10,6 +10,7 @@ #define CFG_SYS_BOOTMAPSZ (20 << 20) #define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE #define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_BITBANGMII_MULTI
/* Default environemnt variables */ #define CFG_EXTRA_ENV_SETTINGS "uimage_flash_addr=80200000\0" \
On Tue, Feb 14, 2023 at 04:20:35PM +0800, Jim Liu wrote:
Signed-off-by: Jim Liu JJLIU0@nuvoton.com
configs/arbel_evb_defconfig | 3 +++ include/configs/arbel.h | 1 + 2 files changed, 4 insertions(+)
diff --git a/configs/arbel_evb_defconfig b/configs/arbel_evb_defconfig index 8f8a603b50..ac4bb40193 100644 --- a/configs/arbel_evb_defconfig +++ b/configs/arbel_evb_defconfig @@ -92,3 +92,6 @@ CONFIG_NPCM_AES=y CONFIG_NPCM_OTP=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_NPCM8XX=y +CONFIG_BITBANGMII=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=0 diff --git a/include/configs/arbel.h b/include/configs/arbel.h index 8e27fb52a1..d009543ff5 100644 --- a/include/configs/arbel.h +++ b/include/configs/arbel.h @@ -10,6 +10,7 @@ #define CFG_SYS_BOOTMAPSZ (20 << 20) #define CFG_SYS_INIT_RAM_ADDR CFG_SYS_SDRAM_BASE #define CFG_SYS_INIT_RAM_SIZE 0x8000 +#define CONFIG_BITBANGMII_MULTI
No "#define CONFIG" in board config.h files, this won't pass CI.
Add bb_miiphy_bus function for designware bitbang feature.
Signed-off-by: Jim Liu JJLIU0@nuvoton.com --- drivers/net/designware.c | 109 ++++++++++++++++++++++++++++++++++++++- drivers/net/designware.h | 3 ++ 2 files changed, 111 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index e09ca3313d..c539afc620 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -757,6 +757,32 @@ int designware_eth_probe(struct udevice *dev) } priv->bus = miiphy_get_dev_by_name(dev->name);
+#if defined(CONFIG_BITBANGMII) && defined(CONFIG_DM_GPIO) + if (dev_read_bool(dev, "snps,bitbang-mii")) { + printf("\n%s: use bitbang mii..\n", dev->name); + ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0, + &priv->mdc_gpio, GPIOD_IS_OUT); + if (ret) { + printf("no mdc-gpio\n"); + return ret; + } + + ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0, + &priv->mdio_gpio, GPIOD_IS_OUT); + + if (ret) { + printf("no mdio-gpio\n"); + return ret; + } + dm_gpio_set_value(&priv->mdc_gpio, 1); + bb_miiphy_buses[0].priv = priv; + sprintf(bb_miiphy_buses[0].name, dev->name); + priv->bus->read = bb_miiphy_read; + priv->bus->write = bb_miiphy_write; + priv->bus->reset = NULL; + } +#endif + ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); if (!ret) @@ -826,7 +852,7 @@ int designware_eth_of_to_plat(struct udevice *dev) reset_flags |= GPIOD_ACTIVE_LOW;
ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, - &priv->reset_gpio, reset_flags); + &priv->reset_gpio, reset_flags); if (ret == 0) { ret = dev_read_u32_array(dev, "snps,reset-delays-us", dw_pdata->reset_delays, 3); @@ -866,3 +892,84 @@ static struct pci_device_id supported[] = { };
U_BOOT_PCI_DEVICE(eth_designware, supported); + +#if defined(CONFIG_BITBANGMII) && CONFIG_IS_ENABLED(DM_GPIO) +int dw_eth_bb_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + struct gpio_desc *desc = &priv->mdio_gpio; + desc->flags = 0; + dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT); + + return 0; +} + +static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct dw_eth_dev *priv = bus->priv; + struct gpio_desc *desc = &priv->mdio_gpio; + desc->flags = 0; + dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN); + + return 0; +} + +static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct dw_eth_dev *priv = bus->priv; + + if (v) + dm_gpio_set_value(&priv->mdio_gpio, 1); + else + dm_gpio_set_value(&priv->mdio_gpio, 0); + + return 0; +} + +static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct dw_eth_dev *priv = bus->priv; + + *v = dm_gpio_get_value(&priv->mdio_gpio); + return 0; +} + +static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct dw_eth_dev *priv = bus->priv; + + if (v) + dm_gpio_set_value(&priv->mdc_gpio, 1); + else + dm_gpio_set_value(&priv->mdc_gpio, 0); + + return 0; +} + +static int dw_eth_bb_delay(struct bb_miiphy_bus *bus) +{ + udelay(1); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "dw_eth_bb", + .init = dw_eth_bb_init, + .mdio_active = dw_eth_bb_mdio_active, + .mdio_tristate = dw_eth_bb_mdio_tristate, + .set_mdio = dw_eth_bb_set_mdio, + .get_mdio = dw_eth_bb_get_mdio, + .set_mdc = dw_eth_bb_set_mdc, + .delay = dw_eth_bb_delay, + } +}; + +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); +#endif diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 9da4e902cb..68ca5d9cd0 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -235,6 +235,9 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; #if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio; + struct gpio_desc mdc_gpio; + struct gpio_desc mdio_gpio; + int mdio_val; #endif #ifdef CONFIG_CLK struct clk *clocks; /* clock list */
Hi Ramon
Please help to review this patch or provide some suggestions.
Nuvoton BMC NPCM845 EVB needs this patch, and customers will use it to test. If you have any questions please let me know.
Best regards, Jim
On Tue, Feb 14, 2023 at 4:20 PM Jim Liu jim.t90615@gmail.com wrote:
Add bb_miiphy_bus function for designware bitbang feature.
Signed-off-by: Jim Liu JJLIU0@nuvoton.com
drivers/net/designware.c | 109 ++++++++++++++++++++++++++++++++++++++- drivers/net/designware.h | 3 ++ 2 files changed, 111 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index e09ca3313d..c539afc620 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -757,6 +757,32 @@ int designware_eth_probe(struct udevice *dev) } priv->bus = miiphy_get_dev_by_name(dev->name);
+#if defined(CONFIG_BITBANGMII) && defined(CONFIG_DM_GPIO)
if (dev_read_bool(dev, "snps,bitbang-mii")) {printf("\n%s: use bitbang mii..\n", dev->name);ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,&priv->mdc_gpio, GPIOD_IS_OUT);if (ret) {printf("no mdc-gpio\n");return ret;}ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,&priv->mdio_gpio, GPIOD_IS_OUT);if (ret) {printf("no mdio-gpio\n");return ret;}dm_gpio_set_value(&priv->mdc_gpio, 1);bb_miiphy_buses[0].priv = priv;sprintf(bb_miiphy_buses[0].name, dev->name);priv->bus->read = bb_miiphy_read;priv->bus->write = bb_miiphy_write;priv->bus->reset = NULL;}+#endif
ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); if (!ret)@@ -826,7 +852,7 @@ int designware_eth_of_to_plat(struct udevice *dev) reset_flags |= GPIOD_ACTIVE_LOW;
ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
&priv->reset_gpio, reset_flags);
&priv->reset_gpio, reset_flags); if (ret == 0) { ret = dev_read_u32_array(dev, "snps,reset-delays-us", dw_pdata->reset_delays, 3);@@ -866,3 +892,84 @@ static struct pci_device_id supported[] = { };
U_BOOT_PCI_DEVICE(eth_designware, supported);
+#if defined(CONFIG_BITBANGMII) && CONFIG_IS_ENABLED(DM_GPIO) +int dw_eth_bb_init(struct bb_miiphy_bus *bus) +{
return 0;+}
+static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{
struct dw_eth_dev *priv = bus->priv;struct gpio_desc *desc = &priv->mdio_gpio;desc->flags = 0;dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT);return 0;+}
+static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{
struct dw_eth_dev *priv = bus->priv;struct gpio_desc *desc = &priv->mdio_gpio;desc->flags = 0;dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN);return 0;+}
+static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{
struct dw_eth_dev *priv = bus->priv;if (v)dm_gpio_set_value(&priv->mdio_gpio, 1);elsedm_gpio_set_value(&priv->mdio_gpio, 0);return 0;+}
+static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{
struct dw_eth_dev *priv = bus->priv;*v = dm_gpio_get_value(&priv->mdio_gpio);return 0;+}
+static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{
struct dw_eth_dev *priv = bus->priv;if (v)dm_gpio_set_value(&priv->mdc_gpio, 1);elsedm_gpio_set_value(&priv->mdc_gpio, 0);return 0;+}
+static int dw_eth_bb_delay(struct bb_miiphy_bus *bus) +{
udelay(1);return 0;+}
+struct bb_miiphy_bus bb_miiphy_buses[] = {
{.name = "dw_eth_bb",.init = dw_eth_bb_init,.mdio_active = dw_eth_bb_mdio_active,.mdio_tristate = dw_eth_bb_mdio_tristate,.set_mdio = dw_eth_bb_set_mdio,.get_mdio = dw_eth_bb_get_mdio,.set_mdc = dw_eth_bb_set_mdc,.delay = dw_eth_bb_delay,}+};
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); +#endif diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 9da4e902cb..68ca5d9cd0 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -235,6 +235,9 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; #if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio;
struct gpio_desc mdc_gpio;struct gpio_desc mdio_gpio;int mdio_val;#endif #ifdef CONFIG_CLK struct clk *clocks; /* clock list */ -- 2.17.1
On Tue, Feb 14, 2023 at 10:20 AM Jim Liu jim.t90615@gmail.com wrote:
Add bb_miiphy_bus function for designware bitbang feature.
Signed-off-by: Jim Liu JJLIU0@nuvoton.com
drivers/net/designware.c | 109 ++++++++++++++++++++++++++++++++++++++- drivers/net/designware.h | 3 ++ 2 files changed, 111 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index e09ca3313d..c539afc620 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -757,6 +757,32 @@ int designware_eth_probe(struct udevice *dev) } priv->bus = miiphy_get_dev_by_name(dev->name);
+#if defined(CONFIG_BITBANGMII) && defined(CONFIG_DM_GPIO)
if (dev_read_bool(dev, "snps,bitbang-mii")) {printf("\n%s: use bitbang mii..\n", dev->name);
debug
ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,&priv->mdc_gpio, GPIOD_IS_OUT);if (ret) {printf("no mdc-gpio\n");return ret;}ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,&priv->mdio_gpio, GPIOD_IS_OUT);if (ret) {printf("no mdio-gpio\n");return ret;}dm_gpio_set_value(&priv->mdc_gpio, 1);bb_miiphy_buses[0].priv = priv;sprintf(bb_miiphy_buses[0].name, dev->name);priv->bus->read = bb_miiphy_read;priv->bus->write = bb_miiphy_write;priv->bus->reset = NULL;}+#endif
ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); if (!ret)@@ -826,7 +852,7 @@ int designware_eth_of_to_plat(struct udevice *dev) reset_flags |= GPIOD_ACTIVE_LOW;
ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
&priv->reset_gpio, reset_flags);
&priv->reset_gpio, reset_flags);
What has changed here ?
if (ret == 0) { ret = dev_read_u32_array(dev, "snps,reset-delays-us", dw_pdata->reset_delays, 3);@@ -866,3 +892,84 @@ static struct pci_device_id supported[] = { };
U_BOOT_PCI_DEVICE(eth_designware, supported);
+#if defined(CONFIG_BITBANGMII) && CONFIG_IS_ENABLED(DM_GPIO) +int dw_eth_bb_init(struct bb_miiphy_bus *bus) +{
return 0;+}
+static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{
struct dw_eth_dev *priv = bus->priv;struct gpio_desc *desc = &priv->mdio_gpio;desc->flags = 0;dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT);return 0;+}
+static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{
struct dw_eth_dev *priv = bus->priv;struct gpio_desc *desc = &priv->mdio_gpio;desc->flags = 0;dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN);return 0;+}
+static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{
struct dw_eth_dev *priv = bus->priv;if (v)dm_gpio_set_value(&priv->mdio_gpio, 1);elsedm_gpio_set_value(&priv->mdio_gpio, 0);return 0;+}
+static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{
struct dw_eth_dev *priv = bus->priv;*v = dm_gpio_get_value(&priv->mdio_gpio);return 0;+}
+static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{
struct dw_eth_dev *priv = bus->priv;if (v)dm_gpio_set_value(&priv->mdc_gpio, 1);elsedm_gpio_set_value(&priv->mdc_gpio, 0);return 0;+}
+static int dw_eth_bb_delay(struct bb_miiphy_bus *bus) +{
udelay(1);
Where is this 1 usec coming from ? should it be configurable ?
return 0;+}
+struct bb_miiphy_bus bb_miiphy_buses[] = {
{.name = "dw_eth_bb",.init = dw_eth_bb_init,.mdio_active = dw_eth_bb_mdio_active,.mdio_tristate = dw_eth_bb_mdio_tristate,.set_mdio = dw_eth_bb_set_mdio,.get_mdio = dw_eth_bb_get_mdio,.set_mdc = dw_eth_bb_set_mdc,.delay = dw_eth_bb_delay,}+};
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); +#endif diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 9da4e902cb..68ca5d9cd0 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -235,6 +235,9 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; #if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio;
struct gpio_desc mdc_gpio;struct gpio_desc mdio_gpio;int mdio_val;#endif #ifdef CONFIG_CLK struct clk *clocks; /* clock list */ -- 2.17.1
Hi Ramon
Thanks for your review. The udelay timing is defined on our spec . Does this need to use config to control it or use dts method to set the timing?
Best regards, Jim
On Sun, Jun 11, 2023 at 3:03 AM Ramon Fried rfried.dev@gmail.com wrote:
On Tue, Feb 14, 2023 at 10:20 AM Jim Liu jim.t90615@gmail.com wrote:
Add bb_miiphy_bus function for designware bitbang feature.
Signed-off-by: Jim Liu JJLIU0@nuvoton.com
drivers/net/designware.c | 109 ++++++++++++++++++++++++++++++++++++++- drivers/net/designware.h | 3 ++ 2 files changed, 111 insertions(+), 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index e09ca3313d..c539afc620 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -757,6 +757,32 @@ int designware_eth_probe(struct udevice *dev) } priv->bus = miiphy_get_dev_by_name(dev->name);
+#if defined(CONFIG_BITBANGMII) && defined(CONFIG_DM_GPIO)
if (dev_read_bool(dev, "snps,bitbang-mii")) {printf("\n%s: use bitbang mii..\n", dev->name);debug
ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,&priv->mdc_gpio, GPIOD_IS_OUT);if (ret) {printf("no mdc-gpio\n");return ret;}ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,&priv->mdio_gpio, GPIOD_IS_OUT);if (ret) {printf("no mdio-gpio\n");return ret;}dm_gpio_set_value(&priv->mdc_gpio, 1);bb_miiphy_buses[0].priv = priv;sprintf(bb_miiphy_buses[0].name, dev->name);priv->bus->read = bb_miiphy_read;priv->bus->write = bb_miiphy_write;priv->bus->reset = NULL;}+#endif
ret = dw_phy_init(priv, dev); debug("%s, ret=%d\n", __func__, ret); if (!ret)@@ -826,7 +852,7 @@ int designware_eth_of_to_plat(struct udevice *dev) reset_flags |= GPIOD_ACTIVE_LOW;
ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
&priv->reset_gpio, reset_flags);
&priv->reset_gpio, reset_flags);What has changed here ?
if (ret == 0) { ret = dev_read_u32_array(dev, "snps,reset-delays-us", dw_pdata->reset_delays, 3);@@ -866,3 +892,84 @@ static struct pci_device_id supported[] = { };
U_BOOT_PCI_DEVICE(eth_designware, supported);
+#if defined(CONFIG_BITBANGMII) && CONFIG_IS_ENABLED(DM_GPIO) +int dw_eth_bb_init(struct bb_miiphy_bus *bus) +{
return 0;+}
+static int dw_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{
struct dw_eth_dev *priv = bus->priv;struct gpio_desc *desc = &priv->mdio_gpio;desc->flags = 0;dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_OUT);return 0;+}
+static int dw_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{
struct dw_eth_dev *priv = bus->priv;struct gpio_desc *desc = &priv->mdio_gpio;desc->flags = 0;dm_gpio_set_dir_flags(&priv->mdio_gpio, GPIOD_IS_IN);return 0;+}
+static int dw_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{
struct dw_eth_dev *priv = bus->priv;if (v)dm_gpio_set_value(&priv->mdio_gpio, 1);elsedm_gpio_set_value(&priv->mdio_gpio, 0);return 0;+}
+static int dw_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{
struct dw_eth_dev *priv = bus->priv;*v = dm_gpio_get_value(&priv->mdio_gpio);return 0;+}
+static int dw_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{
struct dw_eth_dev *priv = bus->priv;if (v)dm_gpio_set_value(&priv->mdc_gpio, 1);elsedm_gpio_set_value(&priv->mdc_gpio, 0);return 0;+}
+static int dw_eth_bb_delay(struct bb_miiphy_bus *bus) +{
udelay(1);Where is this 1 usec coming from ? should it be configurable ?
return 0;+}
+struct bb_miiphy_bus bb_miiphy_buses[] = {
{.name = "dw_eth_bb",.init = dw_eth_bb_init,.mdio_active = dw_eth_bb_mdio_active,.mdio_tristate = dw_eth_bb_mdio_tristate,.set_mdio = dw_eth_bb_set_mdio,.get_mdio = dw_eth_bb_get_mdio,.set_mdc = dw_eth_bb_set_mdc,.delay = dw_eth_bb_delay,}+};
+int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); +#endif diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 9da4e902cb..68ca5d9cd0 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -235,6 +235,9 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; #if CONFIG_IS_ENABLED(DM_GPIO) struct gpio_desc reset_gpio;
struct gpio_desc mdc_gpio;struct gpio_desc mdio_gpio;int mdio_val;#endif #ifdef CONFIG_CLK struct clk *clocks; /* clock list */ -- 2.17.1
On Tue, Jun 13, 2023 at 9:29 AM Jim Liu jim.t90615@gmail.com wrote:
Hi Ramon
Thanks for your review. The udelay timing is defined on our spec . Does this need to use config to control it or use dts method to set the timing?
dts
Best regards, Jim
participants (3)
-
Jim Liu -
Ramon Fried -
Tom Rini