Hello,

Please, I'd like to ask for help/suggestions regarding the following problem that I have:

The problem is regarding making SPL (in SRAM) to booting U-boot from 16 bit NAND. While configuring & debugging, I did run SPL from address in the SDRAM, & it worked fine & loaded U-boot successfully. The next logical step was changing that address from SDRAM to an address in SRAM, the result was successful SPL running but hanging before loading U-Boot. So, I'm not sure if I should modify a configuration(s).

*The following are snippets from the related configurations in case of SPl at SDRAM:

#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl.lds" #define CONFIG_SPL_MAX_SIZE 0x7FF4 #define CONFIG_SPL_PAD_TO 0x7FF4 #define CONFIG_SPL_TEXT_BASE 0x46000000 #define CONFIG_SYS_MONITOR_LEN 0x40000 #define CONFIG_SYS_TEXT_BASE 0x43901028 #define CONFIG_SYS_NAND_U_BOOT_DST 0x43900028 #define CONFIG_SYS_NAND_U_BOOT_START 0x43900028

#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00020000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000

#define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS #define CONFIG_SYS_NAND_5_ADDR_CYCLE 1

#define CONFIG_SPL_NAND_SOFTECC 1 #define CONFIG_SYS_NAND_ECCSIZE 256 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47,\ 48, 49, 50, 51, 52, 53, 54, 55,\ 56, 57, 58, 59, 60, 61, 62, 63 } #define CONFIG_SPL_NAND_SIMPLE 1 #define CONFIG_SPL_NAND_BASE 1 #define CONFIG_SPL_BOARD_INIT 1 #define CONFIG_SPL_ENV_SUPPORT 1 #define CONFIG_SPL_INIT_MINIMAL 1 #define CONFIG_SPL_NAND_LOAD 1 #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_SPL_NAND_BOOT 1

#define DEBUG 1 #define CONFIG_PANIC_HANG 1 #define CONFIG_SPL_PANIC_ON_RAW_IMAGE 1

#define CONFIG_SPL 1 #define CONFIG_SPL_FRAMEWORK 1 #define CONFIG_SPL_LIBCOMMON_SUPPORT 1 #define CONFIG_SPL_LIBGENERIC_SUPPORT 1 #define CONFIG_SPL_SERIAL_SUPPORT 1

#define CONFIG_SPL_NAND_SUPPORT 1 #define CONFIG_SPL_NAND_ECC 1 #define CONFIG_SPL_NAND_DRIVERS 1

*While the modified configurations to run SPL from SRAM are:

#define CONFIG_SPL_BSS_MAX_SIZE 0x600 #define CONFIG_SPL_BSS_START_ADDR 0x106200 #define CONFIG_SPL_TEXT_BASE 0x100000

Thank you in advance.

Best regards, Ahmed