[U-Boot] [PATCH 0/4] Add support for Cadence QSPI on K2G
This series adds support for Cadence QSPI controller present on K2G SoC.
The first patch extends AHB address to 32 bit as K2G has 32 bit AHB address. Second patch enable QUAD mode based on DT data instead of relying on config option. And last to patches add DT node and add configs to enable the driver.
Depends on [1] to enable SPI driver model support on K2G and [2] to support different bus frequencies for two different SPI controllers present on K2G EVM.
[1]https://www.mail-archive.com/u-boot@lists.denx.de/msg209556.html [2]https://patchwork.ozlabs.org/patch/609947/
Vignesh R (4): spi: cadence_qspi_apb: Support 32 bit AHB address spi: cadence_quadspi: Enable QUAD mode based on DT data ARM: dts: K2G: Add support for QSPI controller defconfig: k2g_evm_defconfig: Enable Cadence QSPI controller
arch/arm/dts/k2g-evm.dts | 45 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/k2g.dtsi | 14 +++++++++++++ configs/k2g_evm_defconfig | 2 ++ drivers/spi/cadence_qspi.c | 3 ++- drivers/spi/cadence_qspi.h | 2 +- drivers/spi/cadence_qspi_apb.c | 15 +++++++------- include/configs/k2g_evm.h | 6 ++++++ 7 files changed, 77 insertions(+), 10 deletions(-)
AHB address can be as long as 32 bit, hence remove the CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT and read as u32 value, it anyway does not make sense to mask upper bits.
Signed-off-by: Vignesh R vigneshr@ti.com --- drivers/spi/cadence_qspi_apb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7786dd65f509..a31b43b0114d 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -44,7 +44,6 @@ #define CQSPI_INST_TYPE_QUAD (2)
#define CQSPI_STIG_DATA_LEN_MAX (8) -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF)
#define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4) @@ -694,7 +693,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, addr_bytes = cmdlen - 1;
/* Setup the indirect trigger address */ - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */ @@ -791,7 +790,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, return -EINVAL; } /* Setup the indirect trigger address */ - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
On 04/13/2016 12:52 PM, Vignesh R wrote:
AHB address can be as long as 32 bit, hence remove the CQSPI_REG_INDIRECTRDSTARTADDR mask. Since AHB address is passed from DT and read as u32 value, it anyway does not make sense to mask upper bits.
Signed-off-by: Vignesh R vigneshr@ti.com
drivers/spi/cadence_qspi_apb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-)
Oops, I didn't realize this was for U-Boot.
On SoCFPGA SoCkit: Tested-by: Marek Vasut marex@denx.de Acked-by: Marek Vasut marex@denx.de
Best regards, Marek Vasut
Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode.
Signed-off-by: Vignesh R vigneshr@ti.com --- drivers/spi/cadence_qspi.c | 3 ++- drivers/spi/cadence_qspi.h | 2 +- drivers/spi/cadence_qspi_apb.c | 10 +++++----- 3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 4f7fd5253220..a5244fff4d95 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -191,6 +191,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, struct udevice *bus = dev->parent; struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev); void *base = priv->regbase; u8 *cmd_buf = priv->cmd_buf; size_t data_bytes; @@ -250,7 +251,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, break; case CQSPI_INDIRECT_READ: err = cadence_qspi_apb_indirect_read_setup(plat, - priv->cmd_len, cmd_buf); + priv->cmd_len, dm_plat->mode_rx, cmd_buf); if (!err) { err = cadence_qspi_apb_indirect_read_execute (plat, data_bytes, din); diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 2912e36a53f7..a849f7b19973 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -53,7 +53,7 @@ int cadence_qspi_apb_command_write(void *reg_base_addr, unsigned int txlen, const u8 *txbuf);
int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, - unsigned int cmdlen, const u8 *cmdbuf); + unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf); int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, unsigned int rxlen, u8 *rxbuf); int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index a31b43b0114d..b8cf8277e1ee 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -28,6 +28,7 @@ #include <common.h> #include <asm/io.h> #include <asm/errno.h> +#include <spi.h> #include "cadence_qspi.h"
#define CQSPI_REG_POLL_US (1) /* 1us */ @@ -669,7 +670,7 @@ int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, - unsigned int cmdlen, const u8 *cmdbuf) + unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf) { unsigned int reg; unsigned int rd_reg; @@ -699,10 +700,9 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, /* Configure the opcode */ rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
-#if (CONFIG_SPI_FLASH_QUAD == 1) - /* Instruction and address at DQ0, data at DQ0-3. */ - rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; -#endif + if (rx_width & SPI_RX_QUAD) + /* Instruction and address at DQ0, data at DQ0-3. */ + rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
/* Get address */ addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
On 04/13/2016 12:52 PM, Vignesh R wrote:
Instead of relying on CONFIG_SPI_FLASH_QUAD to be defined to enable QUAD mode, make use of mode_rx field of dm_spi_slave_platdata to determine whether to enable or disable QUAD mode. This is necessary to support muliple SPI controllers where one of them may not support QUAD mode.
Signed-off-by: Vignesh R vigneshr@ti.com
drivers/spi/cadence_qspi.c | 3 ++- drivers/spi/cadence_qspi.h | 2 +- drivers/spi/cadence_qspi_apb.c | 10 +++++----- 3 files changed, 8 insertions(+), 7 deletions(-)
On SoCFPGA SoCkit: Tested-by: Marek Vasut marex@denx.de Acked-by: Marek Vasut marex@denx.de
Best regards, Marek Vasut
K2G SoC has a Cadence QSPI controller to communicate with NOR flash devices. Add DT nodes to support the same. Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor flash slave node for the same.
Signed-off-by: Vignesh R vigneshr@ti.com --- arch/arm/dts/k2g-evm.dts | 45 +++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/k2g.dtsi | 14 ++++++++++++++ 2 files changed, 59 insertions(+)
diff --git a/arch/arm/dts/k2g-evm.dts b/arch/arm/dts/k2g-evm.dts index 38ca7ae1b6b9..e95efd476707 100644 --- a/arch/arm/dts/k2g-evm.dts +++ b/arch/arm/dts/k2g-evm.dts @@ -55,3 +55,48 @@ }; }; }; + +&qspi { + status = "okay"; + + flash0: m25p80@0 { + compatible = "s25fl512s","spi-flash"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <96000000>; + #address-cells = <1>; + #size-cells = <1>; + tshsl-ns = <392>; + tsd2d-ns = <392>; + tchsh-ns = <100>; + tslch-ns = <100>; + block-size = <18>; + + + partition@0 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00000000 0x00100000>; + }; + partition@1 { + label = "QSPI.u-boot-env"; + reg = <0x00100000 0x00040000>; + }; + partition@2 { + label = "QSPI.skern"; + reg = <0x00140000 0x0040000>; + }; + partition@3 { + label = "QSPI.pmmc-firmware"; + reg = <0x00180000 0x0040000>; + }; + partition@4 { + label = "QSPI.kernel"; + reg = <0x001C0000 0x0800000>; + }; + partition@5 { + label = "QSPI.file-system"; + reg = <0x009C0000 0x3640000>; + }; + }; +}; diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi index 88b1a8e998ac..00cd49297336 100644 --- a/arch/arm/dts/k2g.dtsi +++ b/arch/arm/dts/k2g.dtsi @@ -23,6 +23,7 @@ spi1 = &spi1; spi2 = &spi2; spi3 = &spi3; + spi4 = &qspi; };
memory { @@ -84,6 +85,19 @@ bus_freq = <2500000>; };
+ qspi: qspi@2940000 { + compatible = "cadence,qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02940000 0x1000>, + <0x24000000 0x4000000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; + num-cs = <4>; + fifo-depth = <256>; + sram-size = <256>; + status = "disabled"; + }; + #include "k2g-netcp.dtsi"
pmmc: pmmc@2900000 {
On Wed, Apr 13, 2016 at 04:22:47PM +0530, Vignesh R wrote:
K2G SoC has a Cadence QSPI controller to communicate with NOR flash devices. Add DT nodes to support the same. Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor flash slave node for the same.
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
Enable Cadence QSPI controller support to use QSPI on K2G SoC. Also enable Spansion flash support to access s25fl512s flash present on K2G QSPI bus.
Signed-off-by: Vignesh R vigneshr@ti.com --- configs/k2g_evm_defconfig | 2 ++ include/configs/k2g_evm.h | 6 ++++++ 2 files changed, 8 insertions(+)
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig index c39e3cedf685..46a6df87d6f4 100644 --- a/configs/k2g_evm_defconfig +++ b/configs/k2g_evm_defconfig @@ -18,3 +18,5 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_DM_ETH=y CONFIG_REMOTEPROC_TI_POWER=y CONFIG_SYS_NS16550=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_BAR=y diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h index a2d2646eed72..c42ba42d7e0a 100644 --- a/include/configs/k2g_evm.h +++ b/include/configs/k2g_evm.h @@ -74,4 +74,10 @@ #define CONFIG_SF_DEFAULT_BUS 1 #define CONFIG_SF_DEFAULT_CS 0
+#ifndef CONFIG_SPL_BUILD +#define CONFIG_CADENCE_QSPI +#define CONFIG_CQSPI_REF_CLK 384000000 +#define CONFIG_CQSPI_DECODER 0x0 +#endif + #endif /* __CONFIG_K2G_EVM_H */
On Wed, Apr 13, 2016 at 04:22:48PM +0530, Vignesh R wrote:
Enable Cadence QSPI controller support to use QSPI on K2G SoC. Also enable Spansion flash support to access s25fl512s flash present on K2G QSPI bus.
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Tom Rini trini@konsulko.com
On 04/13/2016 12:52 PM, Vignesh R wrote:
This series adds support for Cadence QSPI controller present on K2G SoC.
The first patch extends AHB address to 32 bit as K2G has 32 bit AHB address. Second patch enable QUAD mode based on DT data instead of relying on config option. And last to patches add DT node and add configs to enable the driver.
Depends on [1] to enable SPI driver model support on K2G and [2] to support different bus frequencies for two different SPI controllers present on K2G EVM.
Are you OK if I wrap the first two patches into V11 of the Cadence QSPI submission and add your SoB to the submission?
[1]https://www.mail-archive.com/u-boot@lists.denx.de/msg209556.html [2]https://patchwork.ozlabs.org/patch/609947/
Vignesh R (4): spi: cadence_qspi_apb: Support 32 bit AHB address spi: cadence_quadspi: Enable QUAD mode based on DT data ARM: dts: K2G: Add support for QSPI controller defconfig: k2g_evm_defconfig: Enable Cadence QSPI controller
arch/arm/dts/k2g-evm.dts | 45 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/k2g.dtsi | 14 +++++++++++++ configs/k2g_evm_defconfig | 2 ++ drivers/spi/cadence_qspi.c | 3 ++- drivers/spi/cadence_qspi.h | 2 +- drivers/spi/cadence_qspi_apb.c | 15 +++++++------- include/configs/k2g_evm.h | 6 ++++++ 7 files changed, 77 insertions(+), 10 deletions(-)
On 13 April 2016 at 16:22, Vignesh R vigneshr@ti.com wrote:
This series adds support for Cadence QSPI controller present on K2G SoC.
The first patch extends AHB address to 32 bit as K2G has 32 bit AHB address. Second patch enable QUAD mode based on DT data instead of relying on config option. And last to patches add DT node and add configs to enable the driver.
Depends on [1] to enable SPI driver model support on K2G and [2] to support different bus frequencies for two different SPI controllers present on K2G EVM.
[1]https://www.mail-archive.com/u-boot@lists.denx.de/msg209556.html [2]https://patchwork.ozlabs.org/patch/609947/
Vignesh R (4): spi: cadence_qspi_apb: Support 32 bit AHB address spi: cadence_quadspi: Enable QUAD mode based on DT data ARM: dts: K2G: Add support for QSPI controller
Please rebase this?
defconfig: k2g_evm_defconfig: Enable Cadence QSPI controller
Reviewed-by: Jagan Teki jteki@openedev.com
Hi,
On 05/09/2016 08:04 PM, Jagan Teki wrote:
On 13 April 2016 at 16:22, Vignesh R vigneshr@ti.com wrote:
This series adds support for Cadence QSPI controller present on K2G SoC.
The first patch extends AHB address to 32 bit as K2G has 32 bit AHB address. Second patch enable QUAD mode based on DT data instead of relying on config option. And last to patches add DT node and add configs to enable the driver.
Depends on [1] to enable SPI driver model support on K2G and [2] to support different bus frequencies for two different SPI controllers present on K2G EVM.
[1]https://www.mail-archive.com/u-boot@lists.denx.de/msg209556.html [2]https://patchwork.ozlabs.org/patch/609947/
Vignesh R (4): spi: cadence_qspi_apb: Support 32 bit AHB address spi: cadence_quadspi: Enable QUAD mode based on DT data ARM: dts: K2G: Add support for QSPI controller
Please rebase this?
This series applies cleanly on current u-boot master provided dts changes from my earlier patch series [3] are picked up. [3] is required to support SPI DM on K2G. Could you please pick up the dependent series and then apply this?
[3] https://www.mail-archive.com/u-boot@lists.denx.de/msg211787.html (Convert davinci_spi to DM patch series)
defconfig: k2g_evm_defconfig: Enable Cadence QSPI controller
Reviewed-by: Jagan Teki jteki@openedev.com
participants (4)
-
Jagan Teki -
Marek Vasut -
Tom Rini -
Vignesh R