On 2023/2/24 05:03, Vasily Khoruzhick wrote:

SDHCI driver may attempt to set 26MHz clock, but clk_rk3568 will return error in this case. Apparently, SDHCI silently ignores the error and as a result eMMC initialization fails.

Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.

Signed-off-by: Vasily Khoruzhick anarsoul@gmail.com

Reviewed-by: Kever Yang kever.yang@rock-chips.com

Thanks, - Kever

---

drivers/clk/rockchip/clk_rk3568.c | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index c83ae22dc3..253b69504f 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1443,6 +1443,7 @@ static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv, switch (rate) { case OSC_HZ: case 26 * MHz:

• case 25 * MHz: src_clk = CLK_SDMMC_SEL_24M; break; case 400 * MHz:

@@ -1632,6 +1633,8 @@ static ulong rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate)

switch (rate) { case OSC_HZ:

• case 26 * MHz:
• case 25 * MHz: src_clk = CCLK_EMMC_SEL_24M; break; case 52 * MHz: