[PATCH 0/2] sunxi: v3s: add network support
Add network support for the V3s which only supports the internal PHY. Adding support was straight forward. The emac driver just needs the compatible string and some platform data and the clock driver needs to know the bits for the clock gating as well as the reset bits.
This was tested on a custom board.
Michael Walle (2): clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC net: sun8i_emac: add support for the V3s
drivers/clk/sunxi/clk_v3s.c | 6 ++++++ drivers/net/sun8i_emac.c | 7 +++++++ 2 files changed, 13 insertions(+)
Add the clock gate registers as well as the reset register bits for the EMAC and EPHY for the V3s. These are needed by the sun8i network driver.
Signed-off-by: Michael Walle mwalle@kernel.org --- drivers/clk/sunxi/clk_v3s.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 6524c13540e..0402d5ed190 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -17,6 +17,7 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), + [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
@@ -31,6 +32,8 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
+ [CLK_BUS_EPHY] = GATE(0x070, BIT(0)), + [CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), @@ -45,12 +48,15 @@ static struct ccu_reset v3s_resets[] = { [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), + [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[RST_BUS_TCON0] = RESET(0x2c4, BIT(4)), [RST_BUS_DE] = RESET(0x2c4, BIT(12)),
+ [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), + [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
On Mon, 13 May 2024 22:56:08 +0200 Michael Walle mwalle@kernel.org wrote:
Hi,
Add the clock gate registers as well as the reset register bits for the EMAC and EPHY for the V3s. These are needed by the sun8i network driver.
Signed-off-by: Michael Walle mwalle@kernel.org
Compared against the manual and the Linux driver:
Reviewed-by: Andre Przywara andre.przywara@arm.com
Thanks! Andre
drivers/clk/sunxi/clk_v3s.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c index 6524c13540e..0402d5ed190 100644 --- a/drivers/clk/sunxi/clk_v3s.c +++ b/drivers/clk/sunxi/clk_v3s.c @@ -17,6 +17,7 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
- [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
@@ -31,6 +32,8 @@ static struct ccu_clk_gate v3s_gates[] = { [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
@@ -45,12 +48,15 @@ static struct ccu_reset v3s_resets[] = { [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
[RST_BUS_EMAC] = RESET(0x2c0, BIT(17)), [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
[RST_BUS_TCON0] = RESET(0x2c4, BIT(4)), [RST_BUS_DE] = RESET(0x2c4, BIT(12)),
[RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
[RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
Add the compatible string for the emac found on the V3s SoC. The SoC only supports the internal PHY. There are no (R)MII signals on any pins.
Signed-off-by: Michael Walle mwalle@kernel.org --- drivers/net/sun8i_emac.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 8bff4fe9a9e..94bcd40acb8 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -893,6 +893,11 @@ static const struct emac_variant emac_variant_r40 = { .syscon_offset = 0x164, };
+static const struct emac_variant emac_variant_v3s = { + .syscon_offset = 0x30, + .soc_has_internal_phy = true, +}; + static const struct emac_variant emac_variant_a64 = { .syscon_offset = 0x30, .support_rmii = true, @@ -910,6 +915,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = { .data = (ulong)&emac_variant_h3 }, { .compatible = "allwinner,sun8i-r40-gmac", .data = (ulong)&emac_variant_r40 }, + { .compatible = "allwinner,sun8i-v3s-emac", + .data = (ulong)&emac_variant_v3s }, { .compatible = "allwinner,sun50i-a64-emac", .data = (ulong)&emac_variant_a64 }, { .compatible = "allwinner,sun50i-h6-emac",
On Mon, 13 May 2024 22:56:09 +0200 Michael Walle mwalle@kernel.org wrote:
Hi,
Add the compatible string for the emac found on the V3s SoC. The SoC only supports the internal PHY. There are no (R)MII signals on any pins.
Signed-off-by: Michael Walle mwalle@kernel.org
Nice, that seems indeed all we need for that SoC.
Reviewed-by: Andre Przywara andre.przywara@arm.com
Cheers, Andre
drivers/net/sun8i_emac.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 8bff4fe9a9e..94bcd40acb8 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -893,6 +893,11 @@ static const struct emac_variant emac_variant_r40 = { .syscon_offset = 0x164, };
+static const struct emac_variant emac_variant_v3s = {
- .syscon_offset = 0x30,
- .soc_has_internal_phy = true,
+};
static const struct emac_variant emac_variant_a64 = { .syscon_offset = 0x30, .support_rmii = true, @@ -910,6 +915,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = { .data = (ulong)&emac_variant_h3 }, { .compatible = "allwinner,sun8i-r40-gmac", .data = (ulong)&emac_variant_r40 },
- { .compatible = "allwinner,sun8i-v3s-emac",
.data = (ulong)&emac_variant_v3s },
Hi,
On Mon May 13, 2024 at 10:56 PM CEST, Michael Walle wrote:
Add network support for the V3s which only supports the internal PHY. Adding support was straight forward. The emac driver just needs the compatible string and some platform data and the clock driver needs to know the bits for the clock gating as well as the reset bits.
This was tested on a custom board.
Any news here?
-michael
Michael Walle (2): clk: sunxi: add EMAC and EPHY clocks and resets for the V3s SoC net: sun8i_emac: add support for the V3s
drivers/clk/sunxi/clk_v3s.c | 6 ++++++ drivers/net/sun8i_emac.c | 7 +++++++ 2 files changed, 13 insertions(+)
participants (2)
-
Andre Przywara -
Michael Walle