[U-Boot] [PATCH 1/2] ARM: OMAP4/5: Remove dead code against CONFIG_SYS_CLOCKS_ENABLE_ALL
The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code.
Signed-off-by: Jassi Brar jaswinder.singh@linaro.org --- Hi, The commit f3f98bb0 seems to suggest we want to move these settings into the kernel, but perhaps we should also evaluate the option of making these inits fully board specific but in u-boot?
Thanks.
arch/arm/cpu/armv7/omap-common/clocks-common.c | 47 ------------- arch/arm/cpu/armv7/omap4/clocks.c | 84 ----------------------- arch/arm/cpu/armv7/omap5/clocks.c | 87 ------------------------ arch/arm/include/asm/arch-omap4/clocks.h | 1 - arch/arm/include/asm/arch-omap5/clocks.h | 1 - 5 files changed, 0 insertions(+), 220 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index b1fd277..fc14465 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -326,49 +326,6 @@ static void setup_dplls(void) #endif }
-#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL -static void setup_non_essential_dplls(void) -{ - u32 abe_ref_clk; - const struct dpll_params *params; - - /* IVA */ - clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, - CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); - - params = get_iva_dpll_params(); - do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva"); - - /* Configure ABE dpll */ - params = get_abe_dpll_params(); -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; -#else - abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; - /* - * We need to enable some additional options to achieve - * 196.608MHz from 32768 Hz - */ - setbits_le32(&prcm->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| - CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| - CM_CLKMODE_DPLL_LPMODE_EN_MASK| - CM_CLKMODE_DPLL_REGM4XEN_MASK); - /* Spend 4 REFCLK cycles at each stage */ - clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, - CM_CLKMODE_DPLL_RAMP_RATE_MASK, - 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); -#endif - - /* Select the right reference clk */ - clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, - CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, - abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); - /* Lock the dpll */ - do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe"); -} -#endif - void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv) { u32 step; @@ -584,10 +541,6 @@ void prcm_init(void) enable_basic_clocks(); scale_vcores(); setup_dplls(); -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL - setup_non_essential_dplls(); - enable_non_essential_clocks(); -#endif break; default: break; diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 5bd0a88..b3fc652 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -431,87 +431,3 @@ void enable_basic_uboot_clocks(void) clk_modules_explicit_en_essential, 1); } - -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 *const clk_domains_non_essential[] = { - &prcm->cm_mpu_m3_clkstctrl, - &prcm->cm_ivahd_clkstctrl, - &prcm->cm_dsp_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sgx_clkstctrl, - &prcm->cm1_abe_clkstctrl, - &prcm->cm_c2c_clkstctrl, - &prcm->cm_cam_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sdma_clkstctrl, - 0 - }; - - u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_l3instr_l3_3_clkctrl, - &prcm->cm_l3instr_l3_instr_clkctrl, - &prcm->cm_l3instr_intrconn_wp1_clkctrl, - &prcm->cm_l3init_hsi_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_non_essential[] = { - &prcm->cm1_abe_aess_clkctrl, - &prcm->cm1_abe_pdm_clkctrl, - &prcm->cm1_abe_dmic_clkctrl, - &prcm->cm1_abe_mcasp_clkctrl, - &prcm->cm1_abe_mcbsp1_clkctrl, - &prcm->cm1_abe_mcbsp2_clkctrl, - &prcm->cm1_abe_mcbsp3_clkctrl, - &prcm->cm1_abe_slimbus_clkctrl, - &prcm->cm1_abe_timer5_clkctrl, - &prcm->cm1_abe_timer6_clkctrl, - &prcm->cm1_abe_timer7_clkctrl, - &prcm->cm1_abe_timer8_clkctrl, - &prcm->cm1_abe_wdt3_clkctrl, - &prcm->cm_l4per_gptimer9_clkctrl, - &prcm->cm_l4per_gptimer10_clkctrl, - &prcm->cm_l4per_gptimer11_clkctrl, - &prcm->cm_l4per_gptimer3_clkctrl, - &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, - &prcm->cm_l4per_mcbsp4_clkctrl, - &prcm->cm_l4per_mcspi2_clkctrl, - &prcm->cm_l4per_mcspi3_clkctrl, - &prcm->cm_l4per_mcspi4_clkctrl, - &prcm->cm_l4per_mmcsd3_clkctrl, - &prcm->cm_l4per_mmcsd4_clkctrl, - &prcm->cm_l4per_mmcsd5_clkctrl, - &prcm->cm_l4per_uart1_clkctrl, - &prcm->cm_l4per_uart2_clkctrl, - &prcm->cm_l4per_uart4_clkctrl, - &prcm->cm_wkup_keyboard_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_cam_iss_clkctrl, - &prcm->cm_cam_fdif_clkctrl, - &prcm->cm_dss_dss_clkctrl, - &prcm->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index eecfbad..6c5441f 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -405,90 +405,3 @@ void enable_basic_uboot_clocks(void) clk_modules_explicit_en_essential, 1); } - -/* - * Enable non-essential clock domains, modules and - * do some additional special settings needed - */ -void enable_non_essential_clocks(void) -{ - u32 *const clk_domains_non_essential[] = { - &prcm->cm_mpu_m3_clkstctrl, - &prcm->cm_ivahd_clkstctrl, - &prcm->cm_dsp_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sgx_clkstctrl, - &prcm->cm1_abe_clkstctrl, - &prcm->cm_c2c_clkstctrl, - &prcm->cm_cam_clkstctrl, - &prcm->cm_dss_clkstctrl, - &prcm->cm_sdma_clkstctrl, - 0 - }; - - u32 *const clk_modules_hw_auto_non_essential[] = { - &prcm->cm_mpu_m3_mpu_m3_clkctrl, - &prcm->cm_ivahd_ivahd_clkctrl, - &prcm->cm_ivahd_sl2_clkctrl, - &prcm->cm_dsp_dsp_clkctrl, - &prcm->cm_l3instr_l3_3_clkctrl, - &prcm->cm_l3instr_l3_instr_clkctrl, - &prcm->cm_l3instr_intrconn_wp1_clkctrl, - &prcm->cm_l3init_hsi_clkctrl, - &prcm->cm_l4per_hdq1w_clkctrl, - 0 - }; - - u32 *const clk_modules_explicit_en_non_essential[] = { - &prcm->cm1_abe_aess_clkctrl, - &prcm->cm1_abe_pdm_clkctrl, - &prcm->cm1_abe_dmic_clkctrl, - &prcm->cm1_abe_mcasp_clkctrl, - &prcm->cm1_abe_mcbsp1_clkctrl, - &prcm->cm1_abe_mcbsp2_clkctrl, - &prcm->cm1_abe_mcbsp3_clkctrl, - &prcm->cm1_abe_slimbus_clkctrl, - &prcm->cm1_abe_timer5_clkctrl, - &prcm->cm1_abe_timer6_clkctrl, - &prcm->cm1_abe_timer7_clkctrl, - &prcm->cm1_abe_timer8_clkctrl, - &prcm->cm1_abe_wdt3_clkctrl, - &prcm->cm_l4per_gptimer9_clkctrl, - &prcm->cm_l4per_gptimer10_clkctrl, - &prcm->cm_l4per_gptimer11_clkctrl, - &prcm->cm_l4per_gptimer3_clkctrl, - &prcm->cm_l4per_gptimer4_clkctrl, - &prcm->cm_l4per_mcspi2_clkctrl, - &prcm->cm_l4per_mcspi3_clkctrl, - &prcm->cm_l4per_mcspi4_clkctrl, - &prcm->cm_l4per_mmcsd3_clkctrl, - &prcm->cm_l4per_mmcsd4_clkctrl, - &prcm->cm_l4per_mmcsd5_clkctrl, - &prcm->cm_l4per_uart1_clkctrl, - &prcm->cm_l4per_uart2_clkctrl, - &prcm->cm_l4per_uart4_clkctrl, - &prcm->cm_wkup_keyboard_clkctrl, - &prcm->cm_wkup_wdtimer2_clkctrl, - &prcm->cm_cam_iss_clkctrl, - &prcm->cm_cam_fdif_clkctrl, - &prcm->cm_dss_dss_clkctrl, - &prcm->cm_sgx_sgx_clkctrl, - 0 - }; - - /* Enable optional functional clock for ISS */ - setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); - - /* Enable all optional functional clocks of DSS */ - setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); - - do_enable_clocks(clk_domains_non_essential, - clk_modules_hw_auto_non_essential, - clk_modules_explicit_en_non_essential, - 0); - - /* Put camera module in no sleep mode */ - clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, - CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << - MODULE_CLKCTRL_MODULEMODE_SHIFT); -} diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index be20fc0..eff7d02 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -753,7 +753,6 @@ void setup_post_dividers(u32 *const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); -void enable_non_essential_clocks(void); void do_enable_clocks(u32 *const *clk_domains, u32 *const *clk_modules_hw_auto, u32 *const *clk_modules_explicit_en, diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 5f1a7aa..4f387a7 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -726,7 +726,6 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv); void setup_post_dividers(u32 *const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); -void enable_non_essential_clocks(void); void enable_basic_uboot_clocks(void); void do_enable_clocks(u32 *const *clk_domains, u32 *const *clk_modules_hw_auto,
Hi,
On Tue, Aug 7, 2012 at 2:59 PM, Jassi Brar jaswinder.singh@linaro.org wrote:
The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code.
Signed-off-by: Jassi Brar jaswinder.singh@linaro.org
Hi, The commit f3f98bb0 seems to suggest we want to move these settings into the kernel, but perhaps we should also evaluate the option of making these inits fully board specific but in u-boot?
Thanks.
arch/arm/cpu/armv7/omap-common/clocks-common.c | 47 ------------- arch/arm/cpu/armv7/omap4/clocks.c | 84 ----------------------- arch/arm/cpu/armv7/omap5/clocks.c | 87 ------------------------ arch/arm/include/asm/arch-omap4/clocks.h | 1 - arch/arm/include/asm/arch-omap5/clocks.h | 1 - 5 files changed, 0 insertions(+), 220 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index b1fd277..fc14465 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -326,49 +326,6 @@ static void setup_dplls(void) #endif }
-#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL -static void setup_non_essential_dplls(void) -{
u32 abe_ref_clk;const struct dpll_params *params;/* IVA */clrsetbits_le32(&prcm->cm_bypclk_dpll_iva,CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);params = get_iva_dpll_params();do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");/* Configure ABE dpll */params = get_abe_dpll_params();-#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;-#else
abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;/** We need to enable some additional options to achieve* 196.608MHz from 32768 Hz*/setbits_le32(&prcm->cm_clkmode_dpll_abe,CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|CM_CLKMODE_DPLL_LPMODE_EN_MASK|CM_CLKMODE_DPLL_REGM4XEN_MASK);/* Spend 4 REFCLK cycles at each stage */clrsetbits_le32(&prcm->cm_clkmode_dpll_abe,CM_CLKMODE_DPLL_RAMP_RATE_MASK,1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);-#endif
/* Select the right reference clk */clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel,CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);/* Lock the dpll */do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");-} -#endif
void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv) { u32 step; @@ -584,10 +541,6 @@ void prcm_init(void) enable_basic_clocks(); scale_vcores(); setup_dplls(); -#ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
setup_non_essential_dplls();enable_non_essential_clocks();-#endif break; default: break; diff --git a/arch/arm/cpu/armv7/omap4/clocks.c b/arch/arm/cpu/armv7/omap4/clocks.c index 5bd0a88..b3fc652 100644 --- a/arch/arm/cpu/armv7/omap4/clocks.c +++ b/arch/arm/cpu/armv7/omap4/clocks.c @@ -431,87 +431,3 @@ void enable_basic_uboot_clocks(void) clk_modules_explicit_en_essential, 1); }
-/*
- Enable non-essential clock domains, modules and
- do some additional special settings needed
- */
-void enable_non_essential_clocks(void) -{
u32 *const clk_domains_non_essential[] = {&prcm->cm_mpu_m3_clkstctrl,&prcm->cm_ivahd_clkstctrl,&prcm->cm_dsp_clkstctrl,&prcm->cm_dss_clkstctrl,&prcm->cm_sgx_clkstctrl,&prcm->cm1_abe_clkstctrl,&prcm->cm_c2c_clkstctrl,&prcm->cm_cam_clkstctrl,&prcm->cm_dss_clkstctrl,&prcm->cm_sdma_clkstctrl,0};u32 *const clk_modules_hw_auto_non_essential[] = {&prcm->cm_l3instr_l3_3_clkctrl,&prcm->cm_l3instr_l3_instr_clkctrl,&prcm->cm_l3instr_intrconn_wp1_clkctrl,&prcm->cm_l3init_hsi_clkctrl,0};u32 *const clk_modules_explicit_en_non_essential[] = {&prcm->cm1_abe_aess_clkctrl,&prcm->cm1_abe_pdm_clkctrl,&prcm->cm1_abe_dmic_clkctrl,&prcm->cm1_abe_mcasp_clkctrl,&prcm->cm1_abe_mcbsp1_clkctrl,&prcm->cm1_abe_mcbsp2_clkctrl,&prcm->cm1_abe_mcbsp3_clkctrl,&prcm->cm1_abe_slimbus_clkctrl,&prcm->cm1_abe_timer5_clkctrl,&prcm->cm1_abe_timer6_clkctrl,&prcm->cm1_abe_timer7_clkctrl,&prcm->cm1_abe_timer8_clkctrl,&prcm->cm1_abe_wdt3_clkctrl,&prcm->cm_l4per_gptimer9_clkctrl,&prcm->cm_l4per_gptimer10_clkctrl,&prcm->cm_l4per_gptimer11_clkctrl,&prcm->cm_l4per_gptimer3_clkctrl,&prcm->cm_l4per_gptimer4_clkctrl,&prcm->cm_l4per_hdq1w_clkctrl,&prcm->cm_l4per_mcbsp4_clkctrl,&prcm->cm_l4per_mcspi2_clkctrl,&prcm->cm_l4per_mcspi3_clkctrl,&prcm->cm_l4per_mcspi4_clkctrl,&prcm->cm_l4per_mmcsd3_clkctrl,&prcm->cm_l4per_mmcsd4_clkctrl,&prcm->cm_l4per_mmcsd5_clkctrl,&prcm->cm_l4per_uart1_clkctrl,&prcm->cm_l4per_uart2_clkctrl,&prcm->cm_l4per_uart4_clkctrl,&prcm->cm_wkup_keyboard_clkctrl,&prcm->cm_wkup_wdtimer2_clkctrl,&prcm->cm_cam_iss_clkctrl,&prcm->cm_cam_fdif_clkctrl,&prcm->cm_dss_dss_clkctrl,&prcm->cm_sgx_sgx_clkctrl,0};/* Enable optional functional clock for ISS */setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);/* Enable all optional functional clocks of DSS */setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);do_enable_clocks(clk_domains_non_essential,clk_modules_hw_auto_non_essential,clk_modules_explicit_en_non_essential,0);/* Put camera module in no sleep mode */clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<MODULE_CLKCTRL_MODULEMODE_SHIFT);-} diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index eecfbad..6c5441f 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -405,90 +405,3 @@ void enable_basic_uboot_clocks(void) clk_modules_explicit_en_essential, 1); }
-/*
- Enable non-essential clock domains, modules and
- do some additional special settings needed
- */
-void enable_non_essential_clocks(void) -{
u32 *const clk_domains_non_essential[] = {&prcm->cm_mpu_m3_clkstctrl,&prcm->cm_ivahd_clkstctrl,&prcm->cm_dsp_clkstctrl,&prcm->cm_dss_clkstctrl,&prcm->cm_sgx_clkstctrl,&prcm->cm1_abe_clkstctrl,&prcm->cm_c2c_clkstctrl,&prcm->cm_cam_clkstctrl,&prcm->cm_dss_clkstctrl,&prcm->cm_sdma_clkstctrl,0};u32 *const clk_modules_hw_auto_non_essential[] = {&prcm->cm_mpu_m3_mpu_m3_clkctrl,&prcm->cm_ivahd_ivahd_clkctrl,&prcm->cm_ivahd_sl2_clkctrl,&prcm->cm_dsp_dsp_clkctrl,&prcm->cm_l3instr_l3_3_clkctrl,&prcm->cm_l3instr_l3_instr_clkctrl,&prcm->cm_l3instr_intrconn_wp1_clkctrl,&prcm->cm_l3init_hsi_clkctrl,&prcm->cm_l4per_hdq1w_clkctrl,0};u32 *const clk_modules_explicit_en_non_essential[] = {&prcm->cm1_abe_aess_clkctrl,&prcm->cm1_abe_pdm_clkctrl,&prcm->cm1_abe_dmic_clkctrl,&prcm->cm1_abe_mcasp_clkctrl,&prcm->cm1_abe_mcbsp1_clkctrl,&prcm->cm1_abe_mcbsp2_clkctrl,&prcm->cm1_abe_mcbsp3_clkctrl,&prcm->cm1_abe_slimbus_clkctrl,&prcm->cm1_abe_timer5_clkctrl,&prcm->cm1_abe_timer6_clkctrl,&prcm->cm1_abe_timer7_clkctrl,&prcm->cm1_abe_timer8_clkctrl,&prcm->cm1_abe_wdt3_clkctrl,&prcm->cm_l4per_gptimer9_clkctrl,&prcm->cm_l4per_gptimer10_clkctrl,&prcm->cm_l4per_gptimer11_clkctrl,&prcm->cm_l4per_gptimer3_clkctrl,&prcm->cm_l4per_gptimer4_clkctrl,&prcm->cm_l4per_mcspi2_clkctrl,&prcm->cm_l4per_mcspi3_clkctrl,&prcm->cm_l4per_mcspi4_clkctrl,&prcm->cm_l4per_mmcsd3_clkctrl,&prcm->cm_l4per_mmcsd4_clkctrl,&prcm->cm_l4per_mmcsd5_clkctrl,&prcm->cm_l4per_uart1_clkctrl,&prcm->cm_l4per_uart2_clkctrl,&prcm->cm_l4per_uart4_clkctrl,&prcm->cm_wkup_keyboard_clkctrl,&prcm->cm_wkup_wdtimer2_clkctrl,&prcm->cm_cam_iss_clkctrl,&prcm->cm_cam_fdif_clkctrl,&prcm->cm_dss_dss_clkctrl,&prcm->cm_sgx_sgx_clkctrl,0};/* Enable optional functional clock for ISS */setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);/* Enable all optional functional clocks of DSS */setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);do_enable_clocks(clk_domains_non_essential,clk_modules_hw_auto_non_essential,clk_modules_explicit_en_non_essential,0);/* Put camera module in no sleep mode */clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<MODULE_CLKCTRL_MODULEMODE_SHIFT);-} diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index be20fc0..eff7d02 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -753,7 +753,6 @@ void setup_post_dividers(u32 *const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); -void enable_non_essential_clocks(void); void do_enable_clocks(u32 *const *clk_domains, u32 *const *clk_modules_hw_auto, u32 *const *clk_modules_explicit_en, diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 5f1a7aa..4f387a7 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -726,7 +726,6 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv); void setup_post_dividers(u32 *const base, const struct dpll_params *params); u32 get_sys_clk_index(void); void enable_basic_clocks(void); -void enable_non_essential_clocks(void); void enable_basic_uboot_clocks(void); void do_enable_clocks(u32 *const *clk_domains, u32 *const *clk_modules_hw_auto,
But this would be useful in case some body wants to test things at the u-boot level or to go back to old configuration for testing ?
Thanks, Sricharan
On Tue, Aug 07, 2012 at 02:59:18PM +0530, Jassi Brar wrote:
The commit f3f98bb0 : "ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls" removed the config option aimed towards moving that stuff into kernel, which renders some code unreachable. Remove that code.
Signed-off-by: Jassi Brar jaswinder.singh@linaro.org
With a logical update to apply again, applied to u-boot-ti/master, thanks!
participants (3)
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Jassi Brar -
R, Sricharan -
Tom Rini