Added functions to enable and disable USB clocks which can be invoked during USB init and USB exit respectively.

Cc: Roger Quadros rogerq@ti.com Cc: Tero Kristo t-kristo@ti.com Cc: Nishanth Menon nm@ti.com Signed-off-by: Kishon Vijay Abraham I kishon@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 97 ++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 4 ++ 2 files changed, 101 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 809482c..94ad50e 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -622,6 +622,103 @@ void disable_edma3_clocks(void) } #endif

+#ifdef CONFIG_USB_DWC3 +void enable_usb_clocks(int index) +{ + u32 cm_l3init_usb_otg_ss_clkctrl = 0; + + if (index == 0) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; + /* Enable 960 MHz clock for dwc3 */ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Enable 32 KHz clock for dwc3 */ + setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + } else if (index == 1) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; + /* Enable 960 MHz clock for dwc3 */ + setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Enable 32 KHz clock for dwc3 */ + setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Enable 60 MHz clock for USB2PHY2 */ + setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, + L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); + } + + u32 const clk_domains_usb[] = { + 0 + }; + + u32 const clk_modules_hw_auto_usb[] = { + (*prcm)->cm_l3init_ocp2scp1_clkctrl, + cm_l3init_usb_otg_ss_clkctrl, + 0 + }; + + u32 const clk_modules_explicit_en_usb[] = { + 0 + }; + + do_enable_clocks(clk_domains_usb, + clk_modules_hw_auto_usb, + clk_modules_explicit_en_usb, + 1); +} + +void disable_usb_clocks(int index) +{ + u32 cm_l3init_usb_otg_ss_clkctrl = 0; + + if (index == 0) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; + /* Disable 960 MHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Disable 32 KHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + } else if (index == 1) { + cm_l3init_usb_otg_ss_clkctrl = + (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; + /* Disable 960 MHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, + OPTFCLKEN_REFCLK960M); + + /* Disable 32 KHz clock for dwc3 */ + clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, + USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); + + /* Disable 60 MHz clock for USB2PHY2 */ + clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, + L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); + } + + u32 const clk_domains_usb[] = { + 0 + }; + + u32 const clk_modules_disable[] = { + (*prcm)->cm_l3init_ocp2scp1_clkctrl, + cm_l3init_usb_otg_ss_clkctrl, + 0 + }; + + do_disable_clocks(clk_domains_usb, + clk_modules_disable, + 1); +} +#endif + const struct ctrl_ioregs ioregs_omap5430 = { .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8e3e243..d389743 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -591,6 +591,10 @@ u32 omap_ddr_clk(void); u32 get_sys_clk_index(void); void enable_basic_clocks(void); void enable_basic_uboot_clocks(void); + +void enable_usb_clocks(int index); +void disable_usb_clocks(int index); + void scale_vcores(struct vcores_data const *); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);

invoke enable_usb_clocks during board_usb_init and disable_usb_clocks during board_usb_exit to enable and disable clocks respectively.

Signed-off-by: Kishon Vijay Abraham I kishon@ti.com Reviewed-by: Tom Rini trini@konsulko.com --- board/ti/am43xx/board.c | 2 ++ board/ti/beagle_x15/board.c | 4 ++++ board/ti/dra7xx/evm.c | 2 ++ board/ti/omap5_uevm/evm.c | 2 ++ 4 files changed, 10 insertions(+)

diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 1454976..770726c 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -713,6 +713,7 @@ static struct ti_usb_phy_device usb_phy2_device = {

int board_usb_init(int index, enum usb_init_type init) { + enable_usb_clocks(index); switch (index) { case 0: if (init == USB_INIT_DEVICE) { @@ -759,6 +760,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) default: printf("Invalid Controller Index\n"); } + disable_usb_clocks(index);

return 0; } diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index bcf8cf2..042f9ab 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -356,10 +356,12 @@ static struct ti_usb_phy_device usb_phy2_device = {

int board_usb_init(int index, enum usb_init_type init) { + enable_usb_clocks(index); switch (index) { case 0: if (init == USB_INIT_DEVICE) { printf("port %d can't be used as device\n", index); + disable_usb_clocks(index); return -EINVAL; } else { usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; @@ -379,6 +381,7 @@ int board_usb_init(int index, enum usb_init_type init) usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; } else { printf("port %d can't be used as host\n", index); + disable_usb_clocks(index); return -EINVAL; }

@@ -405,6 +408,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) default: printf("Invalid Controller Index\n"); } + disable_usb_clocks(index); return 0; }

diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 4849694..04fc8ed 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -144,6 +144,7 @@ static struct ti_usb_phy_device usb_phy2_device = {

int board_usb_init(int index, enum usb_init_type init) { + enable_usb_clocks(index); switch (index) { case 0: if (init == USB_INIT_DEVICE) { @@ -190,6 +191,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) default: printf("Invalid Controller Index\n"); } + disable_usb_clocks(index); return 0; }

diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index d0d0e0e..659877c 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -95,6 +95,7 @@ int board_usb_init(int index, enum usb_init_type init) usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; }

+ enable_usb_clocks(index); ti_usb_phy_uboot_init(&usb_phy_device); dwc3_omap_uboot_init(&usb_otg_ss_glue); dwc3_uboot_init(&usb_otg_ss); @@ -112,6 +113,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) ti_usb_phy_uboot_exit(index); dwc3_uboot_exit(index); dwc3_omap_uboot_exit(index); + disable_usb_clocks(index);

return 0; }

Now that we have separate function to enable USB clocks, remove enabling USB clocks from enable_basic_clocks(). Now board_usb_init() should take care to invoke enable_usb_clocks() for enabling USB clocks.

Signed-off-by: Kishon Vijay Abraham I kishon@ti.com --- arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 12 ------------ arch/arm/cpu/armv7/omap5/hw_data.c | 30 ------------------------------ 2 files changed, 42 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index cad8d46..5c2a2ab 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -111,22 +111,10 @@ void enable_basic_clocks(void) &cmper->emifclkctrl, &cmper->otfaemifclkctrl, &cmper->qspiclkctrl, - &cmper->usb0clkctrl, - &cmper->usbphyocp2scp0clkctrl, - &cmper->usb1clkctrl, - &cmper->usbphyocp2scp1clkctrl, &cmper->spi0clkctrl, 0 };

- setbits_le32(&cmper->usb0clkctrl, - USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); - setbits_le32(&cmwkup->usbphy0clkctrl, - USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); - setbits_le32(&cmper->usb1clkctrl, - USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); - setbits_le32(&cmwkup->usbphy1clkctrl, - USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K); do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);

/* Select the Master osc clk as Timer2 clock source */ diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 94ad50e..5805f1f 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -460,13 +460,6 @@ void enable_basic_clocks(void) (*prcm)->cm_l4per_gpio6_clkctrl, (*prcm)->cm_l4per_gpio7_clkctrl, (*prcm)->cm_l4per_gpio8_clkctrl, -#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) - (*prcm)->cm_l3init_ocp2scp1_clkctrl, - (*prcm)->cm_l3init_usb_otg_ss1_clkctrl, -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - (*prcm)->cm_l3init_usb_otg_ss2_clkctrl, -#endif -#endif 0 };

@@ -498,29 +491,6 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK);

-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) - /* Enable 960 MHz clock for dwc3 */ - setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, - OPTFCLKEN_REFCLK960M); - - /* Enable 32 KHz clock for dwc3 */ - setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) - /* Enable 960 MHz clock for dwc3 */ - setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, - OPTFCLKEN_REFCLK960M); - - /* Enable 32 KHz clock for dwc3 */ - setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); - - /* Enable 60 MHz clock for USB2PHY2 */ - setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, - L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); -#endif -#endif - /* Set the correct clock dividers for mmc */ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_DIV_MASK);