Hi,

looking at the schematics and reference design for smcs 91c111 I found out that our hardware designer made an error by pulling LCLK pin of LAN91c111 eth controller low instead high (as datasheet suggests if using async transfer mode).

Could this lead to potential problems in combination with pxa255 ? He also reports that they had the same design on older platform with arm sa1100 and it was doing just fine.

I'm digging through network stuff and my hardware for any errors/faults and trying to eliminate irelevant stuff.

regards, himba