[PATCH 1/2] net: pcnet: Replace mips-specific accessors
Replace mips-specific UNCACHED_SDRAM() macro with standard map_physmem(), which permits the driver to work on other systems than mips.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com --- drivers/net/pcnet.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 59241c95bc..e7d6c8d714 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -332,7 +332,9 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) addr = (unsigned long)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc)); flush_dcache_range(addr, addr + sizeof(*lp->uc)); - addr = UNCACHED_SDRAM(addr); + addr = (unsigned long)map_physmem(addr, + roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN), + MAP_NOCACHE); lp->uc = (struct pcnet_uncached_priv *)addr;
addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
Replace the PCI IO access with PCI memory access, the card supports both, but the former does not work with QEMU SH4.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com --- Note: It would be good to test this on the mips malta --- drivers/net/pcnet.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index e7d6c8d714..34a5a16cfe 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -179,14 +179,14 @@ int pcnet_initialize(bd_t *bis) /* * Setup the PCI device. */ - pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar); - dev->iobase = pci_io_to_phys(devbusfn, bar); + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar); + dev->iobase = pci_mem_to_phys(devbusfn, bar); dev->iobase &= ~0xf;
PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ", dev->name, devbusfn, (unsigned long)dev->iobase);
- command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; + command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; pci_write_config_word(devbusfn, PCI_COMMAND, command); pci_read_config_word(devbusfn, PCI_COMMAND, &status); if ((status & command) != command) {
+cc Paul
Am 18.04.20 um 05:15 schrieb Marek Vasut:
Replace the PCI IO access with PCI memory access, the card supports both, but the former does not work with QEMU SH4.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com
Note: It would be good to test this on the mips malta
I can only test with Qemu. Maybe Paul could ack or test?
drivers/net/pcnet.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index e7d6c8d714..34a5a16cfe 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -179,14 +179,14 @@ int pcnet_initialize(bd_t *bis) /* * Setup the PCI device. */
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);dev->iobase = pci_io_to_phys(devbusfn, bar);
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);dev->iobase = pci_mem_to_phys(devbusfn, bar);dev->iobase &= ~0xf;
PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ", dev->name, devbusfn, (unsigned long)dev->iobase);
command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
Hi Marek,
Am 18.04.20 um 05:15 schrieb Marek Vasut:
Replace the PCI IO access with PCI memory access, the card supports both, but the former does not work with QEMU SH4.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com
Note: It would be good to test this on the mips malta
drivers/net/pcnet.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index e7d6c8d714..34a5a16cfe 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -179,14 +179,14 @@ int pcnet_initialize(bd_t *bis) /* * Setup the PCI device. */
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar);dev->iobase = pci_io_to_phys(devbusfn, bar);
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);dev->iobase = pci_mem_to_phys(devbusfn, bar);
this breaks Malta with qemu-mips:
U-Boot 2020.07-rc1-00103-gc6df21e36e (May 02 2020 - 16:02:48 +0200)
Board: MIPS Malta CoreLV DRAM: 256 MiB Flash: 4 MiB *** Warning - bad CRC, using default environment
In: serial@3f8 Out: serial@3f8 Err: serial@3f8 Net: Ooops: $ 0 : 00000000 00000000 b8000014 00000000 $ 4 : ca020014 00000001 00009800 0000000c $ 8 : 00000013 8ff7df10 00000013 bbe00000 $12 : 00000000 12020000 8ff801a0 00000200 $16 : 8ffa0898 00009800 00000000 8fff5afc $20 : 8ffda63c 8ffda5b0 00000000 00000000 $24 : 8ff804c8 8ffd89f0 $28 : 00000000 8ff7df58 803ffb40 8ffdaaa0 Hi : 00000026 Lo : 0378fe15 epc : 8ffda5a4 (text be01a5a4) ra : 8ffdaaa0 (text be01aaa0) Status: 00000006 Cause : 00000408 (ExcCode 02) BadVA : 00000000 PrId : 00019300 ### ERROR ### Please RESET the board ### QEMU: Terminated
Contrary to SH there is a difference between memory access and IO access on MIPS. So you have to replace also all inw()/outw() with readw()/writew() like so:
static u16 pcnet_read_csr(struct eth_device *dev, int index) { - writew(index, dev->iobase + PCNET_RAP); - return readw(dev->iobase + PCNET_RDP); + void __iomem *base = (void __iomem *)dev->iobase; + writew(index, base + PCNET_RAP); + return readw(base + PCNET_RDP); }
The separate *base pointer is to satisfy the type checks and to prevent gcc warnings.
With the changed IO primitives network still works in qemu-mips. As you already sent a pull request with this patch included, shall I send a follow-up patch?
U-Boot 2020.07-rc1-00105-g527a088ba3-dirty (May 02 2020 - 16:46:30 +0200)
Board: MIPS Malta CoreLV DRAM: 256 MiB Flash: 4 MiB *** Warning - bad CRC, using default environment
In: serial@3f8 Out: serial@3f8 Err: serial@3f8 Net: pcnet_initialize... pcnet#0: devbusfn=0x9800 iobase=0x12020000: AMD PCnet/PCI II 79C970A pcnet#0 IDE: Bus 0: not available malta # dhcp foo pcnet#0: pcnet_halt... pcnet#0: pcnet_init... Rx0: base=0xc00bfa0f buf_length=0xf8f9 status=0x80 Rx1: base=0xcc11fa0f buf_length=0xf8f9 status=0x80 Rx2: base=0xd817fa0f buf_length=0xf8f9 status=0x80 Rx3: base=0xe41dfa0f buf_length=0xf8f9 status=0x80 Init block at 0xaffa0b50: MAC 52 54 00 12 34 56 tlen_rlen=0x2000 rx_ring=0xbfa0f tx_ring=0x400bfa0f BOOTP broadcast 1 Tx0: 342 bytes from 0x8fff8dc0 done Tx0: 342 bytes from 0x8fff8dc0 done Rx0: 590 bytes from 0x8ffa0bc0 DHCP client bound to address 10.0.2.15 (4 ms) Using pcnet#0 device TFTP from server 10.0.2.2; our IP address is 10.0.2.15 Filename 'foo'. Load address: 0x81000000 Loading: Tx0: 42 bytes from 0x8fff86c0 done Rx1: 590 bytes from 0x8ffa11cc Tx0: 77 bytes from 0x8fff8dc0 done Rx2: 64 bytes from 0x8ffa17d8 Tx0: 46 bytes from 0x8fff8dc0 done Rx3: 60 bytes from 0x8ffa1de4 #Tx0: 46 bytes from 0x8fff8dc0 done
0 Bytes/s done Rx0: 60 bytes from 0x8ffa0bc0 pcnet#0: pcnet_halt...
Am 02.05.20 um 17:00 schrieb Daniel Schwierzeck:
Hi Marek,
Am 18.04.20 um 05:15 schrieb Marek Vasut:
Replace the PCI IO access with PCI memory access, the card supports both, but the former does not work with QEMU SH4.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com
Note: It would be good to test this on the mips malta
drivers/net/pcnet.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
...
Contrary to SH there is a difference between memory access and IO access on MIPS. So you have to replace also all inw()/outw() with readw()/writew() like so:
static u16 pcnet_read_csr(struct eth_device *dev, int index) {
writew(index, dev->iobase + PCNET_RAP);return readw(dev->iobase + PCNET_RDP);
void __iomem *base = (void __iomem *)dev->iobase;writew(index, base + PCNET_RAP);return readw(base + PCNET_RDP);}
sorry wrong diff, I meant:
static u16 pcnet_read_csr(struct eth_device *dev, int index) { - outw(index, dev->iobase + PCNET_RAP); - return inw(dev->iobase + PCNET_RDP); + void __iomem *base = (void __iomem *)dev->iobase; + writew(index, base + PCNET_RAP); + return readw(base + PCNET_RDP); }
On 5/2/20 5:03 PM, Daniel Schwierzeck wrote:
Am 02.05.20 um 17:00 schrieb Daniel Schwierzeck:
Hi Marek,
Am 18.04.20 um 05:15 schrieb Marek Vasut:
Replace the PCI IO access with PCI memory access, the card supports both, but the former does not work with QEMU SH4.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com
Note: It would be good to test this on the mips malta
drivers/net/pcnet.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
...
Contrary to SH there is a difference between memory access and IO access on MIPS. So you have to replace also all inw()/outw() with readw()/writew() like so:
static u16 pcnet_read_csr(struct eth_device *dev, int index) {
writew(index, dev->iobase + PCNET_RAP);return readw(dev->iobase + PCNET_RDP);
void __iomem *base = (void __iomem *)dev->iobase;writew(index, base + PCNET_RAP);return readw(base + PCNET_RDP);}
sorry wrong diff, I meant:
static u16 pcnet_read_csr(struct eth_device *dev, int index) {
outw(index, dev->iobase + PCNET_RAP);return inw(dev->iobase + PCNET_RDP);
void __iomem *base = (void __iomem *)dev->iobase;writew(index, base + PCNET_RAP);return readw(base + PCNET_RDP);}
I'm CCing Tom. He didn't pick the PR yet. If you want to send it as separate patch, fine by me, maybe Tom can pick that one right after the PR ; or I can squash it into the PR. I think the former would be easier.
Am 18.04.20 um 05:15 schrieb Marek Vasut:
Replace mips-specific UNCACHED_SDRAM() macro with standard map_physmem(), which permits the driver to work on other systems than mips.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Joe Hershberger joe.hershberger@ni.com
drivers/net/pcnet.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com
BTW: after this patch, arch/mips/lib/bootm.c is the only user of UNCACHED_SDRAM. I'll prepare a patch to remove that old macro entirely.
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 59241c95bc..e7d6c8d714 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -332,7 +332,9 @@ static int pcnet_init(struct eth_device *dev, bd_t *bis) addr = (unsigned long)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc)); flush_dcache_range(addr, addr + sizeof(*lp->uc));
addr = UNCACHED_SDRAM(addr);
addr = (unsigned long)map_physmem(addr,roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),MAP_NOCACHE);lp->uc = (struct pcnet_uncached_priv *)addr;
addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
participants (2)
-
Daniel Schwierzeck -
Marek Vasut