[U-Boot] [PATCH 0/7] powerpc, 8xx: Modernise the 8xx
This patchset modernises the resurrected 8xx.
Christophe Leroy (7): powerpc, 8xx: move specific reginfo powerpc, 8xx: Implement GLL2 ERRATA powerpc, 8xx: Properly set CPM frequency in the device tree powerpc, 8xx: Migrate to Kconfig powerpc, 8xx: move FEC Ethernet driver in drivers/net powerpc, 8xx: move SPI driver to drivers/spi/ powerpc, 8xx: move Serial driver to drivers/serial/
README | 49 ------- arch/powerpc/cpu/mpc8xx/Kconfig | 147 +++++++++++++++++++++ arch/powerpc/cpu/mpc8xx/Makefile | 4 +- arch/powerpc/cpu/mpc8xx/cpu.c | 2 +- arch/powerpc/cpu/mpc8xx/cpu_init.c | 12 +- arch/powerpc/cpu/mpc8xx/fdt.c | 2 + {cmd => arch/powerpc/cpu/mpc8xx}/reginfo.c | 30 +---- arch/powerpc/include/asm/ppc.h | 5 - arch/powerpc/lib/Kconfig | 1 + arch/powerpc/lib/immap.c | 4 - cmd/reginfo.c | 54 +------- drivers/i2c/soft_i2c.c | 2 +- drivers/net/Kconfig | 58 ++++++++ drivers/net/Makefile | 1 + .../cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c | 26 +--- drivers/serial/Kconfig | 72 ++++++++++ drivers/serial/Makefile | 1 + .../serial.c => drivers/serial/serial_mpc8xx.c | 15 --- drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + .../cpu/mpc8xx/spi.c => drivers/spi/mpc8xx_spi.c | 3 - scripts/config_whitelist.txt | 24 ---- 22 files changed, 310 insertions(+), 209 deletions(-) copy {cmd => arch/powerpc/cpu/mpc8xx}/reginfo.c (78%) rename arch/powerpc/cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c (96%) rename arch/powerpc/cpu/mpc8xx/serial.c => drivers/serial/serial_mpc8xx.c (97%) rename arch/powerpc/cpu/mpc8xx/spi.c => drivers/spi/mpc8xx_spi.c (99%)
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr --- This serie applies after the patch "[v5] powerpc: Partialy restore core of mpc8xx"
arch/powerpc/cpu/mpc8xx/Makefile | 1 + {cmd => arch/powerpc/cpu/mpc8xx}/reginfo.c | 30 +---------------- cmd/reginfo.c | 54 ++---------------------------- 3 files changed, 4 insertions(+), 81 deletions(-) copy {cmd => arch/powerpc/cpu/mpc8xx}/reginfo.c (78%)
diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index af1f87cb6f..db2f5ecd47 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -14,6 +14,7 @@ obj-y += cpu_init.o obj-y += fec.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-y += interrupts.o +obj-$(CONFIG_CMD_REGINFO) += reginfo.o obj-y += serial.o obj-y += speed.o obj-y += spi.o diff --git a/cmd/reginfo.c b/arch/powerpc/cpu/mpc8xx/reginfo.c similarity index 78% copy from cmd/reginfo.c copy to arch/powerpc/cpu/mpc8xx/reginfo.c index 96a7542d2d..b5a962431e 100644 --- a/cmd/reginfo.c +++ b/arch/powerpc/cpu/mpc8xx/reginfo.c @@ -6,19 +6,10 @@ */
#include <common.h> -#include <command.h> -#if defined(CONFIG_8xx) #include <mpc8xx.h> -#elif defined (CONFIG_MPC86xx) -extern void mpc86xx_reginfo(void); -#elif defined(CONFIG_MPC85xx) -extern void mpc85xx_reginfo(void); -#endif
-static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]) +void mpc8xx_reginfo(void) { -#if defined(CONFIG_8xx) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; volatile sysconf8xx_t *sysconf = &immap->im_siu_conf; @@ -70,23 +61,4 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, /* * May be some CPM info here? */ - -#elif defined(CONFIG_MPC86xx) - mpc86xx_reginfo(); - -#elif defined(CONFIG_MPC85xx) - mpc85xx_reginfo(); -#endif - - return 0; } - - /**************************************************/ - -#if defined(CONFIG_CMD_REGINFO) -U_BOOT_CMD( - reginfo, 2, 1, do_reginfo, - "print register information", - "" -); -#endif diff --git a/cmd/reginfo.c b/cmd/reginfo.c index 96a7542d2d..5800bb5604 100644 --- a/cmd/reginfo.c +++ b/cmd/reginfo.c @@ -8,7 +8,7 @@ #include <common.h> #include <command.h> #if defined(CONFIG_8xx) -#include <mpc8xx.h> +extern void mpc8xx_reginfo(void); #elif defined (CONFIG_MPC86xx) extern void mpc86xx_reginfo(void); #elif defined(CONFIG_MPC85xx) @@ -19,57 +19,7 @@ static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #if defined(CONFIG_8xx) - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile sysconf8xx_t *sysconf = &immap->im_siu_conf; - volatile sit8xx_t *timers = &immap->im_sit; - - /* Hopefully more PowerPC knowledgable people will add code to display - * other useful registers - */ - - printf ("\nSystem Configuration registers\n" - - "\tIMMR\t0x%08X\n", get_immr(0)); - - printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr); - printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr); - - printf("\tSWT\t0x%08X", sysconf->sc_swt); - printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr); - - printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", - sysconf->sc_sipend, sysconf->sc_simask); - printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n", - sysconf->sc_siel, sysconf->sc_sivec); - printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n", - sysconf->sc_tesr, sysconf->sc_sdcr); - - printf ("Memory Controller Registers\n" - - "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); - printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4); - printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5); - printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6); - printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7); - printf ("\n" - "\tmamr\t0x%08X\tmbmr\t0x%08X \n", - memctl->memc_mamr, memctl->memc_mbmr ); - printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n", - memctl->memc_mstat, memctl->memc_mptpr ); - printf("\tmdr\t0x%08X \n", memctl->memc_mdr); - - printf ("\nSystem Integration Timers\n" - "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", - timers->sit_tbscr, timers->sit_rtcsc); - printf("\tPISCR\t0x%08X \n", timers->sit_piscr); - - /* - * May be some CPM info here? - */ + mpc8xx_reginfo();
#elif defined(CONFIG_MPC86xx) mpc86xx_reginfo();
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr --- arch/powerpc/cpu/mpc8xx/cpu_init.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 0f935aff9e..e8045cc5c6 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -55,6 +55,16 @@ void cpu_init_f (volatile immap_t * immr) reg |= CONFIG_SYS_SCCR; immr->im_clkrst.car_sccr = reg;
+ /* BUG MPC866 GLL2 consideration */ + reg = immr->im_clkrst.car_sccr; + /* probably we use the mode 1:2:1 */ + if ((reg & 0x00060000) == 0x00020000) { + reg &= ~0x00060000; + immr->im_clkrst.car_sccr = reg; + reg |= 0x00020000; + immr->im_clkrst.car_sccr = reg; + } + /* PLL (CPU clock) settings (15-30) */
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
Dear Christophe Leroy,
In message 8947f895b86efe0396b1825998a64a3340fff597.1498751837.git.christophe.leroy@c-s.fr you wrote:
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr
arch/powerpc/cpu/mpc8xx/cpu_init.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 0f935aff9e..e8045cc5c6 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -55,6 +55,16 @@ void cpu_init_f (volatile immap_t * immr) reg |= CONFIG_SYS_SCCR; immr->im_clkrst.car_sccr = reg;
- /* BUG MPC866 GLL2 consideration */
- reg = immr->im_clkrst.car_sccr;
- /* probably we use the mode 1:2:1 */
- if ((reg & 0x00060000) == 0x00020000) {
reg &= ~0x00060000;immr->im_clkrst.car_sccr = reg;reg |= 0x00020000;immr->im_clkrst.car_sccr = reg;- }
This is an excellent example for future situations, so thanks a lot for bringing it up early.
The code you are adding here violates basic (modern) programming standards. To access device registers, proper I/O accessors must be used. In this case the code should use the clrsetbits_be32() macro.
Strictly speaking, you should receive a full NAK on this code.
You may now argument that the surrounding code is full of similar examples of obsolete, broken code, and you are just following this (bad) example.
The standard reply to this would be: well, while you are modifying this file, please clean up the other ocurrences of such bad code as well.
Are you aware of this process? How do you think to handle such situations in the future?
What I really, really am scared of is that you might follow your employer's requirements ("new version only introduces a reduced amount of modifications in source code") instead of following your duties as a custodian (cleaning up the code to meet current programming standards).
Can you please make an explixit statement here how you are going to handle this in the future? [And again, schedule is important, too.]
Best regards,
Wolfgang Denk
Le 30/06/2017 à 15:11, Wolfgang Denk a écrit :
Dear Christophe Leroy,
In message 8947f895b86efe0396b1825998a64a3340fff597.1498751837.git.christophe.leroy@c-s.fr you wrote:
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr
arch/powerpc/cpu/mpc8xx/cpu_init.c | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index 0f935aff9e..e8045cc5c6 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -55,6 +55,16 @@ void cpu_init_f (volatile immap_t * immr) reg |= CONFIG_SYS_SCCR; immr->im_clkrst.car_sccr = reg;
- /* BUG MPC866 GLL2 consideration */
- reg = immr->im_clkrst.car_sccr;
- /* probably we use the mode 1:2:1 */
- if ((reg & 0x00060000) == 0x00020000) {
reg &= ~0x00060000;immr->im_clkrst.car_sccr = reg;reg |= 0x00020000;immr->im_clkrst.car_sccr = reg;- }
This is an excellent example for future situations, so thanks a lot for bringing it up early.
The code you are adding here violates basic (modern) programming standards. To access device registers, proper I/O accessors must be used. In this case the code should use the clrsetbits_be32() macro.
Oh right, that's the way it is done in Linux Kernel, I used to be surprised it was not that way in U-Boot. If it is like this now, that's good.
Strictly speaking, you should receive a full NAK on this code.
You may now argument that the surrounding code is full of similar examples of obsolete, broken code, and you are just following this (bad) example.
No, I may argument that the code I'm submitting is not new code but code that was written in 2010, and maybe even before, when we were using ppcboot.
The standard reply to this would be: well, while you are modifying this file, please clean up the other ocurrences of such bad code as well.
Are you aware of this process? How do you think to handle such situations in the future?
I am now :) I'll keep it in mind for the future.
What I really, really am scared of is that you might follow your employer's requirements ("new version only introduces a reduced amount of modifications in source code") instead of following your duties as a custodian (cleaning up the code to meet current programming standards).
Do not worry. Any justified improvement is worth it. My only employer's requirement is "make sure it will be accepted by Air Trafic Control authorities". All is a matter of justification and I'm not worried about it as far as I manage to keep commits focussed on only one thing. U-boot General Patch Submission Rules states 'Changes that contain different, unrelated modifications shall be submitted as separate patches, one patch per changeset', so this is not in contradiction with my needs.
What the auditors really focus on is the deltas between the COTS (ie the official U-boot release) and the sources we use for them. So it is of our interest to have our changes/fixes properly merged into U-boot.
Can you please make an explixit statement here how you are going to handle this in the future? [And again, schedule is important, too.]
My plan is to convert to the use of IO accessors during this week.
Best regards Christophe
Best regards,
Wolfgang Denk
Dear Christophe,
In message 556dc687-0331-40a6-4260-9f78f6131e47@c-s.fr you wrote:
The code you are adding here violates basic (modern) programming standards. To access device registers, proper I/O accessors must be used. In this case the code should use the clrsetbits_be32() macro.
Oh right, that's the way it is done in Linux Kernel, I used to be surprised it was not that way in U-Boot. If it is like this now, that's good.
It's been here for ages as well. It's only really ancient (and not well maintained) code that does not use it yet.
You may now argument that the surrounding code is full of similar examples of obsolete, broken code, and you are just following this (bad) example.
No, I may argument that the code I'm submitting is not new code but code that was written in 2010, and maybe even before, when we were using ppcboot.
So what? You are submitting it today, to be included into curent mainline.
Are you aware of this process? How do you think to handle such situations in the future?
I am now :) I'll keep it in mind for the future.
The Correct Thing (TM) to do here is to submit two patches: a first one to convert the file in question to using I/O accessors, and a second one to extend the code as needed.
What the auditors really focus on is the deltas between the COTS (ie the official U-boot release) and the sources we use for them. So it is of our interest to have our changes/fixes properly merged into U-boot.
I'm perplexed. If that was the case then why did you never care to minimize such differences?
Can you please make an explixit statement here how you are going to handle this in the future? [And again, schedule is important, too.]
My plan is to convert to the use of IO accessors during this week.
Thanks.
Best regards,
Wolfgang Denk
For processors whose core runs at twice the bus frequency, the fallback frequency calculation in Linux provides a wrong result. Therefore, U-boot needs to pass the correct value.
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr --- arch/powerpc/cpu/mpc8xx/fdt.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c index 34d36478d3..5688671fba 100644 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ b/arch/powerpc/cpu/mpc8xx/fdt.c @@ -20,6 +20,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) "bus-frequency", bd->bi_busfreq, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency", bd->bi_intfreq, 1); + do_fixup_by_compat_u32(blob, "fsl,pq1-soc", "clock-frequency", + bd->bi_intfreq, 1); do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", gd->arch.brg_clk, 1);
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr --- README | 15 ---- arch/powerpc/cpu/mpc8xx/Kconfig | 147 +++++++++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xx/cpu_init.c | 2 +- arch/powerpc/cpu/mpc8xx/fec.c | 8 +- arch/powerpc/include/asm/ppc.h | 5 -- arch/powerpc/lib/Kconfig | 1 + arch/powerpc/lib/immap.c | 4 - drivers/i2c/soft_i2c.c | 2 +- scripts/config_whitelist.txt | 11 --- 9 files changed, 154 insertions(+), 41 deletions(-)
diff --git a/README b/README index fd8465085b..3d9aad5c9c 100644 --- a/README +++ b/README @@ -328,9 +328,6 @@ The following options need to be configured: multiple fs option at one time for marvell soc family
-- 8xx CPU Options: (if using an MPC8xx CPU) - CONFIG_8xx_GCLK_FREQ - CPU clock - - 85xx CPU Options: CONFIG_SYS_PPC64
@@ -3993,16 +3990,6 @@ Low Level (hardware related) configuration options: point to an otherwise UNUSED address space between the top of RAM and the start of the PCI space.
-- CONFIG_SYS_SIUMCR: SIU Module Configuration (11-6) - -- CONFIG_SYS_SYPCR: System Protection Control (11-9) - -- CONFIG_SYS_TBSCR: Time Base Status and Control (11-26) - -- CONFIG_SYS_PISCR: Periodic Interrupt Status and Control (11-31) - -- CONFIG_SYS_PLPRCR: PLL, Low-Power, and Reset Control Register (15-30) - - CONFIG_SYS_SCCR: System Clock and reset Control Register (15-27)
- CONFIG_SYS_OR_TIMING_SDRAM: @@ -4011,8 +3998,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_MAMR_PTA: periodic timer for refresh
-- CONFIG_SYS_DER: Debug Event Register (37-47) - - FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM, CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM, diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index a425cba8aa..d30d5af3a1 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -10,4 +10,151 @@ choice
endchoice
+choice + prompt "CPU select" + default MPC866 + +config MPC866 + bool "MPC866" + +config MPC885 + bool "MPC885" + +endchoice + +config 8xx_GCLK_FREQ + int "CPU GCLK Frequency" + +comment "Configuration Registers" + +config SYS_SIUMCR + hex "SIUMCR register" + help + SIU Module Configuration (11-6) + +config SYS_SYPCR + hex "SYPCR register" + help + System Protection Control (11-9) + +config SYS_TBSCR + hex "TBSCR register" + help + Time Base Status and Control (11-26) + +config SYS_PISCR + hex "PISCR register" + help + Periodic Interrupt Status and Control (11-31) + +config SYS_PLPRCR_BOOL + bool "Customise PLPRCR" + +config SYS_PLPRCR + hex "PLPRCR register" + depends on SYS_PLPRCR_BOOL + help + PLL, Low-Power, and Reset Control Register (15-30) + +config SYS_SCCR + hex "SCCR register" + help + System Clock and reset Control Register (15-27) + +config SYS_SCCR_MASK + hex "MASK for setting SCCR register" + +config SYS_DER + hex "DER register" + help + Debug Event Register (37-47) + +comment "Memory mapping" + +config SYS_BR0_PRELIM + hex "Preliminary value for BR0" + +config SYS_OR0_PRELIM + hex "Preliminary value for OR0" + +config SYS_BR1_PRELIM_BOOL + bool "Define Bank 1" + +config SYS_BR1_PRELIM + hex "Preliminary value for BR1" + depends on SYS_BR1_PRELIM_BOOL + +config SYS_OR1_PRELIM + hex "Preliminary value for OR1" + depends on SYS_BR1_PRELIM_BOOL + +config SYS_BR2_PRELIM_BOOL + bool "Define Bank 2" + +config SYS_BR2_PRELIM + hex "Preliminary value for BR2" + depends on SYS_BR2_PRELIM_BOOL + +config SYS_OR2_PRELIM + hex "Preliminary value for OR2" + depends on SYS_BR2_PRELIM_BOOL + +config SYS_BR3_PRELIM_BOOL + bool "Define Bank 3" + +config SYS_BR3_PRELIM + hex "Preliminary value for BR3" + depends on SYS_BR3_PRELIM_BOOL + +config SYS_OR3_PRELIM + hex "Preliminary value for OR3" + depends on SYS_BR3_PRELIM_BOOL + +config SYS_BR4_PRELIM_BOOL + bool "Define Bank 4" + +config SYS_BR4_PRELIM + hex "Preliminary value for BR4" + depends on SYS_BR4_PRELIM_BOOL + +config SYS_OR4_PRELIM + hex "Preliminary value for OR4" + depends on SYS_BR4_PRELIM_BOOL + +config SYS_BR5_PRELIM_BOOL + bool "Define Bank 5" + +config SYS_BR5_PRELIM + hex "Preliminary value for BR5" + depends on SYS_BR5_PRELIM_BOOL + +config SYS_OR5_PRELIM + hex "Preliminary value for OR5" + depends on SYS_BR5_PRELIM_BOOL + +config SYS_BR6_PRELIM_BOOL + bool "Define Bank 6" + +config SYS_BR6_PRELIM + hex "Preliminary value for BR6" + depends on SYS_BR6_PRELIM_BOOL + +config SYS_OR6_PRELIM + hex "Preliminary value for OR6" + depends on SYS_BR6_PRELIM_BOOL + +config SYS_BR7_PRELIM_BOOL + bool "Define Bank 7" + +config SYS_BR7_PRELIM + hex "Preliminary value for BR7" + depends on SYS_BR7_PRELIM_BOOL + +config SYS_OR7_PRELIM + hex "Preliminary value for OR7" + depends on SYS_BR7_PRELIM_BOOL + +config SYS_IMMR + hex "Value for IMMR" + endmenu diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c index e8045cc5c6..c97ee546bd 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c @@ -51,7 +51,7 @@ void cpu_init_f (volatile immap_t * immr)
immr->im_clkrstk.cark_sccrk = KAPWR_KEY; reg = immr->im_clkrst.car_sccr; - reg &= SCCR_MASK; + reg &= CONFIG_SYS_SCCR_MASK; reg |= CONFIG_SYS_SCCR; immr->im_clkrst.car_sccr = reg;
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index b27310fffb..5daf6fe519 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -383,7 +383,7 @@ static void fec_pin_init(int fecidx) */ immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
-#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) +#if defined(CONFIG_MPC885) && defined(WANT_MII) /* use MDC for MII */ immr->im_ioport.iop_pdpar |= 0x0080; immr->im_ioport.iop_pddir &= ~0x0080; @@ -392,7 +392,7 @@ static void fec_pin_init(int fecidx) if (fecidx == 0) { #if defined(CONFIG_ETHER_ON_FEC1)
-#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ +#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
#if !defined(CONFIG_RMII)
@@ -450,7 +450,7 @@ static void fec_pin_init(int fecidx)
#if defined(CONFIG_ETHER_ON_FEC2)
-#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ +#if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */
#if !defined(CONFIG_RMII) immr->im_cpm.cp_pepar |= 0x0003fffc; @@ -475,7 +475,7 @@ static void fec_pin_init(int fecidx) immr->im_cpm.cp_cptr &= ~0x00000028; #endif /* CONFIG_RMII */
-#endif /* CONFIG_MPC885_FAMILY */ +#endif /* CONFIG_MPC885 */
#endif /* CONFIG_ETHER_ON_FEC2 */
diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h index 9a8afe1132..c6aa2f0dfb 100644 --- a/arch/powerpc/include/asm/ppc.h +++ b/arch/powerpc/include/asm/ppc.h @@ -15,11 +15,6 @@
#if defined(CONFIG_8xx) #include <asm/8xx_immap.h> -#if defined(CONFIG_MPC866) -# define CONFIG_MPC866_FAMILY 1 -#elif defined(CONFIG_MPC885) -# define CONFIG_MPC885_FAMILY 1 -#endif #endif #ifdef CONFIG_MPC86xx #include <mpc86xx.h> diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig index 987cec99cb..e037c40df9 100644 --- a/arch/powerpc/lib/Kconfig +++ b/arch/powerpc/lib/Kconfig @@ -1,5 +1,6 @@ config CMD_IMMAP bool "Enable various commands to dump IMMR information" + depends on 8xx help This enables various commands such as:
diff --git a/arch/powerpc/lib/immap.c b/arch/powerpc/lib/immap.c index 24ac899d2e..cec0383577 100644 --- a/arch/powerpc/lib/immap.c +++ b/arch/powerpc/lib/immap.c @@ -12,8 +12,6 @@ #include <common.h> #include <command.h>
-#if defined(CONFIG_8xx) - #include <asm/8xx_immap.h> #include <commproc.h> #include <asm/iopin_8xx.h> @@ -560,5 +558,3 @@ U_BOOT_CMD( "print MCC registers", "" ); - -#endif diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index de3758d946..7c2282d731 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -28,7 +28,7 @@ #include <asm/arch/gpio.h> #endif #endif -#if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866) +#if defined(CONFIG_8xx) #include <asm/io.h> #endif #include <i2c.h> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8259c17171..787806a9ef 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -17,7 +17,6 @@ CONFIG_8xx_CONS_SCCx CONFIG_8xx_CONS_SMC1 CONFIG_8xx_CONS_SMC2 CONFIG_8xx_CONS_SMCx -CONFIG_8xx_GCLK_FREQ CONFIG_A003399_NOR_WORKAROUND CONFIG_A008044_WORKAROUND CONFIG_ACADIA @@ -1601,10 +1600,6 @@ CONFIG_MPC83XX_PCI2 CONFIG_MPC85XX_FEC CONFIG_MPC85XX_FEC_NAME CONFIG_MPC85XX_PCI2 -CONFIG_MPC866 -CONFIG_MPC866_FAMILY -CONFIG_MPC885 -CONFIG_MPC885_FAMILY CONFIG_MPC8XXX_SPI CONFIG_MPC8xxx_DISABLE_BPTR CONFIG_MPLL_FREQ @@ -3083,7 +3078,6 @@ CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS CONFIG_SYS_DEFAULT_VIDEO_MODE CONFIG_SYS_DEF_EEPROM_ADDR -CONFIG_SYS_DER CONFIG_SYS_DEVICE_NULLDEV CONFIG_SYS_DFU_DATA_BUF_SIZE CONFIG_SYS_DFU_MAX_FILE_SIZE @@ -4909,7 +4903,6 @@ CONFIG_SYS_PIOC_PPUDR_VAL CONFIG_SYS_PIOD_PDR_VAL1 CONFIG_SYS_PIOD_PPUDR_VAL CONFIG_SYS_PIO_MODE -CONFIG_SYS_PISCR CONFIG_SYS_PIT_BASE CONFIG_SYS_PIT_PRESCALE CONFIG_SYS_PIXIS_VBOOT_ENABLE @@ -4931,7 +4924,6 @@ CONFIG_SYS_PLL_BYPASS CONFIG_SYS_PLL_FDR CONFIG_SYS_PLL_ODR CONFIG_SYS_PLL_SETTLING_TIME -CONFIG_SYS_PLPRCR CONFIG_SYS_PLUG_BASE CONFIG_SYS_PMAN CONFIG_SYS_PMC_BASE @@ -5176,7 +5168,6 @@ CONFIG_SYS_SH_SDHI_NR_CHANNEL CONFIG_SYS_SICRH CONFIG_SYS_SICRL CONFIG_SYS_SIL1178_I2C -CONFIG_SYS_SIUMCR CONFIG_SYS_SJA1000_BASE CONFIG_SYS_SMALL_FLASH CONFIG_SYS_SMC0_CYCLE0_VAL @@ -5254,11 +5245,9 @@ CONFIG_SYS_STATUS_OK CONFIG_SYS_STMICRO_BOOT CONFIG_SYS_SUPPORT_64BIT_DATA CONFIG_SYS_SXCNFG_VAL -CONFIG_SYS_SYPCR CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_SYSTEMACE_WIDTH CONFIG_SYS_TBIPA_VALUE -CONFIG_SYS_TBSCR CONFIG_SYS_TCLK CONFIG_SYS_TEXT_ADDR CONFIG_SYS_TEXT_BASE_NOR
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr --- README | 15 ------ arch/powerpc/cpu/mpc8xx/Makefile | 1 - arch/powerpc/cpu/mpc8xx/cpu.c | 2 +- drivers/net/Kconfig | 58 ++++++++++++++++++++++ drivers/net/Makefile | 1 + .../cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c | 18 ------- scripts/config_whitelist.txt | 4 -- 7 files changed, 60 insertions(+), 39 deletions(-) rename arch/powerpc/cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c (98%)
diff --git a/README b/README index 3d9aad5c9c..4eeda3f7fe 100644 --- a/README +++ b/README @@ -4083,21 +4083,6 @@ Low Level (hardware related) configuration options: Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3.
-- CONFIG_ETHER_ON_FEC[12] - Define to enable FEC[12] on a 8xx series processor. - -- CONFIG_FEC[12]_PHY - Define to the hardcoded PHY address which corresponds - to the given FEC; i. e. - #define CONFIG_FEC1_PHY 4 - means that the PHY with address 4 is connected to FEC1 - - When set to -1, means to probe for first available. - -- CONFIG_FEC[12]_PHY_NORXERR - The PHY does not have a RXERR line (RMII only). - (so program the FEC to ignore it). - - CONFIG_RMII Enable RMII mode for all FECs. Note that this is a global option, we can't diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index db2f5ecd47..c6b933b680 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -11,7 +11,6 @@ extra-y += start.o extra-y += traps.o obj-y += cpu.o obj-y += cpu_init.o -obj-y += fec.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-y += interrupts.o obj-$(CONFIG_CMD_REGINFO) += reginfo.o diff --git a/arch/powerpc/cpu/mpc8xx/cpu.c b/arch/powerpc/cpu/mpc8xx/cpu.c index 19392de168..6ce73de4e8 100644 --- a/arch/powerpc/cpu/mpc8xx/cpu.c +++ b/arch/powerpc/cpu/mpc8xx/cpu.c @@ -347,7 +347,7 @@ void reset_8xx_watchdog (volatile immap_t * immr) */ int cpu_eth_init(bd_t *bis) { -#if defined(FEC_ENET) +#if defined(CONFIG_MPC8XX_FEC) fec_initialize(bis); #endif return 0; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 33634c33d4..736aab2e6e 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -246,4 +246,62 @@ config RENESAS_RAVB This driver implements support for the Ethernet AVB block in Renesas M3 and H3 SoCs.
+config MPC8XX_FEC + bool "Fast Ethernet Controller on MPC8XX" + depends on 8xx + select MII + help + This driver implements support for the Fast Ethernet Controller + on MPC8XX + +config ETHER_ON_FEC1 + bool "FEC1" + depends on MPC8XX_FEC + default y + +config FEC1_PHY + int "FEC1 PHY" + depends on ETHER_ON_FEC1 + default -1 + help + Define to the hardcoded PHY address which corresponds + to the given FEC; i. e. + #define CONFIG_FEC1_PHY 4 + means that the PHY with address 4 is connected to FEC1 + + When set to -1, means to probe for first available. + +config PHY_NORXERR + bool "PHY_NORXERR" + depends on ETHER_ON_FEC1 + default n + help + The PHY does not have a RXERR line (RMII only). + (so program the FEC to ignore it). + +config ETHER_ON_FEC2 + bool "FEC2" + depends on MPC8XX_FEC && MPC885 + default y + +config FEC2_PHY + int "FEC2 PHY" + depends on ETHER_ON_FEC2 + default -1 + help + Define to the hardcoded PHY address which corresponds + to the given FEC; i. e. + #define CONFIG_FEC1_PHY 4 + means that the PHY with address 4 is connected to FEC1 + + When set to -1, means to probe for first available. + +config FEC2_PHY_NORXERR + bool "PHY_NORXERR" + depends on ETHER_ON_FEC2 + default n + help + The PHY does not have a RXERR line (RMII only). + (so program the FEC to ignore it). + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 4a5176e087..94a4fd8701 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_LAN91C96) += lan91c96.o obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o +obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVNETA) += mvneta.o obj-$(CONFIG_MVPP2) += mvpp2.o diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/drivers/net/mpc8xx_fec.c similarity index 98% rename from arch/powerpc/cpu/mpc8xx/fec.c rename to drivers/net/mpc8xx_fec.c index 5daf6fe519..ebf8a1c0bd 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/drivers/net/mpc8xx_fec.c @@ -17,14 +17,6 @@ DECLARE_GLOBAL_DATA_PTR;
#undef ET_DEBUG
-#if defined(CONFIG_CMD_NET) && \ - (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)) - -/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */ -#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2) -#define CONFIG_ETHER_ON_FEC1 1 -#endif - /* define WANT_MII when MII support is required */ #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) #define WANT_MII @@ -66,11 +58,7 @@ static struct ether_fcc_info_s { 0, offsetof(immap_t, im_cpm.cp_fec1), -#if defined(CONFIG_FEC1_PHY) CONFIG_FEC1_PHY, -#else - -1, /* discover */ -#endif -1, 0,
@@ -80,11 +68,7 @@ static struct ether_fcc_info_s { 1, offsetof(immap_t, im_cpm.cp_fec2), -#if defined(CONFIG_FEC2_PHY) CONFIG_FEC2_PHY, -#else - -1, -#endif -1, 0, }, @@ -929,5 +913,3 @@ int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, return 0; } #endif - -#endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 787806a9ef..f51dd4fa17 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -739,8 +739,6 @@ CONFIG_ETHER_ON_FCC CONFIG_ETHER_ON_FCC1 CONFIG_ETHER_ON_FCC2 CONFIG_ETHER_ON_FCC3 -CONFIG_ETHER_ON_FEC1 -CONFIG_ETHER_ON_FEC2 CONFIG_ETHPRIME CONFIG_ETH_BUFSIZE CONFIG_ETH_RXSIZE @@ -797,8 +795,6 @@ CONFIG_FEATURE_SH_APPLETS_ALWAYS_WIN CONFIG_FEATURE_SH_EXTRA_QUIET CONFIG_FEATURE_SH_FANCY_PROMPT CONFIG_FEATURE_SH_STANDALONE_SHELL -CONFIG_FEC1_PHY -CONFIG_FEC2_PHY CONFIG_FEC_ENET CONFIG_FEC_ENET_DEV CONFIG_FEC_FIXED_SPEED
On Thu, Jun 29, 2017 at 11:54 AM, Christophe Leroy christophe.leroy@c-s.fr wrote:
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr
README | 15 ------ arch/powerpc/cpu/mpc8xx/Makefile | 1 - arch/powerpc/cpu/mpc8xx/cpu.c | 2 +- drivers/net/Kconfig | 58 ++++++++++++++++++++++ drivers/net/Makefile | 1 + .../cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c | 18 ------- scripts/config_whitelist.txt | 4 -- 7 files changed, 60 insertions(+), 39 deletions(-) rename arch/powerpc/cpu/mpc8xx/fec.c => drivers/net/mpc8xx_fec.c (98%)
Acked-by: Joe Hershberger joe.hershberger@ni.com
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr --- arch/powerpc/cpu/mpc8xx/Makefile | 1 - drivers/spi/Kconfig | 6 ++++++ drivers/spi/Makefile | 1 + arch/powerpc/cpu/mpc8xx/spi.c => drivers/spi/mpc8xx_spi.c | 3 --- 4 files changed, 7 insertions(+), 4 deletions(-) rename arch/powerpc/cpu/mpc8xx/spi.c => drivers/spi/mpc8xx_spi.c (99%)
diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index c6b933b680..9f62454dfb 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -16,5 +16,4 @@ obj-y += interrupts.o obj-$(CONFIG_CMD_REGINFO) += reginfo.o obj-y += serial.o obj-y += speed.o -obj-y += spi.o obj-y += plprcr_write.o diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index bef864f46e..03d0c05f23 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -223,4 +223,10 @@ config TI_QSPI Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. This driver support spi flash single, quad and memory reads.
+config MPC8XX_SPI + bool "MPC8XX SPI Driver" + depends on 8xx + help + Enable support for SPI on MPC8XX + endmenu # menu "SPI Support" diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index c090562c77..9f8b86de76 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o +obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o diff --git a/arch/powerpc/cpu/mpc8xx/spi.c b/drivers/spi/mpc8xx_spi.c similarity index 99% rename from arch/powerpc/cpu/mpc8xx/spi.c rename to drivers/spi/mpc8xx_spi.c index f39ce22632..74ba11e77a 100644 --- a/arch/powerpc/cpu/mpc8xx/spi.c +++ b/drivers/spi/mpc8xx_spi.c @@ -25,8 +25,6 @@ #include <post.h> #include <serial.h>
-#ifdef CONFIG_SPI - /* Warning: * You cannot enable DEBUG for early system initalization, i. e. when * this driver is used to read environment parameters like "baudrate" @@ -421,4 +419,3 @@ ssize_t spi_xfer (size_t count)
return count; } -#endif /* CONFIG_SPI */
Signed-off-by: Christophe Leroy christophe.leroy@c-s.fr --- README | 19 ------ arch/powerpc/cpu/mpc8xx/Makefile | 1 - drivers/serial/Kconfig | 72 ++++++++++++++++++++++ drivers/serial/Makefile | 1 + .../serial.c => drivers/serial/serial_mpc8xx.c | 15 ----- scripts/config_whitelist.txt | 9 --- 6 files changed, 73 insertions(+), 44 deletions(-) rename arch/powerpc/cpu/mpc8xx/serial.c => drivers/serial/serial_mpc8xx.c (97%)
diff --git a/README b/README index 4eeda3f7fe..c5ddf326b3 100644 --- a/README +++ b/README @@ -691,29 +691,10 @@ The following options need to be configured: Define this variable to enable hw flow control in serial driver. Current user of this option is drivers/serial/nsl16550.c driver
-- Console Interface: - Depending on board, define exactly one serial port - (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2, - CONFIG_8xx_CONS_SCC1, ...), or switch off the serial - console by defining CONFIG_8xx_CONS_NONE - - Note: if CONFIG_8xx_CONS_NONE is defined, the serial - port routines must be defined elsewhere - (i.e. serial_init(), serial_getc(), ...) - - Console Baudrate: CONFIG_BAUDRATE - in bps Select one of the baudrates listed in CONFIG_SYS_BAUDRATE_TABLE, see below. - CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale - -- Console Rx buffer length - With CONFIG_SYS_SMC_RXBUFLEN it is possible to define - the maximum receive buffer length for the SMC. - This option is actual only for 8xx possible. - If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE - must be defined, to setup the maximum idle timeout for - the SMC.
- Autoboot Command: CONFIG_BOOTCOMMAND diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index 9f62454dfb..a56eeeeb6b 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -14,6 +14,5 @@ obj-y += cpu_init.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-y += interrupts.o obj-$(CONFIG_CMD_REGINFO) += reginfo.o -obj-y += serial.o obj-y += speed.o obj-y += plprcr_write.o diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c64f4a6d7b..cea39ce3c7 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -491,4 +491,76 @@ config STI_ASC_SERIAL on STiH410 SoC. This is a basic implementation, it supports following baudrate 9600, 19200, 38400, 57600 and 115200.
+config MPC8XX_CONS + bool "Console driver for MPC8XX" + depends on 8xx + default y + +choice + prompt "Console port" + default 8xx_CONS_SMC1 + depends on MPC8XX_CONS + help + Depending on board, define exactly one serial port + (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2, + CONFIG_8xx_CONS_SCC1, ...) + +config 8xx_CONS_SMC1 + bool "SMC1" + +config 8xx_CONS_SMC2 + bool "SMC2" + +config 8xx_CONS_SCC1 + bool "SCC1" + +config 8xx_CONS_SCC2 + bool "SCC2" + +config 8xx_CONS_SCC3 + bool "SCC3" + +config 8xx_CONS_SCC4 + bool "SCC4" + +endchoice + +config SYS_SMC_RXBUFLEN + int "Console Rx buffer length" + depends on MPC8XX_CONS + default 1 + help + With CONFIG_SYS_SMC_RXBUFLEN it is possible to define + the maximum receive buffer length for the SMC. + This option is actual only for 8xx possible. + If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE + must be defined, to setup the maximum idle timeout for + the SMC. + +config SYS_MAXIDLE + int "maximum idle timeout" + depends on MPC8XX_CONS + default 0 + +config SYS_BRGCLK_PRESCALE + int "BRG Clock Prescale" + depends on MPC8XX_CONS + default 1 + +config SYS_SDSR_BOOL + bool "Define SRSR value" + depends on 8xx_CONS_SMC1 || 8xx_CONS_SMC2 + +config SYS_SDSR + hex "SDSR Value" + depends on SYS_SDSR_BOOL + +config SYS_SDMR_BOOL + bool "Define SRMR value" + depends on 8xx_CONS_SMC1 || 8xx_CONS_SMC2 + +config SYS_SDMR + hex "SDMR Value" + depends on SYS_SDMR_BOOL + endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dca31b295c..72a6996a0a 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o obj-$(CONFIG_MSM_SERIAL) += serial_msm.o obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o +obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/drivers/serial/serial_mpc8xx.c similarity index 97% rename from arch/powerpc/cpu/mpc8xx/serial.c rename to drivers/serial/serial_mpc8xx.c index 2519156d4b..5271a3fe1b 100644 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ b/drivers/serial/serial_mpc8xx.c @@ -14,8 +14,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ - #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ #define SMC_INDEX 0 #define PROFF_SMC PROFF_SMC1 @@ -50,15 +48,6 @@ DECLARE_GLOBAL_DATA_PTR;
#endif /* CONFIG_8xx_CONS_SCCx */
-#if !defined(CONFIG_SYS_SMC_RXBUFLEN) -#define CONFIG_SYS_SMC_RXBUFLEN 1 -#define CONFIG_SYS_MAXIDLE 0 -#else -#if !defined(CONFIG_SYS_MAXIDLE) -#error "you must define CONFIG_SYS_MAXIDLE" -#endif -#endif - typedef volatile struct serialbuffer { cbd_t rxbd; /* Rx BD */ cbd_t txbd; /* Tx BD */ @@ -76,9 +65,7 @@ static void serial_setdivisor(volatile cpm8xx_t *cp) divisor=(50*1000*1000 + 8*9600)/16/9600; }
-#ifdef CONFIG_SYS_BRGCLK_PRESCALE divisor /= CONFIG_SYS_BRGCLK_PRESCALE; -#endif
if(divisor<=0x1000) { cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN; @@ -560,5 +547,3 @@ void mpc8xx_serial_initialize(void) serial_register(&serial_scc_device); #endif } - -#endif /* CONFIG_8xx_CONS_NONE */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index f51dd4fa17..00b9cbf949 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -12,11 +12,6 @@ CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES CONFIG_83XX_PCICLK CONFIG_83XX_PCI_STREAMING CONFIG_88F5182 -CONFIG_8xx_CONS_NONE -CONFIG_8xx_CONS_SCCx -CONFIG_8xx_CONS_SMC1 -CONFIG_8xx_CONS_SMC2 -CONFIG_8xx_CONS_SMCx CONFIG_A003399_NOR_WORKAROUND CONFIG_A008044_WORKAROUND CONFIG_ACADIA @@ -2660,7 +2655,6 @@ CONFIG_SYS_BR6_64M CONFIG_SYS_BR6_8M CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR7_PRELIM -CONFIG_SYS_BRGCLK_PRESCALE CONFIG_SYS_BUSCLK CONFIG_SYS_CACHELINE_SHIFT CONFIG_SYS_CACHE_ACR0 @@ -5087,7 +5081,6 @@ CONFIG_SYS_SDIO_BASE0 CONFIG_SYS_SDIO_BASE1 CONFIG_SYS_SDIO_BASE2 CONFIG_SYS_SDIO_BASE3 -CONFIG_SYS_SDMR CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BANKS @@ -5136,7 +5129,6 @@ CONFIG_SYS_SDRC_MR_VAL5 CONFIG_SYS_SDRC_TR_VAL CONFIG_SYS_SDRC_TR_VAL1 CONFIG_SYS_SDRC_TR_VAL2 -CONFIG_SYS_SDSR CONFIG_SYS_SD_VOLTAGE CONFIG_SYS_SEC_MON_ADDR CONFIG_SYS_SEC_MON_OFFSET @@ -5171,7 +5163,6 @@ CONFIG_SYS_SMC0_MODE0_VAL CONFIG_SYS_SMC0_PULSE0_VAL CONFIG_SYS_SMC0_SETUP0_VAL CONFIG_SYS_SMC_CSR0_VAL -CONFIG_SYS_SMC_RXBUFLEN CONFIG_SYS_SMI_BASE CONFIG_SYS_SPANSION_BASE CONFIG_SYS_SPANSION_BOOT
participants (4)
-
Christophe LEROY -
Christophe Leroy
-
Joe Hershberger -
Wolfgang Denk