[PATCH 0/2] Add RGMII-ID phy-mode support for AVE ethernet controller

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[PATCH 1/2] net: dwc_eth_qos: Add...

Kunihiko Hayashi

13 Jul 2022 13 Jul '22

3:59 a.m.

This series adds support for RGMII-ID phy-mode for the SoCs that implement AVE ethernet controller. Some SoCs need to enable delay pins as default.

Kunihiko Hayashi (2): net: ave: Add capability of rgmii-id mode ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins

arch/arm/dts/uniphier-ld20.dtsi | 2 +- arch/arm/dts/uniphier-pxs2.dtsi | 2 +- arch/arm/dts/uniphier-pxs3.dtsi | 4 ++-- drivers/net/sni_ave.c | 14 +++++++++++++- 4 files changed, 17 insertions(+), 5 deletions(-)

-- 2.7.4

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Kunihiko Hayashi

13 Jul 13 Jul

3:59 a.m.

New subject: [PATCH 1/2] net: ave: Add capability of rgmii-id mode

This allows you to specify the type of rgmii-id that will enable phy internal delay in ethernet phy-mode.

This adds all RGMII cases to all of get_pinmode() except LD11, because LD11 SoC doesn't support RGMII due to the constraint of the hardware. When RGMII phy mode is specified in the devicetree for LD11, the driver will abort with an error.

Signed-off-by: Kunihiko Hayashi hayashi.kunihiko@socionext.com --- drivers/net/sni_ave.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/net/sni_ave.c b/drivers/net/sni_ave.c index 58276a40c774..014b070d9e52 100644 --- a/drivers/net/sni_ave.c +++ b/drivers/net/sni_ave.c @@ -483,7 +483,10 @@ static int ave_start(struct udevice *dev) priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off);

val = 0; - if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII) + if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII && + priv->phy_mode != PHY_INTERFACE_MODE_RGMII_ID && + priv->phy_mode != PHY_INTERFACE_MODE_RGMII_RXID && + priv->phy_mode != PHY_INTERFACE_MODE_RGMII_TXID) val |= AVE_CFGR_MII; writel(val, priv->iobase + AVE_CFGR);

@@ -639,6 +642,9 @@ static int ave_pro4_get_pinmode(struct ave_private *priv) break; case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: break; default: return -EINVAL; @@ -693,6 +699,9 @@ static int ave_ld20_get_pinmode(struct ave_private *priv) val = SG_ETPINMODE_RMII(0); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: break; default: return -EINVAL; @@ -720,6 +729,9 @@ static int ave_pxs3_get_pinmode(struct ave_private *priv) val = SG_ETPINMODE_RMII(priv->regmap_arg); break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: break; default: return -EINVAL;

-- 2.7.4

Ramon Fried

6 Aug 6 Aug

7:18 p.m.

New subject: [PATCH 1/2] net: ave: Add capability of rgmii-id mode

On Wed, Jul 13, 2022 at 4:59 AM Kunihiko Hayashi hayashi.kunihiko@socionext.com wrote:

...

This allows you to specify the type of rgmii-id that will enable phy internal delay in ethernet phy-mode.

This adds all RGMII cases to all of get_pinmode() except LD11, because LD11 SoC doesn't support RGMII due to the constraint of the hardware. When RGMII phy mode is specified in the devicetree for LD11, the driver will abort with an error.

Signed-off-by: Kunihiko Hayashi hayashi.kunihiko@socionext.com

drivers/net/sni_ave.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/net/sni_ave.c b/drivers/net/sni_ave.c index 58276a40c774..014b070d9e52 100644 --- a/drivers/net/sni_ave.c +++ b/drivers/net/sni_ave.c @@ -483,7 +483,10 @@ static int ave_start(struct udevice *dev) priv->rx_siz = (PKTSIZE_ALIGN - priv->rx_off);
    val = 0;
  if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII)
  if (priv->phy_mode != PHY_INTERFACE_MODE_RGMII &&
      priv->phy_mode != PHY_INTERFACE_MODE_RGMII_ID &&
      priv->phy_mode != PHY_INTERFACE_MODE_RGMII_RXID &&
      priv->phy_mode != PHY_INTERFACE_MODE_RGMII_TXID)
          val |= AVE_CFGR_MII;
  writel(val, priv->iobase + AVE_CFGR);
@@ -639,6 +642,9 @@ static int ave_pro4_get_pinmode(struct ave_private *priv) break; case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_RGMII:
  case PHY_INTERFACE_MODE_RGMII_ID:
  case PHY_INTERFACE_MODE_RGMII_RXID:
  case PHY_INTERFACE_MODE_RGMII_TXID:
          break;
  default:
          return -EINVAL;
@@ -693,6 +699,9 @@ static int ave_ld20_get_pinmode(struct ave_private *priv) val = SG_ETPINMODE_RMII(0); break; case PHY_INTERFACE_MODE_RGMII:
  case PHY_INTERFACE_MODE_RGMII_ID:
  case PHY_INTERFACE_MODE_RGMII_RXID:
  case PHY_INTERFACE_MODE_RGMII_TXID:
          break;
  default:
          return -EINVAL;
@@ -720,6 +729,9 @@ static int ave_pxs3_get_pinmode(struct ave_private *priv) val = SG_ETPINMODE_RMII(priv->regmap_arg); break; case PHY_INTERFACE_MODE_RGMII:
  case PHY_INTERFACE_MODE_RGMII_ID:
  case PHY_INTERFACE_MODE_RGMII_RXID:
  case PHY_INTERFACE_MODE_RGMII_TXID:
          break;
  default:
          return -EINVAL;
-- 2.7.4

Reviewed-by: Ramon Fried rfried.dev@gmail.com

Tom Rini

8 Aug 8 Aug

9:08 p.m.

New subject: [PATCH 1/2] net: ave: Add capability of rgmii-id mode

On Wed, Jul 13, 2022 at 10:59:44AM +0900, Kunihiko Hayashi wrote:

...

This allows you to specify the type of rgmii-id that will enable phy internal delay in ethernet phy-mode.

This adds all RGMII cases to all of get_pinmode() except LD11, because LD11 SoC doesn't support RGMII due to the constraint of the hardware. When RGMII phy mode is specified in the devicetree for LD11, the driver will abort with an error.

Signed-off-by: Kunihiko Hayashi hayashi.kunihiko@socionext.com Reviewed-by: Ramon Fried rfried.dev@gmail.com

Applied to u-boot/master, thanks!

-- Tom

Kunihiko Hayashi

13 Jul 13 Jul

3:59 a.m.

New subject: [PATCH 2/2] ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins

UniPhier LD20, PXs2 and PXs3 boards have ethernet phy that has RX/TX delays of RGMII interface using pull-ups on the RXDLY and TXDLY pins.

So should set the phy-mode to "rgmii-id" to show that RX/TX delays are enabled.

Signed-off-by: Kunihiko Hayashi hayashi.kunihiko@socionext.com --- arch/arm/dts/uniphier-ld20.dtsi | 2 +- arch/arm/dts/uniphier-pxs2.dtsi | 2 +- arch/arm/dts/uniphier-pxs3.dtsi | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 5e7143ed012f..4549935c421b 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -734,7 +734,7 @@ clocks = <&sys_clk 6>; reset-names = "ether"; resets = <&sys_rst 6>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; local-mac-address = [00 00 00 00 00 00]; socionext,syscon-phy-mode = <&soc_glue 0>;

diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 899ff379c9b8..7a8b6c10f4dc 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -583,7 +583,7 @@ clocks = <&sys_clk 6>; reset-names = "ether"; resets = <&sys_rst 6>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; local-mac-address = [00 00 00 00 00 00]; socionext,syscon-phy-mode = <&soc_glue 0>;

diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index c4344926d95d..004656c992b7 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -564,7 +564,7 @@ clocks = <&sys_clk 6>; reset-names = "ether"; resets = <&sys_rst 6>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; local-mac-address = [00 00 00 00 00 00]; socionext,syscon-phy-mode = <&soc_glue 0>;

@@ -585,7 +585,7 @@ clocks = <&sys_clk 7>; reset-names = "ether"; resets = <&sys_rst 7>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; local-mac-address = [00 00 00 00 00 00]; socionext,syscon-phy-mode = <&soc_glue 1>;

-- 2.7.4

Ramon Fried

7 Aug 7 Aug

2:01 a.m.

New subject: [PATCH 2/2] ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins

On Wed, Jul 13, 2022 at 4:59 AM Kunihiko Hayashi hayashi.kunihiko@socionext.com wrote:

...

UniPhier LD20, PXs2 and PXs3 boards have ethernet phy that has RX/TX delays of RGMII interface using pull-ups on the RXDLY and TXDLY pins.

So should set the phy-mode to "rgmii-id" to show that RX/TX delays are enabled.

Signed-off-by: Kunihiko Hayashi hayashi.kunihiko@socionext.com

arch/arm/dts/uniphier-ld20.dtsi | 2 +- arch/arm/dts/uniphier-pxs2.dtsi | 2 +- arch/arm/dts/uniphier-pxs3.dtsi | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 5e7143ed012f..4549935c421b 100644 --- a/arch/arm/dts/uniphier-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -734,7 +734,7 @@ clocks = <&sys_clk 6>; reset-names = "ether"; resets = <&sys_rst 6>;
                  phy-mode = "rgmii";
                  phy-mode = "rgmii-id";
                  local-mac-address = [00 00 00 00 00 00];
                  socionext,syscon-phy-mode = <&soc_glue 0>;
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 899ff379c9b8..7a8b6c10f4dc 100644 --- a/arch/arm/dts/uniphier-pxs2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -583,7 +583,7 @@ clocks = <&sys_clk 6>; reset-names = "ether"; resets = <&sys_rst 6>;
                  phy-mode = "rgmii";
                  phy-mode = "rgmii-id";
                  local-mac-address = [00 00 00 00 00 00];
                  socionext,syscon-phy-mode = <&soc_glue 0>;
diff --git a/arch/arm/dts/uniphier-pxs3.dtsi b/arch/arm/dts/uniphier-pxs3.dtsi index c4344926d95d..004656c992b7 100644 --- a/arch/arm/dts/uniphier-pxs3.dtsi +++ b/arch/arm/dts/uniphier-pxs3.dtsi @@ -564,7 +564,7 @@ clocks = <&sys_clk 6>; reset-names = "ether"; resets = <&sys_rst 6>;
                  phy-mode = "rgmii";
                  phy-mode = "rgmii-id";
                  local-mac-address = [00 00 00 00 00 00];
                  socionext,syscon-phy-mode = <&soc_glue 0>;
@@ -585,7 +585,7 @@ clocks = <&sys_clk 7>; reset-names = "ether"; resets = <&sys_rst 7>;
                  phy-mode = "rgmii";
                  phy-mode = "rgmii-id";
                  local-mac-address = [00 00 00 00 00 00];
                  socionext,syscon-phy-mode = <&soc_glue 1>;
-- 2.7.4

Reviewed-by: Ramon Fried rfried.dev@gmail.com

Tom Rini

8 Aug 8 Aug

9:08 p.m.

New subject: [PATCH 2/2] ARM: dts: uniphier: Change phy-mode to RGMII-ID to enable delay pins

On Wed, Jul 13, 2022 at 10:59:45AM +0900, Kunihiko Hayashi wrote:

...

UniPhier LD20, PXs2 and PXs3 boards have ethernet phy that has RX/TX delays of RGMII interface using pull-ups on the RXDLY and TXDLY pins.

So should set the phy-mode to "rgmii-id" to show that RX/TX delays are enabled.

Signed-off-by: Kunihiko Hayashi hayashi.kunihiko@socionext.com Reviewed-by: Ramon Fried rfried.dev@gmail.com

Applied to u-boot/master, thanks!

-- Tom

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Kunihiko Hayashi
Ramon Fried
Tom Rini