On Sat, Jan 25, 2020 at 05:52:43PM +0530, Amit Singh Tomar wrote:

This commit adds common arch support for Actions Semi Owl series SoCs and removes the Bubblegum96 board files.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

MAINTAINERS | 2 + arch/arm/Kconfig | 3 +- arch/arm/mach-owl/Kconfig | 29 ++++++-------- arch/arm/mach-owl/Makefile | 1 + arch/arm/mach-owl/soc.c | 57 ++++++++++++++++++++++++++++ board/ucRobotics/bubblegum_96/Kconfig | 15 -------- board/ucRobotics/bubblegum_96/MAINTAINERS | 6 --- board/ucRobotics/bubblegum_96/Makefile | 3 -- board/ucRobotics/bubblegum_96/bubblegum_96.c | 57 ---------------------------- configs/bubblegum_96_defconfig | 4 +- include/configs/bubblegum_96.h | 40 ------------------- include/configs/owl-common.h | 40 +++++++++++++++++++ include/configs/s900.h | 16 ++++++++ 13 files changed, 130 insertions(+), 143 deletions(-) create mode 100644 arch/arm/mach-owl/soc.c delete mode 100644 board/ucRobotics/bubblegum_96/Kconfig delete mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS delete mode 100644 board/ucRobotics/bubblegum_96/Makefile delete mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c delete mode 100644 include/configs/bubblegum_96.h create mode 100644 include/configs/owl-common.h create mode 100644 include/configs/s900.h

diff --git a/MAINTAINERS b/MAINTAINERS index b0634b2..218d811 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -266,6 +266,8 @@ F: arch/arm/mach-owl/ F: board/ucRobotics/ F: drivers/clk/owl/ F: drivers/serial/serial_owl.c +F: include/configs/bubblegum_96.h

This got changed to include/configs/owl-common.h

+F: configs/bubblegum_96_defconfig

ARM RENESAS RMOBILE/R-CAR M: Nobuhiro Iwamatsu iwamatsu@nigauri.org diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9608f54..905118b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -883,9 +883,9 @@ config ARCH_MX5

config ARCH_OWL bool "Actions Semi OWL SoCs"

• select ARM64 select DM select DM_SERIAL

• select OWL_SERIAL select OF_CONTROL imply CMD_DM

@@ -1878,7 +1878,6 @@ source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" source "board/st/stv0991/Kconfig" source "board/tcl/sl50/Kconfig" -source "board/ucRobotics/bubblegum_96/Kconfig" source "board/birdland/bav335x/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig index 199e772..28f6121 100644 --- a/arch/arm/mach-owl/Kconfig +++ b/arch/arm/mach-owl/Kconfig @@ -1,27 +1,22 @@ if ARCH_OWL

-config SYS_SOC

• default "owl"

choice

•    prompt "Actions Semi OWL SoCs board select"
  

•    prompt "Actions Semi Owl SoC Variant"
     optional
  
  

-config TARGET_BUBBLEGUM_96

• bool "96Boards Bubblegum-96"
• help

•  Support for 96Boards Bubblegum-96. This board complies with
  

•  96Board Consumer Edition Specification. Features:
  

•  - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU)
  

•  - 2GiB RAM
  

•  - 8GiB eMMC, uSD slot
  

•  - WiFi, Bluetooth and GPS module
  

•  - 2x Host, 1x Device USB port
  

•  - HDMI
  

•  - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons
  

+config MACH_S900

•    bool "Actions Semi S900"
  

Actions Semi S900 SoC

•    select ARM64
  
  

endchoice

-source "board/ucRobotics/bubblegum_96/Kconfig" +config SYS_TEXT_BASE

•    default 0x11000000
  

+config SYS_CONFIG_NAME

•    default "s900" if MACH_S900
  

+config SYS_SOC

•    default "s900" if MACH_S900
  
  

endif diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile index 1b43dc2..0b181c6 100644 --- a/arch/arm/mach-owl/Makefile +++ b/arch/arm/mach-owl/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+

+obj-y += soc.o obj-y += sysmap-s900.o diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c new file mode 100644 index 0000000..0f9ac64 --- /dev/null +++ b/arch/arm/mach-owl/soc.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Actions Semi Owl SoCs Boards Support.

Actions Semi Owl SoCs platform support

Thanks, Mani

• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#include <cpu_func.h> +#include <linux/arm-smccc.h> +#include <linux/psci.h> +#include <common.h> +#include <asm/io.h> +#include <asm/mach-types.h> +#include <asm/psci.h>

+DECLARE_GLOBAL_DATA_PTR;

+/*

• • dram_init - sets uboots idea of sdram size
• */

+int dram_init(void) +{

• gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
• return 0;

+}

+/* This is called after dram_init() so use get_ram_size result */ +int dram_init_banksize(void) +{

• gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
• gd->bd->bi_dram[0].size = gd->ram_size;
• return 0;

+}

+static void show_psci_version(void) +{

• struct arm_smccc_res res;
• arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
• printf("PSCI: v%ld.%ld\n",

• PSCI_VERSION_MAJOR(res.a0),
  

• PSCI_VERSION_MINOR(res.a0));
  

+}

+int board_init(void) +{

• show_psci_version();
• return 0;

+}

+void reset_cpu(ulong addr) +{

• psci_system_reset();

+} diff --git a/board/ucRobotics/bubblegum_96/Kconfig b/board/ucRobotics/bubblegum_96/Kconfig deleted file mode 100644 index 2dd40d9..0000000 --- a/board/ucRobotics/bubblegum_96/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_BUBBLEGUM_96

-config SYS_BOARD

• default "bubblegum_96"

-config SYS_VENDOR

• default "ucRobotics"

-config SYS_SOC

• default "s900"

-config SYS_CONFIG_NAME

• default "bubblegum_96"

-endif diff --git a/board/ucRobotics/bubblegum_96/MAINTAINERS b/board/ucRobotics/bubblegum_96/MAINTAINERS deleted file mode 100644 index d0cb727..0000000 --- a/board/ucRobotics/bubblegum_96/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -BUBBLEGUM_96 BOARD -M: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org -S: Maintained -F: board/ucRobotics/bubblegum_96/ -F: include/configs/bubblegum_96.h -F: configs/bubblegum_96_defconfig diff --git a/board/ucRobotics/bubblegum_96/Makefile b/board/ucRobotics/bubblegum_96/Makefile deleted file mode 100644 index c4b524d..0000000 --- a/board/ucRobotics/bubblegum_96/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+

-obj-y := bubblegum_96.o diff --git a/board/ucRobotics/bubblegum_96/bubblegum_96.c b/board/ucRobotics/bubblegum_96/bubblegum_96.c deleted file mode 100644 index c16f117..0000000 --- a/board/ucRobotics/bubblegum_96/bubblegum_96.c +++ /dev/null @@ -1,57 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Bubblegum-96 Boards Support
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#include <cpu_func.h> -#include <linux/arm-smccc.h> -#include <linux/psci.h> -#include <common.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <asm/psci.h>

-DECLARE_GLOBAL_DATA_PTR;

-/*

• • dram_init - sets uboots idea of sdram size
• */

-int dram_init(void) -{

• gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
• return 0;

-}

-/* This is called after dram_init() so use get_ram_size result */ -int dram_init_banksize(void) -{

• gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
• gd->bd->bi_dram[0].size = gd->ram_size;
• return 0;

-}

-static void show_psci_version(void) -{

• struct arm_smccc_res res;
• arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
• printf("PSCI: v%ld.%ld\n",

•       PSCI_VERSION_MAJOR(res.a0),
  

• PSCI_VERSION_MINOR(res.a0));
  

-}

-int board_init(void) -{

• show_psci_version();
• return 0;

-}

-void reset_cpu(ulong addr) -{

• psci_system_reset();

-} diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index ae44ce1..8c94def 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_OWL=y -CONFIG_SYS_TEXT_BASE=0x11000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_TARGET_BUBBLEGUM_96=y CONFIG_NR_DRAM_BANKS=1 +CONFIG_MACH_S900=y CONFIG_IDENT_STRING="\nBubblegum-96" CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=5 @@ -21,4 +20,3 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_OWL=y CONFIG_CLK_S900=y -CONFIG_OWL_SERIAL=y diff --git a/include/configs/bubblegum_96.h b/include/configs/bubblegum_96.h deleted file mode 100644 index c739d66..0000000 --- a/include/configs/bubblegum_96.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Board configuration file for Bubblegum-96
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#ifndef _BUBBLEGUM_96_H_ -#define _BUGGLEGUM_96_H_

-/* SDRAM Definitions */ -#define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000

-/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (24000000) /* 24MHz */

-#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)

-/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0)

-/*

• • This is the initial SP which is used only briefly for relocating the u-boot
• • image to the top of SDRAM. After relocation u-boot moves the stack to the
• • proper place.
• */

-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00)

-/* UART Definitions */ -#define CONFIG_BAUDRATE 115200

-/* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

-#endif diff --git a/include/configs/owl-common.h b/include/configs/owl-common.h new file mode 100644 index 0000000..f77a5fa --- /dev/null +++ b/include/configs/owl-common.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Board configuration file for Actions Semi Owl SoCs.
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#ifndef _OWL_COMMON_CONFIG_H_ +#define _OWL_COMMON_CONFIG_H_

+/* SDRAM Definitions */ +#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CONFIG_SYS_SDRAM_SIZE 0x80000000

+/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (24000000) /* 24MHz */

+#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)

+/* Some commands use this as the default load address */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0)

+/*

• • This is the initial SP which is used only briefly for relocating the u-boot
• • image to the top of SDRAM. After relocation u-boot moves the stack to the
• • proper place.
• */

+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00)

+/* UART Definitions */ +#define CONFIG_BAUDRATE 115200

+/* Console configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

+#endif diff --git a/include/configs/s900.h b/include/configs/s900.h new file mode 100644 index 0000000..7544cfc --- /dev/null +++ b/include/configs/s900.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#ifndef _CONFIG_S900_H_ +#define _CONFIG_S900_H_

+/*

• • Include common owl configuration where most the settings are
• */

+#include <configs/owl-common.h>

+#endif

2.7.4

On Sat, Jan 25, 2020 at 05:52:44PM +0530, Amit Singh Tomar wrote:

Now that memory maps(for both S700 and S900 SoCs) can be managed using a common file, rename sysmap-s900 to sysmap-owl to reflect the same.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Reviewed-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org

Thanks, Mani

---

Changes since v2:

• Fixed the commit message and header.

Changes since v1: * compile sysmap-owl.c against CONFIG_ARM64 now.

---

arch/arm/mach-owl/Makefile | 2 +- arch/arm/mach-owl/sysmap-owl.c | 32 ++++++++++++++++++++++++++++++++ arch/arm/mach-owl/sysmap-s900.c | 32 -------------------------------- 3 files changed, 33 insertions(+), 33 deletions(-) create mode 100644 arch/arm/mach-owl/sysmap-owl.c delete mode 100644 arch/arm/mach-owl/sysmap-s900.c

diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile index 0b181c6..f3a69eb 100644 --- a/arch/arm/mach-owl/Makefile +++ b/arch/arm/mach-owl/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+

obj-y += soc.o -obj-y += sysmap-s900.o +obj-$(CONFIG_ARM64) += sysmap-owl.o diff --git a/arch/arm/mach-owl/sysmap-owl.c b/arch/arm/mach-owl/sysmap-owl.c new file mode 100644 index 0000000..81f6ca2 --- /dev/null +++ b/arch/arm/mach-owl/sysmap-owl.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Memory map for Actions Semi Owl series SoCs.
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#include <common.h> +#include <asm/armv8/mmu.h>

+static struct mm_region owl_mem_map[] = {

• {

• .virt = 0x0UL, /* DDR */
  

• .phys = 0x0UL, /* DDR */
  

• .size = 0x80000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

• 	 PTE_BLOCK_INNER_SHARE
  

• }, {

• .virt = 0xE0000000UL, /* Peripheral block */
  

• .phys = 0xE0000000UL, /* Peripheral block */
  

• .size = 0x08000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

• 	 PTE_BLOCK_NON_SHARE |
  

• 	 PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

• }, {

• /* List terminator */
  

• 0,
  

• }

+};

+struct mm_region *mem_map = owl_mem_map; diff --git a/arch/arm/mach-owl/sysmap-s900.c b/arch/arm/mach-owl/sysmap-s900.c deleted file mode 100644 index f78b639..0000000 --- a/arch/arm/mach-owl/sysmap-s900.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Actions Semi S900 Memory map
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#include <common.h> -#include <asm/armv8/mmu.h>

-static struct mm_region s900_mem_map[] = {

• {

• .virt = 0x0UL, /* DDR */
  

• .phys = 0x0UL, /* DDR */
  

• .size = 0x80000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

• 	 PTE_BLOCK_INNER_SHARE
  

• }, {

• .virt = 0xE0000000UL, /* Peripheral block */
  

• .phys = 0xE0000000UL, /* Peripheral block */
  

• .size = 0x08000000UL,
  

• .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

• 	 PTE_BLOCK_NON_SHARE |
  

• 	 PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

• }, {

• /* List terminator */
  

• 0,
  

• }

-};

-struct mm_region *mem_map = s900_mem_map;

2.7.4

On Sat, Jan 25, 2020 at 05:52:45PM +0530, Amit Singh Tomar wrote:

This patch converts S900 clock driver to something common that can be used for other SoCs, for instance S700(few of clk registres are same).

registers

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Changes since v2:

• Fixed the commit message.
• Checked for the clk->id.
• Added a .data member with SoC type.
• Removed #ifdefs from few places.

Changes since v1: * Moved CLK and CLK_OWL symbols from defconfig to arch/arm/Kconfig.

---

arch/arm/Kconfig | 2 + arch/arm/include/asm/arch-owl/clk_s900.h | 57 ----------- arch/arm/include/asm/arch-owl/regs_s700.h | 56 +++++++++++ configs/bubblegum_96_defconfig | 3 - drivers/clk/owl/Kconfig | 8 +- drivers/clk/owl/Makefile | 2 +- drivers/clk/owl/clk_owl.c | 159 ++++++++++++++++++++++++++++++ drivers/clk/owl/clk_owl.h | 65 ++++++++++++ drivers/clk/owl/clk_s900.c | 137 ------------------------- 9 files changed, 285 insertions(+), 204 deletions(-) delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h create mode 100644 drivers/clk/owl/clk_owl.c create mode 100644 drivers/clk/owl/clk_owl.h delete mode 100644 drivers/clk/owl/clk_s900.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 905118b..e6a9d32 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -886,6 +886,8 @@ config ARCH_OWL select DM select DM_SERIAL select OWL_SERIAL

• select CLK
• select CLK_OWL select OF_CONTROL imply CMD_DM

diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h b/arch/arm/include/asm/arch-owl/clk_s900.h deleted file mode 100644 index 88e88f7..0000000 --- a/arch/arm/include/asm/arch-owl/clk_s900.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Actions Semi S900 Clock Definitions
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#ifndef _OWL_CLK_S900_H_ -#define _OWL_CLK_S900_H_

-#include <clk-uclass.h>

-struct owl_clk_priv {

• phys_addr_t base;

-};

-/* BUSCLK register definitions */ -#define CMU_PDBGDIV_8 7 -#define CMU_PDBGDIV_SHIFT 26 -#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) -#define CMU_PERDIV_8 7 -#define CMU_PERDIV_SHIFT 20 -#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) -#define CMU_NOCDIV_2 1 -#define CMU_NOCDIV_SHIFT 19 -#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) -#define CMU_DMMCLK_SRC_APLL 2 -#define CMU_DMMCLK_SRC_SHIFT 10 -#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) -#define CMU_APBCLK_DIV BIT(8) -#define CMU_NOCCLK_SRC BIT(7) -#define CMU_AHBCLK_DIV BIT(4) -#define CMU_CORECLK_MASK 3 -#define CMU_CORECLK_CPLL BIT(1) -#define CMU_CORECLK_HOSC BIT(0)

-/* COREPLL register definitions */ -#define CMU_COREPLL_EN BIT(9) -#define CMU_COREPLL_HOSC_EN BIT(8) -#define CMU_COREPLL_OUT (1104 / 24)

-/* DEVPLL register definitions */ -#define CMU_DEVPLL_CLK BIT(12) -#define CMU_DEVPLL_EN BIT(8) -#define CMU_DEVPLL_OUT (660 / 6)

-/* UARTCLK register definitions */ -#define CMU_UARTCLK_SRC_DEVPLL BIT(16)

-/* DEVCLKEN1 register definitions */ -#define CMU_DEVCLKEN1_UART5 BIT(21)

-#define PLL_STABILITY_WAIT_US 50

-#endif diff --git a/arch/arm/include/asm/arch-owl/regs_s700.h b/arch/arm/include/asm/arch-owl/regs_s700.h new file mode 100644 index 0000000..a0bd737 --- /dev/null +++ b/arch/arm/include/asm/arch-owl/regs_s700.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Actions Semi S700 Register Definitions
• */

+#ifndef _OWL_REGS_S700_H_ +#define _OWL_REGS_S700_H_

+#define CMU_COREPLL (0x0000) +#define CMU_DEVPLL (0x0004) +#define CMU_DDRPLL (0x0008) +#define CMU_NANDPLL (0x000C) +#define CMU_DISPLAYPLL (0x0010) +#define CMU_AUDIOPLL (0x0014) +#define CMU_TVOUTPLL (0x0018) +#define CMU_BUSCLK (0x001C) +#define CMU_SENSORCLK (0x0020) +#define CMU_LCDCLK (0x0024) +#define CMU_DSIPLLCLK (0x0028) +#define CMU_CSICLK (0x002C) +#define CMU_DECLK (0x0030) +#define CMU_SICLK (0x0034) +#define CMU_BUSCLK1 (0x0038) +#define CMU_HDECLK (0x003C) +#define CMU_VDECLK (0x0040) +#define CMU_VCECLK (0x0044) +#define CMU_NANDCCLK (0x004C) +#define CMU_SD0CLK (0x0050) +#define CMU_SD1CLK (0x0054) +#define CMU_SD2CLK (0x0058) +#define CMU_UART0CLK (0x005C) +#define CMU_UART1CLK (0x0060) +#define CMU_UART2CLK (0x0064) +#define CMU_UART3CLK (0x0068) +#define CMU_UART4CLK (0x006C) +#define CMU_UART5CLK (0x0070) +#define CMU_UART6CLK (0x0074) +#define CMU_PWM0CLK (0x0078) +#define CMU_PWM1CLK (0x007C) +#define CMU_PWM2CLK (0x0080) +#define CMU_PWM3CLK (0x0084) +#define CMU_PWM4CLK (0x0088) +#define CMU_PWM5CLK (0x008C) +#define CMU_GPU3DCLK (0x0090) +#define CMU_CORECTL (0x009C) +#define CMU_DEVCLKEN0 (0x00A0) +#define CMU_DEVCLKEN1 (0x00A4) +#define CMU_DEVRST0 (0x00A8) +#define CMU_DEVRST1 (0x00AC) +#define CMU_USBPLL (0x00B0) +#define CMU_ETHERNETPLL (0x00B4) +#define CMU_CVBSPLL (0x00B8) +#define CMU_SSTSCLK (0x00C0)

+#endif diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index 8c94def..e76e9a2 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -17,6 +17,3 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_CLK=y -CONFIG_CLK_OWL=y -CONFIG_CLK_S900=y diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig index 661f198..b2582d3 100644 --- a/drivers/clk/owl/Kconfig +++ b/drivers/clk/owl/Kconfig @@ -3,10 +3,6 @@ config CLK_OWL depends on CLK && ARCH_OWL help Enable support for clock managemet unit present in Actions Semi

•  OWL SoCs.
  

•  S900/S700 SoCs.
  

It'd be good to keep the family name:

Enable support for clock managemet unit present in Actions Semi Owl series S900/S700 SoCs.

-config CLK_S900

•    bool "Actions Semi S900 clock driver"
  

•    depends on CLK_OWL && ARM64
  

•    help
  

•      Enable support for the clocks in Actions Semi S900 SoC.
  

diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile index 63ab573..5218b6b 100644 --- a/drivers/clk/owl/Makefile +++ b/drivers/clk/owl/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+

-obj-$(CONFIG_CLK_S900) += clk_s900.o +obj-$(CONFIG_CLK_OWL) += clk_owl.o diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c new file mode 100644 index 0000000..050dd45 --- /dev/null +++ b/drivers/clk/owl/clk_owl.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Common clock driver for Actions Semi SoCs.
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#include <common.h> +#include <dm.h> +#include "clk_owl.h" +#include <asm/io.h> +#if defined(CONFIG_MACH_S900) +#include <asm/arch-owl/regs_s900.h> +#include <dt-bindings/clock/actions,s900-cmu.h> +#elif defined(CONFIG_MACH_S700) +#include <asm/arch-owl/regs_s700.h> +#include <dt-bindings/clock/actions,s700-cmu.h> +#endif

+void owl_clk_init(struct owl_clk_priv *priv) +{

• u32 bus_clk = 0, core_pll, dev_pll;

+#if defined(CONFIG_MACH_S900)

• /* Enable ASSIST_PLL */
• setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
• udelay(PLL_STABILITY_WAIT_US);

+#endif

It'd be interesting to see how we can add support for S500 which is somewhat different with these configurations... Let's do that later.

• /* Source HOSC to DEV_CLK */
• clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• /* Configure BUS_CLK */
• bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |

• 	CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
  

• 	CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  

• writel(bus_clk, priv->base + CMU_BUSCLK);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure CORE_PLL */
• core_pll = readl(priv->base + CMU_COREPLL);
• core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
• writel(core_pll, priv->base + CMU_COREPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure DEV_PLL */
• dev_pll = readl(priv->base + CMU_DEVPLL);
• dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
• writel(dev_pll, priv->base + CMU_DEVPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Source CORE_PLL for CORE_CLK */
• clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,

• 	CMU_CORECLK_CPLL);
  

• /* Source DEV_PLL for DEV_CLK */
• setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• udelay(PLL_STABILITY_WAIT_US);

+}

+void owl_uart_clk_enable(struct owl_clk_priv *priv) +{

• if (priv->soc == S900) {

• /* Source HOSC for UART5 interface */
  

• clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
  

• /* Enable UART5 interface clock */
  

• setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
  

• } else if (priv->soc == S700) {

• /* Source HOSC for UART3 interface */
  

• clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
  

• /* Enable UART3 interface clock */
  

• setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
  

• }

+}

+void owl_ether_clk_enable(struct owl_clk_priv *priv) +{ +#if defined(CONFIG_MACH_S700)

Either use `priv->soc` or the guard throughout the driver. Please don't mix both.

• setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH_S700);
• setbits_le32(priv->base + CMU_ETHERNETPLL, 5);

+#endif +}

+int owl_clk_enable(struct clk *clk) +{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLK_UART5:
• case CLK_UART3:

• owl_uart_clk_enable(priv);
  

• break;
  

• case CLK_RMII_REF:
• case CLK_ETHERNET:

• owl_ether_clk_enable(priv);
  

• break;
  

• default:

• return 0;
  

Why not return -EINVAL for default case?

• }
• return 0;

+}

+int owl_clk_disable(struct clk *clk) +{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• if (priv->soc == S900) {

• /* Disable UART5 interface clock */
  

• clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
  

• } else if (priv->soc == S700) {

• /* Disable UART3 interface clock */
  

• clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
  

• }
• return 0;

+}

+static int owl_clk_probe(struct udevice *dev) +{

• struct owl_clk_priv *priv = dev_get_priv(dev);
• priv->base = dev_read_addr(dev);
• if (priv->base == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• /* setup necessary clocks */
• owl_clk_init(priv);
• return 0;

+}

+static const struct clk_ops owl_clk_ops = {

• .enable = owl_clk_enable,
• .disable = owl_clk_disable,

+};

+static const struct udevice_id owl_clk_ids[] = { +#if defined(CONFIG_MACH_S900)

• { .compatible = "actions,s900-cmu", .data = S900 },

+#elif defined(CONFIG_MACH_S700)

• { .compatible = "actions,s700-cmu", .data = S700 },
• { }

+#endif

Guard is not necessary here.

Thanks, Mani

+};

+U_BOOT_DRIVER(clk_owl) = {

• .name = "clk_owl",
• .id = UCLASS_CLK,
• .of_match = owl_clk_ids,
• .ops = &owl_clk_ops,
• .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
• .probe = owl_clk_probe,

+}; diff --git a/drivers/clk/owl/clk_owl.h b/drivers/clk/owl/clk_owl.h new file mode 100644 index 0000000..9a65091 --- /dev/null +++ b/drivers/clk/owl/clk_owl.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Actions Semi SoCs Clock Definitions
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#ifndef _OWL_CLK_H_ +#define _OWL_CLK_H_

+#include <clk-uclass.h>

+enum owl_soc {

• S700,
• S900,

+};

+struct owl_clk_priv {

• phys_addr_t base;
• enum owl_soc soc;

+};

+/* BUSCLK register definitions */ +#define CMU_PDBGDIV_8 7 +#define CMU_PDBGDIV_SHIFT 26 +#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) +#define CMU_PERDIV_8 7 +#define CMU_PERDIV_SHIFT 20 +#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) +#define CMU_NOCDIV_2 1 +#define CMU_NOCDIV_SHIFT 19 +#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) +#define CMU_DMMCLK_SRC_APLL 2 +#define CMU_DMMCLK_SRC_SHIFT 10 +#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) +#define CMU_APBCLK_DIV BIT(8) +#define CMU_NOCCLK_SRC BIT(7) +#define CMU_AHBCLK_DIV BIT(4) +#define CMU_CORECLK_MASK 3 +#define CMU_CORECLK_CPLL BIT(1) +#define CMU_CORECLK_HOSC BIT(0)

+/* COREPLL register definitions */ +#define CMU_COREPLL_EN BIT(9) +#define CMU_COREPLL_HOSC_EN BIT(8) +#define CMU_COREPLL_OUT (1104 / 24)

+/* DEVPLL register definitions */ +#define CMU_DEVPLL_CLK BIT(12) +#define CMU_DEVPLL_EN BIT(8) +#define CMU_DEVPLL_OUT (660 / 6)

+/* UARTCLK register definitions */ +#define CMU_UARTCLK_SRC_DEVPLL BIT(16)

+#define PLL_STABILITY_WAIT_US 50

+#define CMU_DEVCLKEN1_UART5 BIT(21) +#define CMU_DEVCLKEN1_UART3 BIT(11)

+#define CMU_DEVCLKEN1_ETH_S700 BIT(23)

+#endif diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c deleted file mode 100644 index a7c15d2..0000000 --- a/drivers/clk/owl/clk_s900.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Actions Semi S900 clock driver
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#include <common.h> -#include <dm.h> -#include <asm/arch-owl/clk_s900.h> -#include <asm/arch-owl/regs_s900.h> -#include <asm/io.h>

-#include <dt-bindings/clock/s900_cmu.h>

-void owl_clk_init(struct owl_clk_priv *priv) -{

• u32 bus_clk = 0, core_pll, dev_pll;
• /* Enable ASSIST_PLL */
• setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
• udelay(PLL_STABILITY_WAIT_US);
• /* Source HOSC to DEV_CLK */
• clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• /* Configure BUS_CLK */
• bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |

• 	CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
  

• 	CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  

• writel(bus_clk, priv->base + CMU_BUSCLK);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure CORE_PLL */
• core_pll = readl(priv->base + CMU_COREPLL);
• core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
• writel(core_pll, priv->base + CMU_COREPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure DEV_PLL */
• dev_pll = readl(priv->base + CMU_DEVPLL);
• dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
• writel(dev_pll, priv->base + CMU_DEVPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Source CORE_PLL for CORE_CLK */
• clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,

• 	CMU_CORECLK_CPLL);
  

• /* Source DEV_PLL for DEV_CLK */
• setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• udelay(PLL_STABILITY_WAIT_US);

-}

-void owl_uart_clk_enable(struct owl_clk_priv *priv) -{

• /* Source HOSC for UART5 interface */
• clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
• /* Enable UART5 interface clock */
• setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);

-}

-void owl_uart_clk_disable(struct owl_clk_priv *priv) -{

• /* Disable UART5 interface clock */
• clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);

-}

-int owl_clk_enable(struct clk *clk) -{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLOCK_UART5:

• owl_uart_clk_enable(priv);
  

• break;
  

• default:

• return 0;
  

• }
• return 0;

-}

-int owl_clk_disable(struct clk *clk) -{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLOCK_UART5:

• owl_uart_clk_disable(priv);
  

• break;
  

• default:

• return 0;
  

• }
• return 0;

-}

-static int owl_clk_probe(struct udevice *dev) -{

• struct owl_clk_priv *priv = dev_get_priv(dev);
• priv->base = dev_read_addr(dev);
• if (priv->base == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• /* setup necessary clocks */
• owl_clk_init(priv);
• return 0;

-}

-static struct clk_ops owl_clk_ops = {

• .enable = owl_clk_enable,
• .disable = owl_clk_disable,

-};

-static const struct udevice_id owl_clk_ids[] = {

• { .compatible = "actions,s900-cmu" },
• { }

-};

-U_BOOT_DRIVER(clk_owl) = {

• .name = "clk_s900",
• .id = UCLASS_CLK,
• .of_match = owl_clk_ids,
• .ops = &owl_clk_ops,
• .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
• .probe = owl_clk_probe,

-};

2.7.4

On 23/02/2020 17:25, Manivannan Sadhasivam wrote:

Hi,

On Sat, Jan 25, 2020 at 05:52:45PM +0530, Amit Singh Tomar wrote:

...

This patch converts S900 clock driver to something common that can be used for other SoCs, for instance S700(few of clk registres are same).

registers

...

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Changes since v2:

• Fixed the commit message.
• Checked for the clk->id.
• Added a .data member with SoC type.
• Removed #ifdefs from few places.

Changes since v1: * Moved CLK and CLK_OWL symbols from defconfig to arch/arm/Kconfig.

---

arch/arm/Kconfig | 2 + arch/arm/include/asm/arch-owl/clk_s900.h | 57 ----------- arch/arm/include/asm/arch-owl/regs_s700.h | 56 +++++++++++ configs/bubblegum_96_defconfig | 3 - drivers/clk/owl/Kconfig | 8 +- drivers/clk/owl/Makefile | 2 +- drivers/clk/owl/clk_owl.c | 159 ++++++++++++++++++++++++++++++ drivers/clk/owl/clk_owl.h | 65 ++++++++++++ drivers/clk/owl/clk_s900.c | 137 ------------------------- 9 files changed, 285 insertions(+), 204 deletions(-) delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h create mode 100644 drivers/clk/owl/clk_owl.c create mode 100644 drivers/clk/owl/clk_owl.h delete mode 100644 drivers/clk/owl/clk_s900.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 905118b..e6a9d32 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -886,6 +886,8 @@ config ARCH_OWL select DM select DM_SERIAL select OWL_SERIAL

• select CLK
• select CLK_OWL select OF_CONTROL imply CMD_DM

diff --git a/arch/arm/include/asm/arch-owl/clk_s900.h b/arch/arm/include/asm/arch-owl/clk_s900.h deleted file mode 100644 index 88e88f7..0000000 --- a/arch/arm/include/asm/arch-owl/clk_s900.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Actions Semi S900 Clock Definitions
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#ifndef _OWL_CLK_S900_H_ -#define _OWL_CLK_S900_H_

-#include <clk-uclass.h>

-struct owl_clk_priv {

• phys_addr_t base;

-};

-/* BUSCLK register definitions */ -#define CMU_PDBGDIV_8 7 -#define CMU_PDBGDIV_SHIFT 26 -#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) -#define CMU_PERDIV_8 7 -#define CMU_PERDIV_SHIFT 20 -#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) -#define CMU_NOCDIV_2 1 -#define CMU_NOCDIV_SHIFT 19 -#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) -#define CMU_DMMCLK_SRC_APLL 2 -#define CMU_DMMCLK_SRC_SHIFT 10 -#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) -#define CMU_APBCLK_DIV BIT(8) -#define CMU_NOCCLK_SRC BIT(7) -#define CMU_AHBCLK_DIV BIT(4) -#define CMU_CORECLK_MASK 3 -#define CMU_CORECLK_CPLL BIT(1) -#define CMU_CORECLK_HOSC BIT(0)

-/* COREPLL register definitions */ -#define CMU_COREPLL_EN BIT(9) -#define CMU_COREPLL_HOSC_EN BIT(8) -#define CMU_COREPLL_OUT (1104 / 24)

-/* DEVPLL register definitions */ -#define CMU_DEVPLL_CLK BIT(12) -#define CMU_DEVPLL_EN BIT(8) -#define CMU_DEVPLL_OUT (660 / 6)

-/* UARTCLK register definitions */ -#define CMU_UARTCLK_SRC_DEVPLL BIT(16)

-/* DEVCLKEN1 register definitions */ -#define CMU_DEVCLKEN1_UART5 BIT(21)

-#define PLL_STABILITY_WAIT_US 50

-#endif diff --git a/arch/arm/include/asm/arch-owl/regs_s700.h b/arch/arm/include/asm/arch-owl/regs_s700.h new file mode 100644 index 0000000..a0bd737 --- /dev/null +++ b/arch/arm/include/asm/arch-owl/regs_s700.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Actions Semi S700 Register Definitions
• */

+#ifndef _OWL_REGS_S700_H_ +#define _OWL_REGS_S700_H_

+#define CMU_COREPLL (0x0000) +#define CMU_DEVPLL (0x0004) +#define CMU_DDRPLL (0x0008) +#define CMU_NANDPLL (0x000C) +#define CMU_DISPLAYPLL (0x0010) +#define CMU_AUDIOPLL (0x0014) +#define CMU_TVOUTPLL (0x0018) +#define CMU_BUSCLK (0x001C) +#define CMU_SENSORCLK (0x0020) +#define CMU_LCDCLK (0x0024) +#define CMU_DSIPLLCLK (0x0028) +#define CMU_CSICLK (0x002C) +#define CMU_DECLK (0x0030) +#define CMU_SICLK (0x0034) +#define CMU_BUSCLK1 (0x0038) +#define CMU_HDECLK (0x003C) +#define CMU_VDECLK (0x0040) +#define CMU_VCECLK (0x0044) +#define CMU_NANDCCLK (0x004C) +#define CMU_SD0CLK (0x0050) +#define CMU_SD1CLK (0x0054) +#define CMU_SD2CLK (0x0058) +#define CMU_UART0CLK (0x005C) +#define CMU_UART1CLK (0x0060) +#define CMU_UART2CLK (0x0064) +#define CMU_UART3CLK (0x0068) +#define CMU_UART4CLK (0x006C) +#define CMU_UART5CLK (0x0070) +#define CMU_UART6CLK (0x0074) +#define CMU_PWM0CLK (0x0078) +#define CMU_PWM1CLK (0x007C) +#define CMU_PWM2CLK (0x0080) +#define CMU_PWM3CLK (0x0084) +#define CMU_PWM4CLK (0x0088) +#define CMU_PWM5CLK (0x008C) +#define CMU_GPU3DCLK (0x0090) +#define CMU_CORECTL (0x009C) +#define CMU_DEVCLKEN0 (0x00A0) +#define CMU_DEVCLKEN1 (0x00A4) +#define CMU_DEVRST0 (0x00A8) +#define CMU_DEVRST1 (0x00AC) +#define CMU_USBPLL (0x00B0) +#define CMU_ETHERNETPLL (0x00B4) +#define CMU_CVBSPLL (0x00B8) +#define CMU_SSTSCLK (0x00C0)

+#endif diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig index 8c94def..e76e9a2 100644 --- a/configs/bubblegum_96_defconfig +++ b/configs/bubblegum_96_defconfig @@ -17,6 +17,3 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIMER=y CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_CLK=y -CONFIG_CLK_OWL=y -CONFIG_CLK_S900=y diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig index 661f198..b2582d3 100644 --- a/drivers/clk/owl/Kconfig +++ b/drivers/clk/owl/Kconfig @@ -3,10 +3,6 @@ config CLK_OWL depends on CLK && ARCH_OWL help Enable support for clock managemet unit present in Actions Semi

•  OWL SoCs.
  

•  S900/S700 SoCs.
  

It'd be good to keep the family name:

Enable support for clock managemet unit present in Actions Semi Owl series S900/S700 SoCs.

...

-config CLK_S900

•    bool "Actions Semi S900 clock driver"
  

•    depends on CLK_OWL && ARM64
  

•    help
  

•      Enable support for the clocks in Actions Semi S900 SoC.
  

diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile index 63ab573..5218b6b 100644 --- a/drivers/clk/owl/Makefile +++ b/drivers/clk/owl/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+

-obj-$(CONFIG_CLK_S900) += clk_s900.o +obj-$(CONFIG_CLK_OWL) += clk_owl.o diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c new file mode 100644 index 0000000..050dd45 --- /dev/null +++ b/drivers/clk/owl/clk_owl.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Common clock driver for Actions Semi SoCs.
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#include <common.h> +#include <dm.h> +#include "clk_owl.h" +#include <asm/io.h> +#if defined(CONFIG_MACH_S900) +#include <asm/arch-owl/regs_s900.h> +#include <dt-bindings/clock/actions,s900-cmu.h> +#elif defined(CONFIG_MACH_S700) +#include <asm/arch-owl/regs_s700.h> +#include <dt-bindings/clock/actions,s700-cmu.h> +#endif

+void owl_clk_init(struct owl_clk_priv *priv) +{

• u32 bus_clk = 0, core_pll, dev_pll;

+#if defined(CONFIG_MACH_S900)

• /* Enable ASSIST_PLL */
• setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
• udelay(PLL_STABILITY_WAIT_US);

+#endif

It'd be interesting to see how we can add support for S500 which is somewhat different with these configurations... Let's do that later.

...

• /* Source HOSC to DEV_CLK */
• clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• /* Configure BUS_CLK */
• bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |

• 	CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
  

• 	CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  

• writel(bus_clk, priv->base + CMU_BUSCLK);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure CORE_PLL */
• core_pll = readl(priv->base + CMU_COREPLL);
• core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
• writel(core_pll, priv->base + CMU_COREPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure DEV_PLL */
• dev_pll = readl(priv->base + CMU_DEVPLL);
• dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
• writel(dev_pll, priv->base + CMU_DEVPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Source CORE_PLL for CORE_CLK */
• clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,

• 	CMU_CORECLK_CPLL);
  

• /* Source DEV_PLL for DEV_CLK */
• setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• udelay(PLL_STABILITY_WAIT_US);

+}

+void owl_uart_clk_enable(struct owl_clk_priv *priv) +{

• if (priv->soc == S900) {

• /* Source HOSC for UART5 interface */
  

• clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
  

• /* Enable UART5 interface clock */
  

• setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
  

• } else if (priv->soc == S700) {

• /* Source HOSC for UART3 interface */
  

• clrbits_le32(priv->base + CMU_UART3CLK, CMU_UARTCLK_SRC_DEVPLL);
  

• /* Enable UART3 interface clock */
  

• setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
  

• }

+}

+void owl_ether_clk_enable(struct owl_clk_priv *priv) +{ +#if defined(CONFIG_MACH_S700)

Either use `priv->soc` or the guard throughout the driver. Please don't mix both.

I think the idea is to use priv->soc wherever possible, but revert to the #ifdef guards where this affects SoC specific register offsets. This prevents us from dummy-defining CMU_DEVCLKEN1_ETH_S700 for the S900, for instance.

...

• setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH_S700);
• setbits_le32(priv->base + CMU_ETHERNETPLL, 5);

+#endif +}

+int owl_clk_enable(struct clk *clk) +{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLK_UART5:
• case CLK_UART3:

• owl_uart_clk_enable(priv);
  

• break;
  

• case CLK_RMII_REF:
• case CLK_ETHERNET:

• owl_ether_clk_enable(priv);
  

• break;
  

• default:

• return 0;
  

Why not return -EINVAL for default case?

...

• }
• return 0;

+}

+int owl_clk_disable(struct clk *clk) +{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• if (priv->soc == S900) {

• /* Disable UART5 interface clock */
  

• clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
  

• } else if (priv->soc == S700) {

• /* Disable UART3 interface clock */
  

• clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART3);
  

• }
• return 0;

+}

+static int owl_clk_probe(struct udevice *dev) +{

• struct owl_clk_priv *priv = dev_get_priv(dev);
• priv->base = dev_read_addr(dev);
• if (priv->base == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• /* setup necessary clocks */
• owl_clk_init(priv);
• return 0;

+}

+static const struct clk_ops owl_clk_ops = {

• .enable = owl_clk_enable,
• .disable = owl_clk_disable,

+};

+static const struct udevice_id owl_clk_ids[] = { +#if defined(CONFIG_MACH_S900)

• { .compatible = "actions,s900-cmu", .data = S900 },

+#elif defined(CONFIG_MACH_S700)

• { .compatible = "actions,s700-cmu", .data = S700 },
• { }

+#endif

Guard is not necessary here.

Indeed, but it's here to not give false impressions: Despite the joint code, the clock driver only works for one SoC at a time. Having only that one respective compatible string in here makes this obvious.

The main reason for this approach is that the register offsets are quite different, dissecting this at runtime does not sound worthwhile for just those few clocks that we need. So the idea was to go with one source file, to make use of the commonalities of the clocks, but use #ifdef guards where needed.

This admittedly starts to look quite messy. And with the Ethernet clocks in it is probably already at a point where proper separation would be better.

So to make this easier: Amit, can you remove the Ethernet clocks from this patch, and add them later in your Ethernet series? Maybe this buys us some time to refactor this meanwhile?

Cheers, Andre

...

+};

+U_BOOT_DRIVER(clk_owl) = {

• .name = "clk_owl",
• .id = UCLASS_CLK,
• .of_match = owl_clk_ids,
• .ops = &owl_clk_ops,
• .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
• .probe = owl_clk_probe,

+}; diff --git a/drivers/clk/owl/clk_owl.h b/drivers/clk/owl/clk_owl.h new file mode 100644 index 0000000..9a65091 --- /dev/null +++ b/drivers/clk/owl/clk_owl.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Actions Semi SoCs Clock Definitions
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

+#ifndef _OWL_CLK_H_ +#define _OWL_CLK_H_

+#include <clk-uclass.h>

+enum owl_soc {

• S700,
• S900,

+};

+struct owl_clk_priv {

• phys_addr_t base;
• enum owl_soc soc;

+};

+/* BUSCLK register definitions */ +#define CMU_PDBGDIV_8 7 +#define CMU_PDBGDIV_SHIFT 26 +#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) +#define CMU_PERDIV_8 7 +#define CMU_PERDIV_SHIFT 20 +#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) +#define CMU_NOCDIV_2 1 +#define CMU_NOCDIV_SHIFT 19 +#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) +#define CMU_DMMCLK_SRC_APLL 2 +#define CMU_DMMCLK_SRC_SHIFT 10 +#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) +#define CMU_APBCLK_DIV BIT(8) +#define CMU_NOCCLK_SRC BIT(7) +#define CMU_AHBCLK_DIV BIT(4) +#define CMU_CORECLK_MASK 3 +#define CMU_CORECLK_CPLL BIT(1) +#define CMU_CORECLK_HOSC BIT(0)

+/* COREPLL register definitions */ +#define CMU_COREPLL_EN BIT(9) +#define CMU_COREPLL_HOSC_EN BIT(8) +#define CMU_COREPLL_OUT (1104 / 24)

+/* DEVPLL register definitions */ +#define CMU_DEVPLL_CLK BIT(12) +#define CMU_DEVPLL_EN BIT(8) +#define CMU_DEVPLL_OUT (660 / 6)

+/* UARTCLK register definitions */ +#define CMU_UARTCLK_SRC_DEVPLL BIT(16)

+#define PLL_STABILITY_WAIT_US 50

+#define CMU_DEVCLKEN1_UART5 BIT(21) +#define CMU_DEVCLKEN1_UART3 BIT(11)

+#define CMU_DEVCLKEN1_ETH_S700 BIT(23)

+#endif diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c deleted file mode 100644 index a7c15d2..0000000 --- a/drivers/clk/owl/clk_s900.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Actions Semi S900 clock driver
• • Copyright (C) 2015 Actions Semi Co., Ltd.
• • Copyright (C) 2018 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org
• */

-#include <common.h> -#include <dm.h> -#include <asm/arch-owl/clk_s900.h> -#include <asm/arch-owl/regs_s900.h> -#include <asm/io.h>

-#include <dt-bindings/clock/s900_cmu.h>

-void owl_clk_init(struct owl_clk_priv *priv) -{

• u32 bus_clk = 0, core_pll, dev_pll;
• /* Enable ASSIST_PLL */
• setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
• udelay(PLL_STABILITY_WAIT_US);
• /* Source HOSC to DEV_CLK */
• clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• /* Configure BUS_CLK */
• bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |

• 	CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
  

• 	CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
  

• writel(bus_clk, priv->base + CMU_BUSCLK);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure CORE_PLL */
• core_pll = readl(priv->base + CMU_COREPLL);
• core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
• writel(core_pll, priv->base + CMU_COREPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Configure DEV_PLL */
• dev_pll = readl(priv->base + CMU_DEVPLL);
• dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
• writel(dev_pll, priv->base + CMU_DEVPLL);
• udelay(PLL_STABILITY_WAIT_US);
• /* Source CORE_PLL for CORE_CLK */
• clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,

• 	CMU_CORECLK_CPLL);
  

• /* Source DEV_PLL for DEV_CLK */
• setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
• udelay(PLL_STABILITY_WAIT_US);

-}

-void owl_uart_clk_enable(struct owl_clk_priv *priv) -{

• /* Source HOSC for UART5 interface */
• clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
• /* Enable UART5 interface clock */
• setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);

-}

-void owl_uart_clk_disable(struct owl_clk_priv *priv) -{

• /* Disable UART5 interface clock */
• clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);

-}

-int owl_clk_enable(struct clk *clk) -{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLOCK_UART5:

• owl_uart_clk_enable(priv);
  

• break;
  

• default:

• return 0;
  

• }
• return 0;

-}

-int owl_clk_disable(struct clk *clk) -{

• struct owl_clk_priv *priv = dev_get_priv(clk->dev);
• switch (clk->id) {
• case CLOCK_UART5:

• owl_uart_clk_disable(priv);
  

• break;
  

• default:

• return 0;
  

• }
• return 0;

-}

-static int owl_clk_probe(struct udevice *dev) -{

• struct owl_clk_priv *priv = dev_get_priv(dev);
• priv->base = dev_read_addr(dev);
• if (priv->base == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• /* setup necessary clocks */
• owl_clk_init(priv);
• return 0;

-}

-static struct clk_ops owl_clk_ops = {

• .enable = owl_clk_enable,
• .disable = owl_clk_disable,

-};

-static const struct udevice_id owl_clk_ids[] = {

• { .compatible = "actions,s900-cmu" },
• { }

-};

-U_BOOT_DRIVER(clk_owl) = {

• .name = "clk_s900",
• .id = UCLASS_CLK,
• .of_match = owl_clk_ids,
• .ops = &owl_clk_ops,
• .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
• .probe = owl_clk_probe,

-};

2.7.4

On Sun, 23 Feb 2020 23:08:25 +0530 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org wrote:

Hi Amit,

On Sat, Jan 25, 2020 at 05:52:51PM +0530, Amit Singh Tomar wrote:

...

Right now, Clock bindings for ethernet uses different names(even in Linux) CLK_ETH_MAC for S900 and CLK_ETHERNET for S700, It causes compilation problem when using them for common clock driver.

Let's use same name CLK_ETHERNET for both S700 and S900.

So are you changing the include file that you just imported from Linux? I don't think that's a good idea, as you start to divert from the kernel in a subtle way. And especially the header files should stay unchanged. So either you send this patch to the kernel first, or, probably better, you drop this change here, and unify the name at the point where it's used (#ifndef CLK_ETHERNET ....)

Cheers, Andre.

...

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Reviewed-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org

Thanks, Mani

...

---

Changes since v2:

• Newly added patch, not there in v2/v1.

---

include/dt-bindings/clock/actions,s900-cmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h index 7c12515..2247f1c 100644 --- a/include/dt-bindings/clock/actions,s900-cmu.h +++ b/include/dt-bindings/clock/actions,s900-cmu.h @@ -121,7 +121,7 @@ #define CLK_DDR1 97 #define CLK_DMM 98

-#define CLK_ETH_MAC 99 +#define CLK_ETHERNET 99 #define CLK_RMII_REF 100

#define CLK_NR_CLKS (CLK_RMII_REF + 1)

2.7.4

On Sat, Jan 25, 2020 at 05:52:52PM +0530, Amit Singh Tomar wrote:

UART controller present on S700 is compatible with existing S900 controller, this patch simply adds a proper compatible string so that owl uart driver can be reused for S700.

Reviewed-by: Andre Przywara andre.przywara@arm.com Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

---

Changes since v2: * No changes. Changes since v1: * No changes.

---

drivers/serial/serial_owl.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c index 7ead73e..76995bf 100644 --- a/drivers/serial/serial_owl.c +++ b/drivers/serial/serial_owl.c @@ -121,6 +121,7 @@ static const struct dm_serial_ops owl_serial_ops = {

static const struct udevice_id owl_serial_ids[] = { { .compatible = "actions,s900-serial" },

• { .compatible = "actions,owl-uart" },

Either use s900 and s700 or owl.

Thanks, Mani

{ } };

-- 2.7.4

On Sat, Jan 25, 2020 at 05:52:53PM +0530, Amit Singh Tomar wrote:

The Cubieboard is a single board computer containing a Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).

This patch adds respective defconfig alongwith device tree(sync with Linux v5.5-rc6).

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com

Reviewed-by: Manivannan Sadhasivam manivannan.sadhasivam@linaro.org

Thanks, Mani

---

Changes since v2:

• Synced with Linux tag v5.5-rc6.

Changes since v1: * No changes.

---

arch/arm/dts/s700-cubieboard7.dts | 92 +++++++++++++++++++++++++++++++++++++++ configs/cubieboard7_defconfig | 16 +++++++ 2 files changed, 108 insertions(+) create mode 100644 arch/arm/dts/s700-cubieboard7.dts create mode 100644 configs/cubieboard7_defconfig

diff --git a/arch/arm/dts/s700-cubieboard7.dts b/arch/arm/dts/s700-cubieboard7.dts new file mode 100644 index 0000000..63e375c --- /dev/null +++ b/arch/arm/dts/s700-cubieboard7.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/*

• • Copyright (c) 2017 Andreas Färber
• */

+/dts-v1/;

+#include "s700.dtsi"

+/ {

• compatible = "cubietech,cubieboard7", "actions,s700";
• model = "CubieBoard7";
• aliases {

• serial3 = &uart3;
  

• };
• chosen {

• stdout-path = "serial3:115200n8";
  

• };
• memory@0 {

• device_type = "memory";
  

• reg = <0x0 0x0 0x0 0x80000000>;
  

• };
• memory@1,e0000000 {

• device_type = "memory";
  

• reg = <0x1 0xe0000000 0x0 0x0>;
  

• };

+};

+&i2c0 {

• status = "okay";
• pinctrl-names = "default";
• pinctrl-0 = <&i2c0_default>;

+};

+&i2c1 {

• status = "okay";
• pinctrl-names = "default";
• pinctrl-0 = <&i2c1_default>;

+};

+&i2c2 {

• status = "disabled";
• pinctrl-names = "default";
• pinctrl-0 = <&i2c2_default>;

+};

+&pinctrl {

• i2c0_default: i2c0_default {

• pinmux {
  

• 	groups = "i2c0_mfp";
  

• 	function = "i2c0";
  

• };
  

• pinconf {
  

• 	pins = "i2c0_sclk", "i2c0_sdata";
  

• 	bias-pull-up;
  

• };
  

• };
• i2c1_default: i2c1_default {

• pinmux {
  

• 	groups = "i2c1_dummy";
  

• 	function = "i2c1";
  

• };
  

• pinconf {
  

• 	pins = "i2c1_sclk", "i2c1_sdata";
  

• 	bias-pull-up;
  

• };
  

• };
• i2c2_default: i2c2_default {

• pinmux {
  

• 	groups = "i2c2_dummy";
  

• 	function = "i2c2";
  

• };
  

• pinconf {
  

• 	pins = "i2c2_sclk", "i2c2_sdata";
  

• 	bias-pull-up;
  

• };
  

• };

+};

+&timer {

• clocks = <&hosc>;

+};

+&uart3 {

• status = "okay";

+}; diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig new file mode 100644 index 0000000..0459997 --- /dev/null +++ b/configs/cubieboard7_defconfig @@ -0,0 +1,16 @@ +CONFIG_ARM=y +CONFIG_ARCH_OWL=y +CONFIG_MACH_S700=y +CONFIG_IDENT_STRING="\ncubieboard7" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyOWL3,115200n8" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="U-Boot => " +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_TIMER=y

+CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7"

2.7.4

On Sat, Jan 25, 2020 at 05:52:57PM +0530, Amit Singh Tomar wrote:

The simplest and most generic form of a reset controller just exposes multiple MMIO registers, where each bit toggles a separate reset line. Add a generic driver to describe this kind of reset controller.

This is used on the Action Semi S700, for instance, but also by other SoCs.

Why not name it as reset-simple as linux kernel?

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com [Andre: make more generic, let it cover multiple registers, slight rework] Signed-off-by: Andre Przywara andre.przywara@arm.com

---

Changes since v2: * Newly added patch, not there in v2/v1.

---

drivers/reset/Kconfig | 6 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-generic.c | 111 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 drivers/reset/reset-generic.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 75ccd65..1cdc159 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -12,6 +12,12 @@ config DM_RESET although driving such reset isgnals using GPIOs may be more appropriate in this case.

+config GENERIC_RESET

•    bool "Generic Reset controller driver"
  

•    depends on DM_RESET
  

•    help
  

•      Support Generic reset controller.
  

config SANDBOX_RESET bool "Enable the sandbox reset test driver" depends on DM_MAILBOX && SANDBOX diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 0a044d5..5e027a1 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -4,6 +4,7 @@ #

obj-$(CONFIG_DM_RESET) += reset-uclass.o +obj-$(CONFIG_GENERIC_RESET) += reset-generic.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o obj-$(CONFIG_STI_RESET) += sti-reset.o diff --git a/drivers/reset/reset-generic.c b/drivers/reset/reset-generic.c new file mode 100644 index 0000000..9c45087 --- /dev/null +++ b/drivers/reset/reset-generic.c @@ -0,0 +1,111 @@ +/*

• • Copyright (C) 2017 Amit Singh Tomar amittomer25@gmail.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <reset-uclass.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h>

+DECLARE_GLOBAL_DATA_PTR;

+struct generic_reset_priv {

• void __iomem *membase;
• int max_reset;

+};

+#define BITS_PER_BYTE 8 +static int generic_reset_toggle(struct reset_ctl *rst, bool assert) +{

• struct generic_reset_priv *priv = dev_get_priv(rst->dev);
• int reg_width = sizeof(u32);
• int bank, offset;
• u32 reg;
• if (rst->id >= priv->max_reset)

• return -EINVAL;
  

• bank = rst->id / (reg_width * BITS_PER_BYTE);
• offset = rst->id % (reg_width * BITS_PER_BYTE);
• reg = readl(priv->membase + (bank * reg_width));
• if (assert)

• writel(reg & ~BIT(offset), priv->membase + (bank * reg_width));
  

• else

• writel(reg | BIT(offset), priv->membase + (bank * reg_width));
  

• return 0;

+}

+static int generic_reset_assert(struct reset_ctl *rst) +{

• return generic_reset_toggle(rst, true);

+}

+static int generic_reset_deassert(struct reset_ctl *rst) +{

• return generic_reset_toggle(rst, false);

+}

+static int generic_reset_free(struct reset_ctl *rst) +{

• return 0;

+}

+static int generic_reset_request(struct reset_ctl *rst) +{

• struct generic_reset_priv *priv = dev_get_priv(rst->dev);
• if (rst->id >= priv->max_reset)

• return -EINVAL;
  

• return generic_reset_assert(rst);

+}

+struct reset_ops generic_reset_reset_ops = {

• .free = generic_reset_free,
• .request = generic_reset_request,
• .rst_assert = generic_reset_assert,
• .rst_deassert = generic_reset_deassert,

+};

+static const struct udevice_id generic_reset_ids[] = {

• { .compatible = "generic-reset" },
• { .compatible = "actions,s700-reset" },

No need of S700 specific compatible here. Linux kernel dts also doesn't require it.

Thanks, Mani

• { }

+};

+static int generic_reset_probe(struct udevice *dev) +{

• struct generic_reset_priv *priv = dev_get_priv(dev);
• fdt_addr_t addr;
• fdt_size_t size;
• addr = devfdt_get_addr_size_index(dev, 0, &size);
• if (addr == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• priv->max_reset = dev_read_u32_default(dev, "num-resets", -1);
• if (priv->max_reset == -1)

• priv->max_reset = size * BITS_PER_BYTE;
  

• priv->membase = devm_ioremap(dev, addr, size);
• if (!priv->membase)

• return -EFAULT;
  

• return 0;

+}

+U_BOOT_DRIVER(generic_reset) = {

• .name = "generic_reset",
• .id = UCLASS_RESET,
• .of_match = generic_reset_ids,
• .ops = &generic_reset_reset_ops,
• .probe = generic_reset_probe,
• .priv_auto_alloc_size = sizeof(struct generic_reset_priv),

+};

2.7.4

On Sat, 25 Jan 2020 17:52:57 +0530 Amit Singh Tomar amittomer25@gmail.com wrote:

Hi,

The simplest and most generic form of a reset controller just exposes multiple MMIO registers, where each bit toggles a separate reset line. Add a generic driver to describe this kind of reset controller.

This is used on the Action Semi S700, for instance, but also by other SoCs.

As tempting as this may be, but the S900 uses the more common style of integrating the reset controller in the CMU device: mmc0: mmc@e0330000 { ... clocks = <&cmu CLK_SD0>; resets = <&cmu RESET_SD0>; ...

So you should probably follow suit here for the S700 as well, especially as the Linux S700 CMU driver already defines resets, they just don't seem to be used yet.

So please drop this patch and the next one, and integrate the reset functionality in clk_owl.c, similar to what we do for sunxi.

Cheers, Andre.

P.S. I agree with Mani that the Ethernet patches should be a separate series.

Signed-off-by: Amit Singh Tomar amittomer25@gmail.com [Andre: make more generic, let it cover multiple registers, slight rework] Signed-off-by: Andre Przywara andre.przywara@arm.com

---

Changes since v2: * Newly added patch, not there in v2/v1.

---

drivers/reset/Kconfig | 6 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-generic.c | 111 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 drivers/reset/reset-generic.c

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 75ccd65..1cdc159 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -12,6 +12,12 @@ config DM_RESET although driving such reset isgnals using GPIOs may be more appropriate in this case.

+config GENERIC_RESET

•    bool "Generic Reset controller driver"
  

•    depends on DM_RESET
  

•    help
  

•      Support Generic reset controller.
  

config SANDBOX_RESET bool "Enable the sandbox reset test driver" depends on DM_MAILBOX && SANDBOX diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 0a044d5..5e027a1 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -4,6 +4,7 @@ #

obj-$(CONFIG_DM_RESET) += reset-uclass.o +obj-$(CONFIG_GENERIC_RESET) += reset-generic.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o obj-$(CONFIG_STI_RESET) += sti-reset.o diff --git a/drivers/reset/reset-generic.c b/drivers/reset/reset-generic.c new file mode 100644 index 0000000..9c45087 --- /dev/null +++ b/drivers/reset/reset-generic.c @@ -0,0 +1,111 @@ +/*

• • Copyright (C) 2017 Amit Singh Tomar amittomer25@gmail.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <reset-uclass.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/sizes.h>

+DECLARE_GLOBAL_DATA_PTR;

+struct generic_reset_priv {

• void __iomem *membase;
• int max_reset;

+};

+#define BITS_PER_BYTE 8 +static int generic_reset_toggle(struct reset_ctl *rst, bool assert) +{

• struct generic_reset_priv *priv = dev_get_priv(rst->dev);
• int reg_width = sizeof(u32);
• int bank, offset;
• u32 reg;
• if (rst->id >= priv->max_reset)

• return -EINVAL;
  

• bank = rst->id / (reg_width * BITS_PER_BYTE);
• offset = rst->id % (reg_width * BITS_PER_BYTE);
• reg = readl(priv->membase + (bank * reg_width));
• if (assert)

• writel(reg & ~BIT(offset), priv->membase + (bank * reg_width));
  

• else

• writel(reg | BIT(offset), priv->membase + (bank * reg_width));
  

• return 0;

+}

+static int generic_reset_assert(struct reset_ctl *rst) +{

• return generic_reset_toggle(rst, true);

+}

+static int generic_reset_deassert(struct reset_ctl *rst) +{

• return generic_reset_toggle(rst, false);

+}

+static int generic_reset_free(struct reset_ctl *rst) +{

• return 0;

+}

+static int generic_reset_request(struct reset_ctl *rst) +{

• struct generic_reset_priv *priv = dev_get_priv(rst->dev);
• if (rst->id >= priv->max_reset)

• return -EINVAL;
  

• return generic_reset_assert(rst);

+}

+struct reset_ops generic_reset_reset_ops = {

• .free = generic_reset_free,
• .request = generic_reset_request,
• .rst_assert = generic_reset_assert,
• .rst_deassert = generic_reset_deassert,

+};

+static const struct udevice_id generic_reset_ids[] = {

• { .compatible = "generic-reset" },
• { .compatible = "actions,s700-reset" },
• { }

+};

+static int generic_reset_probe(struct udevice *dev) +{

• struct generic_reset_priv *priv = dev_get_priv(dev);
• fdt_addr_t addr;
• fdt_size_t size;
• addr = devfdt_get_addr_size_index(dev, 0, &size);
• if (addr == FDT_ADDR_T_NONE)

• return -EINVAL;
  

• priv->max_reset = dev_read_u32_default(dev, "num-resets", -1);
• if (priv->max_reset == -1)

• priv->max_reset = size * BITS_PER_BYTE;
  

• priv->membase = devm_ioremap(dev, addr, size);
• if (!priv->membase)

• return -EFAULT;
  

• return 0;

+}

+U_BOOT_DRIVER(generic_reset) = {

• .name = "generic_reset",
• .id = UCLASS_RESET,
• .of_match = generic_reset_ids,
• .ops = &generic_reset_reset_ops,
• .probe = generic_reset_probe,
• .priv_auto_alloc_size = sizeof(struct generic_reset_priv),

+};