The MPC8555E and MPC8548E reference manuals are quite specific about the formula required to change the value of CCSRBAR. This patch implements that formula. --- cpu/mpc85xx/cpu_init.c | 25 +++++++++++++++++++++++-- 1 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 736aef1..2f256de 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -141,10 +141,31 @@ void cpu_init_early_f(void) MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 1, BOOKE_PAGESZ_4K, 0);

+ // Update CCSRBAR using the procedure described in + // the MPC8548E Reference Manual, section 4.3.1.1.1: + // -- Read the current value of CCSRBAR using a load word + // instruction followed by an isync. + // This forces all accesses to configuration space to + // complete. temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); - out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12); - + asm volatile ("isync"); + + // -- Write the new value to CCSRBAR. + out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, + CFG_CCSRBAR_PHYS >> 12); + + // -- Perform a load of an address that does not access + // configuration space or the on-chip SRAM, + // but has an address mapping already in effect + // (for example, boot ROM). + // Follow this load with an isync. + temp = *(volatile u32 *)0xfffff000; + asm volatile ("isync"); + + // -- Read the contents of CCSRBAR from its new location, + // followed by another isync. temp = in_be32((volatile u32 *)CFG_CCSRBAR); + asm volatile ("isync"); } #endif