[U-Boot] [PATCH v4 00/14] sf: Update sf framework to support all sizes of flashes
This is a v4 patch series with some modifications on previous series with same head "sf: Update sf framework to support all sizes of flashes"
These patches removes some redundents and better coding when comapred to v3.
The current implementation in sf supports 3-byte address mode due to this up to 16MB amount of flash is able to access for those flashes which has an actual size of > 16MB.
This series of patches is more detailed/meatured changes w.r.t the current sf framework in addition to changes related to support all sizes using bank/exnt register addr accessing support.
With these new updates on sf framework, the flashes which has < 16MB are not effected as per as performance is concern and but the u-boot.bin size incrased ~460 bytes.
sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s
sf update(for first 16MBytes), Changes after: U-Boot> sf update 0x1000000 0x0 0x1000000 - N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s - W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s - S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s
The main aim of these changes is to not effect the current framework and at the same time to support the > 16Mbyte flashes, becuase of this I involved few flash vendor people in CC [thought that they may/mayn't be a mailing list members] to know their views.
REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE.
Please let me know for any issues/concerns/questions.
-- Thanks, Jagan.
Jagannadha Sutradharudu Teki (14): sf: Add bank address register writing support sf: Discover the bank addr commands sf: Read flash bank addr register at probe time sf: Update sf to support all sizes of flashes sf: Update sf read to support all sizes of flashes sf: Add bank addr code in CONFIG_SPI_FLASH_BAR sf: Use spi_flash_addr() in write call sf: stmicro: Add support for N25Q512 sf: stmicro: Add support for N25Q512A sf: stmicro: Add support for N25Q1024 sf: stmicro: Add support for N25Q1024A sf: spansion: Add support for S25FL512S_64K sf: Remove spi_flash_cmd_poll_bit() sf: Add Flag status register polling support
README | 5 + drivers/mtd/spi/spansion.c | 7 ++ drivers/mtd/spi/spi_flash.c | 191 +++++++++++++++++++++++++++++------ drivers/mtd/spi/spi_flash_internal.h | 29 +++++- drivers/mtd/spi/stmicro.c | 24 +++++ include/spi_flash.h | 8 ++ 6 files changed, 231 insertions(+), 33 deletions(-)
Hi,
Any comments on this series.
-- Thanks, Jagan.
On Fri, Jun 14, 2013 at 2:25 AM, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-teki@xilinx.com wrote:
This is a v4 patch series with some modifications on previous series with same head "sf: Update sf framework to support all sizes of flashes"
These patches removes some redundents and better coding when comapred to v3.
The current implementation in sf supports 3-byte address mode due to this up to 16MB amount of flash is able to access for those flashes which has an actual size of > 16MB.
This series of patches is more detailed/meatured changes w.r.t the current sf framework in addition to changes related to support all sizes using bank/exnt register addr accessing support.
With these new updates on sf framework, the flashes which has < 16MB are not effected as per as performance is concern and but the u-boot.bin size incrased ~460 bytes.
sf update(for first 16MBytes), Changes before: U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256 16777216 bytes written, 0 bytes skipped in 199.72s, speed 86480 B/s
- W25Q128BV 16777216 bytes written, 0 bytes skipped in 351.739s, speed 48913 B/s
- S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 65.659s, speed 262144 B/s
sf update(for first 16MBytes), Changes after: U-Boot> sf update 0x1000000 0x0 0x1000000
- N25Q256 16777216 bytes written, 0 bytes skipped in 198.953s, speed 86480 B/s
- W25Q128BV 16777216 bytes written, 0 bytes skipped in 350.90s, speed 49200 B/s
- S25FL256S_64K 16777216 bytes written, 0 bytes skipped in 66.521s, speed 262144 B/s
The main aim of these changes is to not effect the current framework and at the same time to support the > 16Mbyte flashes, becuase of this I involved few flash vendor people in CC [thought that they may/mayn't be a mailing list members] to know their views.
REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE.
Please let me know for any issues/concerns/questions.
-- Thanks, Jagan.
Jagannadha Sutradharudu Teki (14): sf: Add bank address register writing support sf: Discover the bank addr commands sf: Read flash bank addr register at probe time sf: Update sf to support all sizes of flashes sf: Update sf read to support all sizes of flashes sf: Add bank addr code in CONFIG_SPI_FLASH_BAR sf: Use spi_flash_addr() in write call sf: stmicro: Add support for N25Q512 sf: stmicro: Add support for N25Q512A sf: stmicro: Add support for N25Q1024 sf: stmicro: Add support for N25Q1024A sf: spansion: Add support for S25FL512S_64K sf: Remove spi_flash_cmd_poll_bit() sf: Add Flag status register polling support
README | 5 + drivers/mtd/spi/spansion.c | 7 ++ drivers/mtd/spi/spi_flash.c | 191 +++++++++++++++++++++++++++++------ drivers/mtd/spi/spi_flash_internal.h | 29 +++++- drivers/mtd/spi/stmicro.c | 24 +++++ include/spi_flash.h | 8 ++ 6 files changed, 231 insertions(+), 33 deletions(-)
-- 1.8.3
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participants (2)
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Jagan Teki -
Jagannadha Sutradharudu Teki