Primary Protected Application (PPA) is the base of TrustZone for Freescale Layerscape SoCs. It needs to run in secure memory while the rest of u-boot can run in non-secure memory. The secure memory is reserved at the very end of DDR, before debug server and MC reservations. The address varies depending on the total size of intalled DDR.

Signed-off-by: York Sun yorksun@freescale.com

---

Changes in v1: Initial patch. Depends on http://patchwork.ozlabs.org/patch/540248/

README | 14 ++++++++++--- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 23 +++++++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++ board/freescale/ls2085a/ls2085a.c | 17 --------------- board/freescale/ls2085aqds/ls2085aqds.c | 17 --------------- board/freescale/ls2085ardb/ls2085ardb.c | 17 --------------- include/configs/ls2085a_common.h | 4 ++-- 7 files changed, 39 insertions(+), 56 deletions(-)

diff --git a/README b/README index ef8d437..e1ca7c2 100644 --- a/README +++ b/README @@ -3881,7 +3881,7 @@ Configuration Settings: Scratch address used by the alternate memory test You only need to set this if address zero isn't writeable

-- CONFIG_SYS_MEM_TOP_HIDE (PPC only): +- CONFIG_SYS_MEM_TOP_HIDE: If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of RAM and won't get "touched" at all by U-Boot. By @@ -5048,6 +5048,10 @@ within that device. normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the virtual address in NOR flash.

+- CONFIG_SYS_MEM_TOP_HIDE_MIN + Define minimum DDR size to be hided from top of the DDR memory. + MC requires the region to be aligned with 512MB. + Freescale Layerscape Debug Server Support: ------------------------------------------- The Freescale Layerscape Debug Server Support supports the loading of @@ -5060,8 +5064,12 @@ This firmware often needs to be loaded during U-Boot booting. - CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE Define minimum DDR size required for debug server image

-- CONFIG_SYS_MEM_TOP_HIDE_MIN - Define minimum DDR size to be hided from top of the DDR memory +Freescale Layerscape Primary Protected Application (PPA) support +---------------------------------------------------------------- +Freescale PPA runs in secure DDR, reserved from DDR pool. + +- CONFIG_FSL_PPA_RESERVED_DRAM_SIZE + If defined, this is reserved in highest address as secure memory

Reproducible builds ------------------- diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 9d1c70f..690c263 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -537,3 +537,26 @@ void reset_cpu(ulong addr) val |= 0x02; scfg_out32(rstcr, val); } + +#ifndef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE +#define CONFIG_FSL_PPA_RESERVED_DRAM_SIZE 0 +#endif +#ifndef CONFIG_SYS_MEM_TOP_HIDE_MIN +#define CONFIG_SYS_MEM_TOP_HIDE_MIN 0 +#endif +unsigned long get_dram_size_to_hide(void) +{ + unsigned long dram_to_hide = CONFIG_FSL_PPA_RESERVED_DRAM_SIZE; + +/* Carve the Debug Server private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_DEBUG_SERVER + dram_to_hide += debug_server_get_dram_block_size(); +#endif + +/* Carve the MC private DRAM block from the end of DRAM */ +#ifdef CONFIG_FSL_MC_ENET + dram_to_hide += mc_get_dram_block_size(); +#endif + + return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); +} diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 87bb937..77637a9 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -17,6 +17,9 @@ #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0

+/* High memory for PPA, MC, debug server when applicable */ +#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide() + #if defined(CONFIG_LS2085A) #define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index 27481e2..6f4c3d4 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -66,23 +66,6 @@ int arch_misc_init(void) } #endif

-unsigned long get_dram_size_to_hide(void) -{ - unsigned long dram_to_hide = 0; - -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - dram_to_hide += debug_server_get_dram_block_size(); -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET - dram_to_hide += mc_get_dram_block_size(); -#endif - - return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); -} - int board_eth_init(bd_t *bis) { int error = 0; diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c index b02d6e8..8898cc3 100644 --- a/board/freescale/ls2085aqds/ls2085aqds.c +++ b/board/freescale/ls2085aqds/ls2085aqds.c @@ -251,23 +251,6 @@ int arch_misc_init(void) } #endif

-unsigned long get_dram_size_to_hide(void) -{ - unsigned long dram_to_hide = 0; - -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - dram_to_hide += debug_server_get_dram_block_size(); -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET - dram_to_hide += mc_get_dram_block_size(); -#endif - - return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); -} - #ifdef CONFIG_FSL_MC_ENET void fdt_fixup_board_enet(void *fdt) { diff --git a/board/freescale/ls2085ardb/ls2085ardb.c b/board/freescale/ls2085ardb/ls2085ardb.c index 18953b8..efddf74 100644 --- a/board/freescale/ls2085ardb/ls2085ardb.c +++ b/board/freescale/ls2085ardb/ls2085ardb.c @@ -217,23 +217,6 @@ int arch_misc_init(void) } #endif

-unsigned long get_dram_size_to_hide(void) -{ - unsigned long dram_to_hide = 0; - -/* Carve the Debug Server private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_DEBUG_SERVER - dram_to_hide += debug_server_get_dram_block_size(); -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ -#ifdef CONFIG_FSL_MC_ENET - dram_to_hide += mc_get_dram_block_size(); -#endif - - return roundup(dram_to_hide, CONFIG_SYS_MEM_TOP_HIDE_MIN); -} - #ifdef CONFIG_FSL_MC_ENET void fdt_fixup_board_enet(void *fdt) { diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 0011e72..1d0d28b 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -189,14 +189,14 @@ unsigned long long get_qixis_addr(void); /* * Carve out a DDR region which will not be used by u-boot/Linux * - * It will be used by MC and Debug Server. The MC region must be + * It will be used by PPA, MC and Debug Server. The MC region must be * 512MB aligned, so the min size to hide is 512MB. */ +#define CONFIG_FSL_PPA_RESERVED_DRAM_SIZE (2048UL * 1024) #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) #define CONFIG_SYS_MEM_TOP_HIDE_MIN (512UL * 1024 * 1024) -#define CONFIG_SYS_MEM_TOP_HIDE get_dram_size_to_hide() #endif

/* PCIe */

DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area reserved for TrustZone with size CONFIG_FSL_PPA_RESERVED_DRAM_SIZE.

Early MMU tables are changed to set DDR as non-secure. Before setting final MMU tables in secure DDR, existing MMU needs to be updated with a secure DDR entry. A new table is added into final MMU tables so secure memory can have 2MB granuality.

A new global data variable secure_ram is introduced to host the address of secure memory. "bdinfo" command shows its value.

Signed-off-by: York Sun yorksun@freescale.com

---

Changes in v1: None

arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 126 ++++++++++++++++++++++-- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 ++- arch/arm/include/asm/global_data.h | 3 + board/freescale/ls2085a/ddr.c | 10 ++ board/freescale/ls2085aqds/ddr.c | 10 ++ board/freescale/ls2085ardb/ddr.c | 10 ++ common/cmd_bdinfo.c | 4 + 7 files changed, 162 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 690c263..5ce6f8f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -207,10 +207,86 @@ static inline void early_mmu_setup(void) }

/* + * Called from early mmu setup. The phys_addr needs to be in + * the table and aligned. This function sets the block to secure. + */ +static inline int fixup_early_secure_ddr(u64 *level0_table, + phys_addr_t phys_addr) +{ + int ret = 0; +#ifdef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE + struct table_info table = {}; + struct sys_mmu_table ddr_entry = { + 0, 0, BLOCK_SIZE_L1, MT_NORMAL, PMD_SECT_OUTER_SHARE + }; + + ddr_entry.virt_addr = phys_addr; + ddr_entry.phys_addr = phys_addr; + ret = find_table(&ddr_entry, &table, level0_table); + if (!ret) + ret = set_block_entry(&ddr_entry, &table); +#endif + + return ret; +} +/* + * Called from final mmu setup. The phys_addr is new, non-existing + * address. A new sub table is created @level2_table_secure. + */ +static inline int final_secure_ddr(u64 *level0_table, + u64 *level2_table_secure, + phys_addr_t phys_addr) +{ + int ret = 0; +#ifdef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE + struct table_info table = {}; + struct sys_mmu_table ddr_entry = { + 0, 0, BLOCK_SIZE_L1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS + }; + u64 index; + + /* Need to create a new table */ + ddr_entry.virt_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1); + ddr_entry.phys_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1); + ret = find_table(&ddr_entry, &table, level0_table); + if (ret) + return ret; + index = (ddr_entry.virt_addr - table.table_base) >> SECTION_SHIFT_L1; + set_pgtable_table(table.ptr, index, level2_table_secure); + table.ptr = level2_table_secure; + table.table_base = ddr_entry.virt_addr; + table.entry_size = BLOCK_SIZE_L2; + ret = set_block_entry(&ddr_entry, &table); + if (ret) { + printf("MMU error: could not fill non-secure ddr block entries\n"); + return ret; + } + ddr_entry.virt_addr = phys_addr; + ddr_entry.phys_addr = phys_addr; + ddr_entry.size = CONFIG_FSL_PPA_RESERVED_DRAM_SIZE; + ddr_entry.attribute = PMD_SECT_OUTER_SHARE; + ret = find_table(&ddr_entry, &table, level0_table); + if (ret) { + printf("MMU error: could not find secure ddr table\n"); + return ret; + } + ret = set_block_entry(&ddr_entry, &table); + if (ret) + printf("MMU error: could not set secure ddr block entry\n"); +#endif + + return ret; +} + +/* * The final tables look similar to early tables, but different in detail. * These tables are in DRAM. Sub tables are added to enable cache for * QBMan and OCRAM. * + * Put the MMU table in secure memory if gd->arch.secure_ram is set. + * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. + * * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB. @@ -224,17 +300,35 @@ static inline void early_mmu_setup(void) static inline void final_mmu_setup(void) { unsigned int el, i; - u64 *level0_table = (u64 *)gd->arch.tlb_addr; - u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000); - u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000); - u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); -#ifdef CONFIG_FSL_LSCH3 - u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); -#elif defined(CONFIG_FSL_LSCH2) - u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); - u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000); + u64 *level0_table = gd->arch.secure_ram ? (u64 *)gd->arch.secure_ram + : (u64 *)gd->arch.tlb_addr; + u64 *level1_table0 = level0_table + 512; + u64 *level1_table1 = level1_table0 + 512; + u64 *level2_table0 = level1_table1 + 512; + u64 *level2_table1 = level2_table0 + 512; +#ifdef CONFIG_FSL_LSCH2 + u64 *level2_table2 = level2_table1 + 512; #endif + u64 *level2_table_secure; struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; + u64 secure_ram = gd->arch.secure_ram & ~(BLOCK_SIZE_L1 - 1); + + /* + * Modify the early MMU table to create a secure memory + * to host the table + */ + if (!fixup_early_secure_ddr((u64 *)CONFIG_SYS_FSL_OCRAM_BASE, + secure_ram)) { + flush_dcache_range(CONFIG_SYS_FSL_OCRAM_BASE, + CONFIG_SYS_FSL_OCRAM_BASE + 0x5000); + asm volatile( + "tlbi vae3, %0\n" + "dsb sy\n" + "isb" + : : "r" (secure_ram) : "memory"); + } else { + printf("MMU error: Failed to create early MMU secure DDR\n"); + }

/* Invalidate all table entries */ memset(level0_table, 0, PGTABLE_SIZE); @@ -269,6 +363,20 @@ static inline void final_mmu_setup(void) &final_mmu_table[i]); } } + /* Set the PPA memory to secure */ + if (gd->arch.secure_ram) { +#ifdef CONFIG_FSL_LSCH3 + level2_table_secure = level2_table1 + 512; +#elif defined(CONFIG_FSL_LSCH2) + level2_table_secure = level2_table2 + 512; +#endif + /* update tlb pointer */ + gd->arch.tlb_addr = gd->arch.secure_ram; + if (!final_secure_ddr(level0_table, + level2_table_secure, + gd->arch.secure_ram)) + gd->arch.secure_ram |= 1; /* set the valid flag */ + }

/* flush new MMU table */ flush_dcache_range(gd->arch.tlb_addr, diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index b4b85a8..a13a3d3 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -129,12 +129,14 @@ static const struct sys_mmu_table early_mmu_table[] = { { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS}, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, @@ -161,7 +163,8 @@ static const struct sys_mmu_table final_mmu_table[] = { { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, @@ -208,7 +211,8 @@ static const struct sys_mmu_table final_mmu_table[] = { CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, + CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, + PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 4e3ea55..d0c7fc4 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -49,6 +49,9 @@ struct arch_global_data { #ifdef CONFIG_FSL_LSCH3 unsigned long mem2_clk; #endif +#ifdef CONFIG_FSL_LAYERSCAPE + phys_addr_t secure_ram; /* lsb is a valid flag */ +#endif };

#include <asm-generic/global_data.h> diff --git a/board/freescale/ls2085a/ddr.c b/board/freescale/ls2085a/ddr.c index 4884fa2..b7c939b 100644 --- a/board/freescale/ls2085a/ddr.c +++ b/board/freescale/ls2085a/ddr.c @@ -180,8 +180,18 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; +#ifdef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size - + CONFIG_FSL_PPA_RESERVED_DRAM_SIZE; +#endif } else { gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - + CONFIG_FSL_PPA_RESERVED_DRAM_SIZE; +#endif }

#ifdef CONFIG_SYS_DP_DDR_BASE_PHY diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2085aqds/ddr.c index 8d71ae1..f24ef12 100644 --- a/board/freescale/ls2085aqds/ddr.c +++ b/board/freescale/ls2085aqds/ddr.c @@ -170,8 +170,18 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; +#ifdef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size - + CONFIG_FSL_PPA_RESERVED_DRAM_SIZE; +#endif } else { gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - + CONFIG_FSL_PPA_RESERVED_DRAM_SIZE; +#endif }

#ifdef CONFIG_SYS_DP_DDR_BASE_PHY diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c index 8d71ae1..f24ef12 100644 --- a/board/freescale/ls2085ardb/ddr.c +++ b/board/freescale/ls2085ardb/ddr.c @@ -170,8 +170,18 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; +#ifdef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size - + CONFIG_FSL_PPA_RESERVED_DRAM_SIZE; +#endif } else { gd->bd->bi_dram[0].size = gd->ram_size; +#ifdef CONFIG_FSL_PPA_RESERVED_DRAM_SIZE + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - + CONFIG_FSL_PPA_RESERVED_DRAM_SIZE; +#endif }

#ifdef CONFIG_SYS_DP_DDR_BASE_PHY diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index ed3b935..408d020 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -377,6 +377,10 @@ static int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, print_num("-> size", bd->bi_dram[i].size); }

+#ifdef CONFIG_FSL_LAYERSCAPE + if (gd->arch.secure_ram & 0x1) + print_num("Secure ram", gd->arch.secure_ram & ~1); +#endif #if defined(CONFIG_CMD_NET) && !defined(CONFIG_DM_ETH) print_eths(); #endif