[PATCH 1/3] armv8: Include <linux/types.h> in mmu.h
Import missing definition of type u64.
Fixes: 22932ffc03e5 ("ARMv8: Adjust MMU setup") Signed-off-by: Pierre-Clément Tosi ptosi@google.com Cc: Tom Rini trini@konsulko.com Cc: York Sun yorksun@freescale.com --- arch/arm/include/asm/armv8/mmu.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index fc97c55114..517300e566 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -104,6 +104,9 @@ #define TCR_EL3_RSVD (1 << 31 | 1 << 23)
#ifndef __ASSEMBLY__ + +#include <linux/types.h> + static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) { asm volatile("dsb sy");
Remove the ability for caller code to set MAIR through set_ttbr_tcr_mair() as that doesn't seem to be used nor necessary given that the register is typically initialized once to a compile-time constant, MEMORY_ATTRIBUTES, to be used by the hardware as a byte array to be indexed through the 3-bit attribute entry in PTEs (see MT_NORMAL and MT_DEVICE_*). As those attribute offsets are themselves CPP macros, it is very unlikely for U-Boot to start dynamically defining the value of MAIR at runtime.
For now, keep setting the register from within the function so that no functional change should be expected.
Signed-off-by: Pierre-Clément Tosi ptosi@google.com Cc: Tom Rini trini@konsulko.com Cc: Patrick Delaunay patrick.delaunay@foss.st.com Cc: Patrice Chotard patrice.chotard@foss.st.com --- arch/arm/cpu/armv8/cache_v8.c | 3 +-- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 9 +++------ arch/arm/include/asm/armv8/mmu.h | 4 +++- 3 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 3de18c7675..b91b61713e 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -415,8 +415,7 @@ __weak void mmu_setup(void) setup_all_pgtables();
el = current_el(); - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), - MEMORY_ATTRIBUTES); + set_ttbr_tcr(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL));
/* enable the mmu */ set_sctlr(get_sctlr() | CR_M); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 2ded3e4efc..5917058fa1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -451,10 +451,8 @@ static inline void early_mmu_setup(void) setup_pgtables();
/* point TTBR to the new table */ - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, - get_tcr(el, NULL, NULL) & - ~(TCR_ORGN_MASK | TCR_IRGN_MASK), - MEMORY_ATTRIBUTES); + set_ttbr_tcr(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL) + & ~(TCR_ORGN_MASK | TCR_IRGN_MASK));
set_sctlr(get_sctlr() | CR_M); } @@ -607,8 +605,7 @@ static inline void final_mmu_setup(void) invalidate_icache_all();
/* point TTBR to the new table */ - set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), - MEMORY_ATTRIBUTES); + set_ttbr_tcr(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL));
set_sctlr(get_sctlr() | CR_M); } diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 517300e566..7c17c06e98 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -107,8 +107,10 @@
#include <linux/types.h>
-static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) +static inline void set_ttbr_tcr(int el, u64 table, u64 tcr) { + const u64 attr = MEMORY_ATTRIBUTES; + asm volatile("dsb sy"); if (el == 1) { asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
As the register is initialized to a constant value, it can be set at any point before the MMU has been enabled. Instead of waiting until the very last moment to do so, initialize it during early boot, when we initialize other system registers. This ensures it is valid at any point once the C runtime is up.
Signed-off-by: Pierre-Clément Tosi ptosi@google.com Cc: Tom Rini trini@konsulko.com --- arch/arm/cpu/armv8/Kconfig | 6 ++++++ arch/arm/cpu/armv8/start.S | 12 ++++++++++++ arch/arm/include/asm/armv8/mmu.h | 5 ----- 3 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 9967376eca..efb451e9a5 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -31,6 +31,12 @@ config ARMV8_SET_SMPEN it can be safely enabled when EL2/EL3 initialized SMPEN bit or when CPU implementation doesn't include that register.
+config ARMV8_SET_MAIR + bool "Initialize the MAIR to its constant value out of boot" + default y if !SYS_DISABLE_DCACHE_OPS + help + Say Y here to set MAIR_ELx (MEMORY_ATTRIBUTES), needed by the MMU. + config ARMV8_SPIN_TABLE bool "Support spin-table enable method" depends on ARMV8_MULTIENTRY && OF_LIBFDT diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 91b00a46cc..dca58922c1 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -135,6 +135,18 @@ pie_fixup_done: msr cpacr_el1, x0 /* Enable FP/SIMD */ 0:
+#ifdef CONFIG_ARMV8_SET_MAIR + ldr x2, =(MEMORY_ATTRIBUTES) + switch_el x1, 3f, 2f, 1f + b 0f +3: msr mair_el3, x2 + b 0f +2: msr mair_el2, x2 + b 0f +1: msr mair_el1, x2 +0: +#endif + #ifdef COUNTER_FREQUENCY branch_if_not_highest_el x0, 4f ldr x0, =COUNTER_FREQUENCY diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 7c17c06e98..c9fbfcaed2 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -109,21 +109,16 @@
static inline void set_ttbr_tcr(int el, u64 table, u64 tcr) { - const u64 attr = MEMORY_ATTRIBUTES; - asm volatile("dsb sy"); if (el == 1) { asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); - asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory"); } else if (el == 2) { asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); - asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory"); } else if (el == 3) { asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); - asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory"); } else { hang(); }
On Tue, Mar 29, 2022 at 06:06:07PM +0100, Pierre-Clément Tosi wrote:
As the register is initialized to a constant value, it can be set at any point before the MMU has been enabled. Instead of waiting until the very last moment to do so, initialize it during early boot, when we initialize other system registers. This ensures it is valid at any point once the C runtime is up.
Signed-off-by: Pierre-Clément Tosi ptosi@google.com Cc: Tom Rini trini@konsulko.com
arch/arm/cpu/armv8/Kconfig | 6 ++++++ arch/arm/cpu/armv8/start.S | 12 ++++++++++++ arch/arm/include/asm/armv8/mmu.h | 5 ----- 3 files changed, 18 insertions(+), 5 deletions(-)
This makes a number of platforms such as: px30-core-ctouch2-of10-px30 px30-core-ctouch2-px30 px30-core-edimm2.2-px30 odroid-go2 evb-px30 firefly-px30 fail to build due to size increase.
participants (2)
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Pierre-Clément Tosi -
Tom Rini