[U-Boot] Booting from NAND on MX51
Hi,
I am using mx51 3stack Freescale dev board, and I would like to make it boot u-boot from NAND. Does anyone have any local changes that enable that feature?
The u-boot works when is downloaded into RAM from Jtag, but can't get it boot from NAND when I write it there. Do I have to develop nand_spl, early stage0 loader?
I have also tried to change the following setting on the standard mx51_3stack config but still cannot get it boot from NAND.
#undef CONFIG_SKIP_RELOCATE_UBOOT #define CONFIG_SYS_NAND_BOOT 1
Does anyone have u-boot booting from NAND on mx51? Any repository, or a patch that might be available?
Regards, Andreas
------------------------------------------------------------------------ -
/* * Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de * * (C) Copyright 2009 Freescale Semiconductor, Inc. * * Configuration settings for the MX51-3Stack Freescale board. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */
#ifndef __CONFIG_H #define __CONFIG_H
#include <asm/arch/mx51.h>
/* High Level Configuration Options */ #define CONFIG_ARMV7 1 /* This is armv7 Cortex-A8 CPU core */ #define CONFIG_SYS_APCS_GNU #define CONFIG_L2_OFF
#define CONFIG_MXC 1 #define CONFIG_MX51_3DS 1 /* in a mx51 */ #define CONFIG_FLASH_HEADER 1 #define CONFIG_FLASH_HEADER_OFFSET 0x400 #define CONFIG_FLASH_HEADER_BARKER 0xB1
#undef CONFIG_SKIP_RELOCATE_UBOOT #define CONFIG_SYS_NAND_BOOT 1
#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
#define CONFIG_ARCH_CPU_INIT #define CONFIG_ARCH_MMU
#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO
#define BOARD_LATE_INIT /* * Disabled for now due to build problems under Debian and a significant * increase in the final file size: 144260 vs. 109536 Bytes. */
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_REVISION_TAG 1 #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1
/* * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128
/* * Hardware drivers */ #define CONFIG_MX51_UART 1 #define CONFIG_MX51_UART1 1
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
/*********************************************************** * Command definition ***********************************************************/
#include <config_cmd_default.h>
#define CONFIG_CMD_PING #define CONFIG_CMD_DHCP /* Enable below configure when supporting nand */ #define CONFIG_CMD_NAND #define CONFIG_MXC_NAND #define CONFIG_CMD_ENV #define CMD_SAVEENV #undef CONFIG_CMD_IMLS #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_NET_RETRY_COUNT 100 #define CONFIG_NET_MULTI #define CONFIG_CMD_MMC
/* * MMC Configs */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC 1 #define CONFIG_GENERIC_MMC #define CONFIG_IMX_MMC #define CONFIG_DOS_PARTITION 1 #define CONFIG_CMD_FAT 1 #endif
/* * I2C Configs */ #define CONFIG_CMD_I2C 1 #define CONFIG_HARD_I2C 1 #define CONFIG_I2C_MXC 1 #define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0xfe
#define CONFIG_BOOTDELAY 3
#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
#define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "ethprime=smc911x\0" \ "uboot_addr=0xa0000000\0" \ "uboot=u-boot.bin\0" \ "kernel=uImage\0" \ "nfsroot=/opt/eldk/arm\0" \ "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ "bootcmd=run bootcmd_net\0" \ "bootcmd_net=run bootargs_base bootargs_nfs; " \ "tftpboot ${loadaddr} ${kernel}; bootm\0" \ "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ "protect off ${uboot_addr} 0xa003ffff; " \ "erase ${uboot_addr} 0xa003ffff; " \ "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ "setenv filesize; saveenv\0"
/*Support LAN9217*/ #define CONFIG_SMC911X 1 #define CONFIG_SMC911X_16_BIT 1 #define CONFIG_SMC911X_BASE mx51_io_base_addr
/* * The MX51 3stack board seems to have a hardware "peculiarity" confirmed under * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A * controller inverted. The controller is capable of detecting and correcting * this, but it needs 4 network packets for that. Which means, at startup, you * will not receive answers to the first 4 packest, unless there have been some * broadcasts on the network, or your board is on a hub. Reducing the ARP * timeout from default 5 seconds to 200ms we speed up the initial TFTP * transfer, should the user wish one, significantly. */ #define CONFIG_ARP_TIMEOUT 200UL
/* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "MX51 U-Boot > " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x10000
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING 1
/*---------------------------------------------------------------------- - * Stack sizes * * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
/*---------------------------------------------------------------------- - * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE_ADDR /* TO1 boards */ /* #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) */ #define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
/*---------------------------------------------------------------------- - * FLASH and environment organization */ #define CONFIG_SYS_NO_FLASH
/*---------------------------------------------------------------------- - * NAND FLASH driver setup */ #define NAND_MAX_CHIPS 8 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_NAND_FW_16BIT 0 /* 1: 16bit 0: 8bit */
/* Monitor at beginning of flash */ #define CONFIG_FSL_ENV_IN_NAND /* #define CONFIG_FSL_ENV_IN_NAND */
#define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE #if defined(CONFIG_FSL_ENV_IN_NAND) #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_OFFSET 0x100000 #elif defined(CONFIG_FSL_ENV_IN_MMC) #define CONFIG_ENV_IS_IN_MMC 1 #define CONFIG_ENV_OFFSET (768 * 1024) #else #define CONFIG_ENV_IS_NOWHERE 1 #endif /* * JFFS2 partitions */ #undef CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_DEV "nand0"
#endif /* __CONFIG_H */
Andreas Orfanos wrote:
Hi,
Hi Andreas,
I am using mx51 3stack Freescale dev board, and I would like to make it boot u-boot from NAND.
I sent patches for the mx51evk (babbage board), but NAND is not (yet) supported. This is the first MX51 board that should go into mainline. The mx51_3stack is not supported in u-boot. How do you derive your u-boot ? From my patches or from another source ?
Does anyone have any local changes that enable that feature?
The u-boot works when is downloaded into RAM from Jtag, but can't get it boot from NAND when I write it there. Do I have to develop nand_spl, early stage0 loader?
Well, I think the MX51 can boot without an early loader. The processor can boot directly from NAND, if the correct boot pins are set and no internal fuses are blown to avoid it, as stated in the user manual. The processor reads an image in the IMX format - you see documentation in doc/README.imximage. At the beginning of the image there must be a suitable for your board DCD table, that enables the IOMUX for the NAND controller and does the required setup. The image length is part of the IMX header and the processor copies automatically from NAND to the RAM address you set in the header and then jumps to the starting address.
As I said, I have not tried (the mx51evk has no NAND). However, booting from other sources (SD card, SPI Flash) works in this way.
Regards, Stefano
Hi Stefano,
Thank you for your reply. MX51 for u-boot can be found in launchpad.net Here is the link:
https://launchpad.net/ubuntu/+source/uboot-imx/
It has MX51_3stack too. You need to download the source code, including the diffs, and patch them appropriately.
I didn't know how the ROM MX51 boot loader works. Thanks for writing that README document.
I have set up the right switches on the board, and I can boot RedBoot from nand without problem. Therefore it should be easy to do it on u-boot.
I can't find that imximage on 2009-08 u-boot you mention in your document. But I found it on the latest git u-boot repository. I will check out the latest u-boot and give it a go.
Regards, Andreas
-----Original Message----- From: Stefano Babic [mailto:sbabic@denx.de] Sent: 10 February 2010 11:44 To: Andreas Orfanos Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] Booting from NAND on MX51
Andreas Orfanos wrote:
Hi,
Hi Andreas,
I am using mx51 3stack Freescale dev board, and I would like to make
it
boot u-boot from NAND.
I sent patches for the mx51evk (babbage board), but NAND is not (yet) supported. This is the first MX51 board that should go into mainline. The mx51_3stack is not supported in u-boot. How do you derive your u-boot ? From my patches or from another source ?
Does anyone have any local changes that enable that feature?
The u-boot works when is downloaded into RAM from Jtag, but can't get
it
boot from NAND when I write it there. Do I have to develop nand_spl, early stage0 loader?
Well, I think the MX51 can boot without an early loader. The processor can boot directly from NAND, if the correct boot pins are set and no internal fuses are blown to avoid it, as stated in the user manual. The processor reads an image in the IMX format - you see documentation in doc/README.imximage. At the beginning of the image there must be a suitable for your board DCD table, that enables the IOMUX for the NAND controller and does the required setup. The image length is part of the IMX header and the processor copies automatically from NAND to the RAM address you set in the header and then jumps to the starting address.
As I said, I have not tried (the mx51evk has no NAND). However, booting from other sources (SD card, SPI Flash) works in this way.
Regards, Stefano
Hi,
Le 10/02/2010 13:23, Andreas Orfanos a écrit :
I have set up the right switches on the board, and I can boot RedBoot from nand without problem. Therefore it should be easy to do it on u-boot.
we are booting u-boot from NAND on a custom iMX51 board (using mDDR and not DDR2), we started from Freescale's u-boot for 3 Stack board (it's in their BSP which can be downloaded from their website) and customized it to our hardware as we have many changes vs the reference design. We are using a customized DCD table to configure the CPU and it works fine.
Eric
Hi
Did you have to make changes in cpu/arm_cortex8/start.S file? I don't have to make any changes on DCD table anyway, as it has already produced by freescale for mx51_3stack board
Regards Andreas
-----Original Message----- From: Eric Bénard [mailto:eric@eukrea.com] Sent: 10 February 2010 13:55 To: Andreas Orfanos Cc: U-Boot user list; sbabic@denx.de Subject: Re: [U-Boot] Booting from NAND on MX51
Hi,
Le 10/02/2010 13:23, Andreas Orfanos a écrit :
I have set up the right switches on the board, and I can boot RedBoot from nand without problem. Therefore it should be easy to do it on u-boot.
we are booting u-boot from NAND on a custom iMX51 board (using mDDR and not DDR2), we started from Freescale's u-boot for 3 Stack board (it's in their BSP which can be downloaded from their website) and customized it to our hardware as we have many changes vs the reference design. We are using a customized DCD table to configure the CPU and it works fine.
Eric
Hi Andreas,
Le 10/02/2010 15:55, Andreas Orfanos a écrit :
Did you have to make changes in cpu/arm_cortex8/start.S file?
we are using u-boot-2009.01 + freescale patches. No change to start.S (except a small hack to turn on a led to check u-boot is properly loaded and run).
I don't have to make any changes on DCD table anyway, as it has already produced by freescale for mx51_3stack board
I started with the DCD of Redboot for 3Stack as the one for the 3Stack in u-boot never worked here. If you don't manage to get it running using RedBoot DCD, come back to me on next thursday where I should be able to extract some patches as I'm actually busy on an other subject.
Eric
Hi Eric,
Thank you for the information. Yes, I have found 2 DCD errors when comparing RedBood DCDs with u-boot DCDs, I fixed those error and now the MX51 ROM boot loader copies the u-boot code into RAM. Someone will need to double check those in Redboot with those in u-boot and update the u-boot code. See below the flash_header.S file that I am using.
Now the system copies code from NAND but crashes somewhere at the early stage. Are any more switches that might need to be turned "on", or "off" in the mx51_3stack config file?
Regards, Andreas
/* * Copyright 2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */
#include <config.h> #include <asm/arch/mx51.h> #include "board-mx51_3stack.h"
#ifdef CONFIG_FLASH_HEADER #ifndef CONFIG_FLASH_HEADER_OFFSET # error "Must define the offset of flash header" #endif #define MXC_DCD_ITEM(i, type, addr, val) \ dcd_node_##i: \ .word type ; \ .word addr ; \ .word val ; \
.section ".text.flasheader", "x" b _start .org CONFIG_FLASH_HEADER_OFFSET app_code_jump_v: .word _start app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER app_code_csf: .word (TEXT_BASE + 0x40000 - 0x1000) //0 dcd_ptr_ptr: .word dcd_ptr super_root_key: .word 0 dcd_ptr: .word dcd_array_start app_dest_ptr: .word TEXT_BASE dcd_array_start: magic: .word 0xB17219E9 dcd_array_size: .word dcd_data_end - dcd_array_start - 8 /* DCD */ /* DDR2 IOMUX configuration */ MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200) MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5) MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5) MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2) MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2) MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7) MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45) MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45) MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45) MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45) MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0) MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3) MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3) MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3) MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3) MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3) MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3) MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2) /* Set drive strength to MAX */ #if 0 MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6) MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6) MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6) MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6) #endif /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */ /* CAS=3, BL=4 */ MXC_DCD_ITEM(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000) MXC_DCD_ITEM(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000) MXC_DCD_ITEM(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0) MXC_DCD_ITEM(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa) MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa) /* Init DRAM on CS0 */ MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a) MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b) MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008019) /* error*/ MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018) MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018) MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019) MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00428019) /* error */ MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) /* Init DRAM on CS1 */ MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e) MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f) MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d) MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c) MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c) MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d) MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0042801d) MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000) MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000) MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0) MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000) MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY1, 0x00048000) MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY2, 0x000e8000) MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY3, 0x00ff8000) MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY4, 0x00fa8000) MXC_DCD_ITEM(57, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00ed8000)
dcd_data_end: //image_len: .word 0x80000 image_len: .word __u_boot_cmd_end - TEXT_BASE #endif
-----Original Message----- From: Eric Bénard [mailto:eric@eukrea.com] Sent: 10 February 2010 15:16 To: Andreas Orfanos Cc: U-Boot user list Subject: Re: [U-Boot] Booting from NAND on MX51
Hi Andreas,
Le 10/02/2010 15:55, Andreas Orfanos a écrit :
Did you have to make changes in cpu/arm_cortex8/start.S file?
we are using u-boot-2009.01 + freescale patches. No change to start.S (except a small hack to turn on a led to check u-boot is properly loaded and run).
I don't have to make any changes on DCD table anyway, as it has already produced by freescale for mx51_3stack board
I started with the DCD of Redboot for 3Stack as the one for the 3Stack in u-boot never worked here. If you don't manage to get it running using RedBoot DCD, come back to me on next thursday where I should be able to extract some patches as I'm actually busy on an other subject.
Eric
Hi Andreas,
Thank you for the information. Yes, I have found 2 DCD errors when comparing RedBood DCDs with u-boot DCDs, I fixed those error and now the MX51 ROM boot loader copies the u-boot code into RAM.
Would you please be so kind and point those errors out explicitely so that not every reader has to find the differences by himself? Posting a patch which does the updates would be an easy way to accompish this...
Thanks Detlev
Detlev Zundel wrote:
Would you please be so kind and point those errors out explicitely so that not every reader has to find the differences by himself? Posting a patch which does the updates would be an easy way to accompish this...
And why not to send a patch to try to get the 3stack board supported in the u-boot mainline ?
The differences reported are related to the Freescale's delivery, that is at the end a u-boot fork (2009.01 or 2009.08), not part of mainline.
Regards, Stefano
Hi,
Finally managed to boot uboot from NAND. MX51_3STACK u-boot was crashing somewhere in the beginning. There, board_init() was calling setup_core_voltages() and there a write to clock registers was making u-boot to crash. I removed that write and thing booted fine. I will make a patch with all the changes and post it here.
However, JFFS2 it seems quite slow, very slow... I have setup some mtdparts, one of them "mnt", and then make a "chpart nand.mnt". When I try a list command "ls", the whole listing is incredibly slow.
Does anyone ever seen issues NAND and Jff2 on MX51? Any u-boot version that you have seen it working?
Any advice will be very much appreciated.
Regards, Andreas
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Andreas Orfanos Sent: 11 February 2010 10:25 To: Eric Bénard Cc: U-Boot user list Subject: Re: [U-Boot] Booting from NAND on MX51
Hi Eric,
Thank you for the information. Yes, I have found 2 DCD errors when comparing RedBood DCDs with u-boot DCDs, I fixed those error and now the MX51 ROM boot loader copies the u-boot code into RAM. Someone will need to double check those in Redboot with those in u-boot and update the u-boot code. See below the flash_header.S file that I am using.
Now the system copies code from NAND but crashes somewhere at the early stage. Are any more switches that might need to be turned "on", or "off" in the mx51_3stack config file?
Regards, Andreas
/* * Copyright 2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */
#include <config.h> #include <asm/arch/mx51.h> #include "board-mx51_3stack.h"
#ifdef CONFIG_FLASH_HEADER #ifndef CONFIG_FLASH_HEADER_OFFSET # error "Must define the offset of flash header" #endif #define MXC_DCD_ITEM(i, type, addr, val) \ dcd_node_##i: \ .word type ; \ .word addr ; \ .word val ; \
.section ".text.flasheader", "x" b _start .org CONFIG_FLASH_HEADER_OFFSET app_code_jump_v: .word _start app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER app_code_csf: .word (TEXT_BASE + 0x40000 - 0x1000) //0 dcd_ptr_ptr: .word dcd_ptr super_root_key: .word 0 dcd_ptr: .word dcd_array_start app_dest_ptr: .word TEXT_BASE dcd_array_start: magic: .word 0xB17219E9 dcd_array_size: .word dcd_data_end - dcd_array_start - 8 /* DCD */ /* DDR2 IOMUX configuration */ MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200) MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5) MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5) MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2) MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2) MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7) MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45) MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45) MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45) MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45) MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0) MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3) MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3) MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3) MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3) MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3) MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3) MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2) /* Set drive strength to MAX */ #if 0 MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6) MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6) MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6) MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6) #endif /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */ /* CAS=3, BL=4 */ MXC_DCD_ITEM(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000) MXC_DCD_ITEM(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000) MXC_DCD_ITEM(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0) MXC_DCD_ITEM(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa) MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa) /* Init DRAM on CS0 */ MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a) MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b) MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008019) /* error*/ MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018) MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018) MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019) MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00428019) /* error */ MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) /* Init DRAM on CS1 */ MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e) MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f) MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d) MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c) MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c) MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d) MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0042801d) MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000) MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000) MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0) MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000) MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY1, 0x00048000) MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY2, 0x000e8000) MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY3, 0x00ff8000) MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY4, 0x00fa8000) MXC_DCD_ITEM(57, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00ed8000)
dcd_data_end: //image_len: .word 0x80000 image_len: .word __u_boot_cmd_end - TEXT_BASE #endif
-----Original Message----- From: Eric Bénard [mailto:eric@eukrea.com] Sent: 10 February 2010 15:16 To: Andreas Orfanos Cc: U-Boot user list Subject: Re: [U-Boot] Booting from NAND on MX51
Hi Andreas,
Le 10/02/2010 15:55, Andreas Orfanos a écrit :
Did you have to make changes in cpu/arm_cortex8/start.S file?
we are using u-boot-2009.01 + freescale patches. No change to start.S (except a small hack to turn on a led to check u-boot is properly loaded and run).
I don't have to make any changes on DCD table anyway, as it has already produced by freescale for mx51_3stack board
I started with the DCD of Redboot for 3Stack as the one for the 3Stack in u-boot never worked here. If you don't manage to get it running using RedBoot DCD, come back to me on next thursday where I should be able to extract some patches as I'm actually busy on an other subject.
Eric _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
I would not be surprised to see JFFS2 problems with most i.MX platforms. The nand ecc includes the spare area so you can not write a JFFS2 free marker to spare and then later write to the main area. There are patches for JFFS2 in the kernel for this. I don't know about u-boot.
John
On Mon, Feb 15, 2010 at 11:15 AM, Andreas Orfanos aorfanos@airvana.com wrote:
Hi,
Finally managed to boot uboot from NAND. MX51_3STACK u-boot was crashing somewhere in the beginning. There, board_init() was calling setup_core_voltages() and there a write to clock registers was making u-boot to crash. I removed that write and thing booted fine. I will make a patch with all the changes and post it here.
However, JFFS2 it seems quite slow, very slow... I have setup some mtdparts, one of them "mnt", and then make a "chpart nand.mnt". When I try a list command "ls", the whole listing is incredibly slow.
Does anyone ever seen issues NAND and Jff2 on MX51? Any u-boot version that you have seen it working?
Any advice will be very much appreciated.
Regards, Andreas
-----Original Message----- From: u-boot-bounces@lists.denx.de [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Andreas Orfanos Sent: 11 February 2010 10:25 To: Eric Bénard Cc: U-Boot user list Subject: Re: [U-Boot] Booting from NAND on MX51
Hi Eric,
Thank you for the information. Yes, I have found 2 DCD errors when comparing RedBood DCDs with u-boot DCDs, I fixed those error and now the MX51 ROM boot loader copies the u-boot code into RAM. Someone will need to double check those in Redboot with those in u-boot and update the u-boot code. See below the flash_header.S file that I am using.
Now the system copies code from NAND but crashes somewhere at the early stage. Are any more switches that might need to be turned "on", or "off" in the mx51_3stack config file?
Regards, Andreas
/* * Copyright 2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */
#include <config.h> #include <asm/arch/mx51.h> #include "board-mx51_3stack.h"
#ifdef CONFIG_FLASH_HEADER #ifndef CONFIG_FLASH_HEADER_OFFSET # error "Must define the offset of flash header" #endif #define MXC_DCD_ITEM(i, type, addr, val) \ dcd_node_##i: \ .word type ; \ .word addr ; \ .word val ; \
.section ".text.flasheader", "x" b _start .org CONFIG_FLASH_HEADER_OFFSET app_code_jump_v: .word _start app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER app_code_csf: .word (TEXT_BASE + 0x40000 - 0x1000) //0 dcd_ptr_ptr: .word dcd_ptr super_root_key: .word 0 dcd_ptr: .word dcd_array_start app_dest_ptr: .word TEXT_BASE dcd_array_start: magic: .word 0xB17219E9 dcd_array_size: .word dcd_data_end - dcd_array_start - 8 /* DCD */ /* DDR2 IOMUX configuration */ MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200) MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5) MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5) MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2) MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2) MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7) MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45) MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45) MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45) MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45) MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0) MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3) MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3) MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3) MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3) MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3) MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3) MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2) /* Set drive strength to MAX */ #if 0 MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6) MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6) MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6) MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6) #endif /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */ /* CAS=3, BL=4 */ MXC_DCD_ITEM(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000) MXC_DCD_ITEM(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000) MXC_DCD_ITEM(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0) MXC_DCD_ITEM(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa) MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa) /* Init DRAM on CS0 */ MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a) MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b) MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008019) /* error*/ MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018) MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018) MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019) MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00428019) /* error */ MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) /* Init DRAM on CS1 */ MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e) MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f) MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d) MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c) MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c) MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d) MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0042801d) MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000) MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000) MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0) MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000) MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY1, 0x00048000) MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY2, 0x000e8000) MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY3, 0x00ff8000) MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY4, 0x00fa8000) MXC_DCD_ITEM(57, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00ed8000)
dcd_data_end: //image_len: .word 0x80000 image_len: .word __u_boot_cmd_end - TEXT_BASE #endif
-----Original Message----- From: Eric Bénard [mailto:eric@eukrea.com] Sent: 10 February 2010 15:16 To: Andreas Orfanos Cc: U-Boot user list Subject: Re: [U-Boot] Booting from NAND on MX51
Hi Andreas,
Le 10/02/2010 15:55, Andreas Orfanos a écrit :
Did you have to make changes in cpu/arm_cortex8/start.S file?
we are using u-boot-2009.01 + freescale patches. No change to start.S (except a small hack to turn on a led to check u-boot is properly loaded and run).
I don't have to make any changes on DCD table anyway, as it has already produced by freescale for mx51_3stack board
I started with the DCD of Redboot for 3Stack as the one for the 3Stack in u-boot never worked here. If you don't manage to get it running using RedBoot DCD, come back to me on next thursday where I should be able to extract some patches as I'm actually busy on an other subject.
Eric _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi,
I would not be surprised to see JFFS2 problems with most i.MX platforms. The nand ecc includes the spare area so you can not write a JFFS2 free marker to spare and then later write to the main area. There are patches for JFFS2 in the kernel for this. I don't know about u-boot.
Also as a general remark, JFFS2 on larger devices _is_ really slow. Because of this _and_ the handling on blocks going bad on reads, we therefore suggest to our customers to use UBI + UBIFS on NAND.
Best wishes Detlev
participants (5)
-
Andreas Orfanos -
Detlev Zundel -
Eric Bénard -
John Rigby -
Stefano Babic