Re: [U-Boot] [linux-sunxi] Re: [PATCH] sunxi: Fix gmac not working reliable on the Bananapi
On Mon, Sep 29, 2014 at 2:16 PM, Karsten Merker merker@debian.org wrote:
On Mon, Sep 29, 2014 at 09:13:37AM +0300, Siarhei Siamashka wrote:
On Sun, 28 Sep 2014 20:13:21 +0200 Hans de Goede hdegoede@redhat.com wrote:
In order for the gmac nic to work reliable on the Bananapi, we need to poke these 2 undocumented bits in the gmac clk register. Since these are undocumented, this commit only sets these bits on the Bananapi for now.
I'll contact Allwinner to try and get these bits documented, once they are documented we can hopefully replace this hack with a better patch.
Could you please provide a bit more details in the commit message? What are the symptoms of the problem?
Without the patch, u-boot on the BananaPi shows massive packet loss on every network activity. The packet loss is so extreme that it is actually impossible to boot a kernel by tftp because u-boot gives up. The mainline kernel has (once booted) shown similar problems on the BananaPi.
How did you come to the idea to poke these bits?
The linux 3.4 kernel from https://github.com/LeMaker/linux-bananapi (which is a patched linux-sunxi.org 3.4 kernel) does not show this problem, so we started looking into what is different there, and the relevant change that was found was setting these particular undocumented bits.
File at issue here asking for the documentation https://github.com/allwinner-zh/documents
Does the GMAC driver in the linux kernel need a similar fix/workaround?
Not as far as I can see - once u-boot has set these two bits during system initialization, the mainline kernel works fine without any changes.
Also as mentioned in another e-mail http://lists.denx.de/pipermail/u-boot/2014-September/190096.html u-boot configures the "912MHz @1.4V" CPU clock frequency/voltage setup for sun7i hardware. And according to the information from Tony Zhang, this is supposed to be unreliable for the Banana Pi. So what happens to this GMAC bug if you just increase the dcdc2 voltage in u-boot (or reduce the CPU clock frequency)?
I can test that if you could tell me what would have to be changed in u-boot to do that.
Regards, Karsten -- Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der Werbung sowie der Markt- oder Meinungsforschung.
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Hi,
On 09/29/2014 08:35 PM, jonsmirl@gmail.com wrote:
On Mon, Sep 29, 2014 at 2:16 PM, Karsten Merker merker@debian.org wrote:
On Mon, Sep 29, 2014 at 09:13:37AM +0300, Siarhei Siamashka wrote:
How did you come to the idea to poke these bits?
The linux 3.4 kernel from https://github.com/LeMaker/linux-bananapi (which is a patched linux-sunxi.org 3.4 kernel) does not show this problem, so we started looking into what is different there, and the relevant change that was found was setting these particular undocumented bits.
File at issue here asking for the documentation https://github.com/allwinner-zh/documents
I'm already talking to Allwinner about this, it seems that bits 10-11, or more likely 10-12 of the gmac clk register are the tx equivalent of bits 5-7, "Configure GMAC receive clock delay chain". I think this is there to deal with the pcb data and clk traces not having the same length, so that this is highly board specific. I'm waiting on confirmation on this from Allwinner, as well as some info on the unit of this 0-7 value.
Regards,
Hans
On Tue, Sep 30, 2014 at 8:02 AM, Hans de Goede hdegoede@redhat.com wrote:
Hi,
On 09/29/2014 08:35 PM, jonsmirl@gmail.com wrote:
On Mon, Sep 29, 2014 at 2:16 PM, Karsten Merker merker@debian.org wrote:
On Mon, Sep 29, 2014 at 09:13:37AM +0300, Siarhei Siamashka wrote:
How did you come to the idea to poke these bits?
The linux 3.4 kernel from https://github.com/LeMaker/linux-bananapi (which is a patched linux-sunxi.org 3.4 kernel) does not show this problem, so we started looking into what is different there, and the relevant change that was found was setting these particular undocumented bits.
File at issue here asking for the documentation https://github.com/allwinner-zh/documents
I'm already talking to Allwinner about this, it seems that bits 10-11, or more likely 10-12 of the gmac clk register are the tx equivalent of bits 5-7, "Configure GMAC receive clock delay chain". I think this is there to deal with the pcb data and clk traces not having the same length, so that this is highly board specific. I'm waiting on confirmation on this from Allwinner, as well as some info on the unit of this 0-7 value.
Encourage them to update the manual and push a new copy to git hub immediately. Too much info like this is getting buried in mail archives. Electronic publishing is free - update as often as you want.
The more they fix stuff like this in the manual, the fewer questions they will need to deal with in person. When it goes into the manual it won't get lost.
Regards,
Hans
Op 30 sep. 2014, om 14:02 heeft Hans de Goede hdegoede@redhat.com het volgende geschreven:
Hi,
On 09/29/2014 08:35 PM, jonsmirl@gmail.com wrote:
On Mon, Sep 29, 2014 at 2:16 PM, Karsten Merker merker@debian.org wrote:
On Mon, Sep 29, 2014 at 09:13:37AM +0300, Siarhei Siamashka wrote:
How did you come to the idea to poke these bits?
The linux 3.4 kernel from https://github.com/LeMaker/linux-bananapi (which is a patched linux-sunxi.org 3.4 kernel) does not show this problem, so we started looking into what is different there, and the relevant change that was found was setting these particular undocumented bits.
File at issue here asking for the documentation https://github.com/allwinner-zh/documents
I'm already talking to Allwinner about this, it seems that bits 10-11, or more likely 10-12 of the gmac clk register are the tx equivalent of bits 5-7, "Configure GMAC receive clock delay chain". I think this is there to deal with the pcb data and clk traces not having the same length, so that this is highly board specific. I'm waiting on confirmation on this from Allwinner, as well as some info on the unit of this 0-7 value.
Gbit ethernet requires a delay between the lines, which you can implement by adding 10cm or so extra trace on the PCB or tell the MAC or PHY to do it in software. Very board specific, but so far I've only seen Intel reference designs use the extra trace length method most arm/ppc/mips gbit boards use a PHY that handles it in hardware on request like the GMAC is doing above.
regards,
Koen
participants (3)
-
Hans de Goede -
jonsmirl＠gmail.com -
Koen Kooi