The two Makefiles arch/arm/mach-uniphier/{ph1-ld4,ph1-sld8}/Makefile are completely the same. We can improve the maintainability by having one to include the other.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/ph1-sld8/Makefile | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-)

diff --git a/arch/arm/mach-uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile index 5ce3d8a..8eb575e 100644 --- a/arch/arm/mach-uniphier/ph1-sld8/Makefile +++ b/arch/arm/mach-uniphier/ph1-sld8/Makefile @@ -1,16 +1 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o -obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o -obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o -obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o -else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o -endif - -obj-y += boot-mode.o +include $(src)/../ph1-ld4/Makefile

The UniPhier platform is going to enable Driver Model and UART support on SPL. Move UART pin settings to early_pin_init(), which is called from SPL.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/ph1-ld4/Makefile | 2 +- arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c | 27 +++++++++++++++++++++++++ arch/arm/mach-uniphier/ph1-ld4/pinctrl.c | 18 ++--------------- arch/arm/mach-uniphier/ph1-pro4/Makefile | 2 +- arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c | 27 +++++++++++++++++++++++++ arch/arm/mach-uniphier/ph1-pro4/pinctrl.c | 15 ++------------ arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c | 27 +++++++++++++++++++++++++ arch/arm/mach-uniphier/ph1-sld8/pinctrl.c | 18 ++--------------- arch/arm/mach-uniphier/spl.c | 9 +++++++-- 9 files changed, 96 insertions(+), 49 deletions(-) create mode 100644 arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c create mode 100644 arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c create mode 100644 arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c

diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile index fa36419..af815c3 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/Makefile +++ b/arch/arm/mach-uniphier/ph1-ld4/Makefile @@ -5,7 +5,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o + early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o obj-$(CONFIG_SPL_DM) += platdevice.o diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c new file mode 100644 index 0000000..e5e86bb --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ + sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ + + sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ + sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ + + sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ + sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c index 15d81eb..3074d0a 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */

-#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h>

@@ -14,20 +14,6 @@ void pin_init(void)

/* Comment format: PAD Name -> Function Name */

-#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */ - sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */ - - sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */ - sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */ - - sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */ - sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */ - - sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ - sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ -#endif - #ifdef CONFIG_NAND_DENALI sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */ sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */ diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile index ac27d9b..f6a584e 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/Makefile +++ b/arch/arm/mach-uniphier/ph1-pro4/Makefile @@ -5,7 +5,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o obj-y += sg_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o + early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o obj-$(CONFIG_SPL_DM) += platdevice.o diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c new file mode 100644 index 0000000..85bb6a0 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ + sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ + sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ + sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ + sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ + sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ + sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ +#endif + + writel(1, SG_LOADPINCTRL); +} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c index f382ef4..4df9098 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */

-#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h>

@@ -12,17 +12,6 @@ void pin_init(void) { /* Comment format: PAD Name -> Function Name */

-#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */ - sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */ - sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */ - sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */ - sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */ - sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */ - sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */ - sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */ -#endif - #ifdef CONFIG_NAND_DENALI sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */ sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */ diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c new file mode 100644 index 0000000..28cc429 --- /dev/null +++ b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <mach/sg-regs.h> + +void early_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ + sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ + + sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ + sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ + + sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ + sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ + + sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ + sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ +#endif +} diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c index 4c494ff..57a8093 100644 --- a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c +++ b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */

-#include <common.h> #include <asm/io.h> #include <mach/sg-regs.h>

@@ -12,20 +12,6 @@ void pin_init(void) { /* Comment format: PAD Name -> Function Name */

-#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */ - sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */ - - sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */ - sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */ - - sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */ - sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */ - - sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */ - sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */ -#endif - #ifdef CONFIG_SYS_I2C_UNIPHIER { u32 tmp; diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c index c3d90d0..a0d0f04 100644 --- a/arch/arm/mach-uniphier/spl.c +++ b/arch/arm/mach-uniphier/spl.c @@ -20,6 +20,7 @@ void pll_init(void); void pin_init(void); void memconf_init(void); void early_clkrst_init(void); +void early_pin_init(void); int umc_init(void); void enable_dpll_ssc(void);

@@ -47,6 +48,10 @@ void spl_board_init(void)

led_write(L, 2, , );

+ early_pin_init(); + + led_write(L, 3, , ); + { int res;

@@ -56,9 +61,9 @@ void spl_board_init(void) ; } } - led_write(L, 3, , ); + led_write(L, 4, , );

enable_dpll_ssc();

- led_write(L, 4, , ); + led_write(L, 5, , ); }

Enable CONFIG_SPL_DM and CONFIG_SPL_SERIAL_SUPPORT, which provide Driver Model UART support on SPL.

CONFIG_SYS_SPL_MALLOC_{START,SIZE} should be dropped because simple malloc is preferred on SPL. Dlmalloc requires some static variables on .data section that is not available yet for NOR boot mode etc.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/spl.c | 13 ++++++++++--- configs/ph1_ld4_defconfig | 1 + configs/ph1_pro4_defconfig | 1 + configs/ph1_sld8_defconfig | 1 + include/configs/uniphier.h | 4 +--- 5 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c index a0d0f04..a34d3a1 100644 --- a/arch/arm/mach-uniphier/spl.c +++ b/arch/arm/mach-uniphier/spl.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2013-2015 Panasonic Corporation - * Author: Masahiro Yamada yamada.m@jp.panasonic.com + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada yamada.masahiro@socionext.com * * SPDX-License-Identifier: GPL-2.0+ */ @@ -52,6 +53,12 @@ void spl_board_init(void)

led_write(L, 3, , );

+#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_write(L, 4, , ); + { int res;

@@ -61,9 +68,9 @@ void spl_board_init(void) ; } } - led_write(L, 4, , ); + led_write(L, 5, , );

enable_dpll_ssc();

- led_write(L, 5, , ); + led_write(L, 6, , ); } diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 292f2ca..aa1805b 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_DM=y CONFIG_DM_SERIAL=y +CONFIG_SPL_DM=y CONFIG_DM_I2C=y CONFIG_MACH_PH1_LD4=y CONFIG_PFC_MICRO_SUPPORT_CARD=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 2021862..194f7a5 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_DM=y CONFIG_DM_SERIAL=y +CONFIG_SPL_DM=y CONFIG_DM_I2C=y CONFIG_MACH_PH1_PRO4=y CONFIG_PFC_MICRO_SUPPORT_CARD=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index cf229ae..e7e7fff 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_DM=y CONFIG_DM_SERIAL=y +CONFIG_SPL_DM=y CONFIG_DM_I2C=y CONFIG_MACH_PH1_SLD8=y CONFIG_PFC_MICRO_SUPPORT_CARD=y diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 58608ca..c27010a 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -280,9 +280,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #endif

-#define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000) -#define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000) - #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000) #else @@ -292,6 +289,7 @@ #define CONFIG_PANIC_HANG

#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NAND_SUPPORT

#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */

The Boot ROM of UniPhier platform only loads 64KB image. We should always make sure that SPL memory footprint is less than that.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

include/configs/uniphier.h | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index db1e08f..d2d88dd 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -296,4 +296,6 @@

#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x10000

+#define CONFIG_SPL_MAX_FOOTPRINT 0x10000 + #endif /* __CONFIG_UNIPHIER_COMMON_H__ */

To remove the ifdef conditional of CONFIG_SKIP_LOWLEVEL_INIT, add late_lowlevel_init.S to U-Boot proper.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/Makefile | 1 + arch/arm/mach-uniphier/late_lowlevel_init.S | 12 ++++++++++++ include/configs/uniphier.h | 4 ---- 3 files changed, 13 insertions(+), 4 deletions(-) create mode 100644 arch/arm/mach-uniphier/late_lowlevel_init.S

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index e7a801b..f191aa3 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -12,6 +12,7 @@ obj-y += ddrphy_training.o

else

+obj-y += late_lowlevel_init.o obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S new file mode 100644 index 0000000..22be2a2 --- /dev/null +++ b/arch/arm/mach-uniphier/late_lowlevel_init.S @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +ENTRY(lowlevel_init) + mov pc, lr +ENDPROC(lowlevel_init) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index ba89a42..d4688c5 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -276,10 +276,6 @@ #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif

-#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - #define CONFIG_SPL_STACK (0x0ff08000) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)

Currently, the secondary CPU(s) are kicked three times: Boot ROM ---(kick)--> SPL ---(kick)--> U-boot ---(kick)--> Linux. It makes the boot sequence very complicated.

This commit merges the first and the second kicks, so the secondary CPU(s) can directly jump from SPL to Linux. arch/arm/mach-uniphier/smp.S is no longer necessary.

Linux boot test passed.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/Makefile | 1 - arch/arm/mach-uniphier/cache_uniphier.c | 13 ++------ arch/arm/mach-uniphier/lowlevel_init.S | 42 +++++++++++++++++++++---- arch/arm/mach-uniphier/smp.S | 54 --------------------------------- 4 files changed, 38 insertions(+), 72 deletions(-) delete mode 100644 arch/arm/mach-uniphier/smp.S

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index f191aa3..24591d6 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-y += reset.o obj-y += cache_uniphier.o -obj-$(CONFIG_UNIPHIER_SMP) += smp.o obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o

diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index 52f3c7c..4bf01bc 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada yamada.m@jp.panasonic.com + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada yamada.masahiro@socionext.com * * SPDX-License-Identifier: GPL-2.0+ */ @@ -119,20 +120,10 @@ void v7_outer_cache_disable(void) writel(tmp, SSCC); }

-void wakeup_secondary(void); - void enable_caches(void) { uint32_t reg;

-#ifdef CONFIG_UNIPHIER_SMP - /* - * The secondary CPU must move to DDR, - * before L2 disable. - * On SPL, the Page Table is located on the L2. - */ - wakeup_secondary(); -#endif /* * UniPhier SoCs must use L2 cache for init stack pointer. * We disable L2 and L1 in this order. diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S index 4a23ea4..825b160 100644 --- a/arch/arm/mach-uniphier/lowlevel_init.S +++ b/arch/arm/mach-uniphier/lowlevel_init.S @@ -48,6 +48,25 @@ ENTRY(lowlevel_init) bl enable_mmu

#ifdef CONFIG_UNIPHIER_SMP +secondary_startup: + /* + * Entry point for secondary CPUs + * + * The Boot ROM has already enabled MMU for the secondary CPUs as well + * as for the primary one. The MMU table embedded in the Boot ROM + * prohibits the DRAM access, so it is impossible to bring the + * secondary CPUs into DRAM directly. They must jump here into SPL, + * which is run on L2 cache. + * + * Boot Sequence + * [primary CPU] [secondary CPUs] + * start from Boot ROM start from Boot ROM + * jump to SPL sleep in Boot ROM + * kick secondaries ---(sev)---> jump to SPL + * jump to U-Boot main sleep in SPL + * jump to Linux + * kick secondaries ---(sev)---> jump to Linux + */ /* * ACTLR (Auxiliary Control Register) for Cortex-A9 * bit[9] Parity on @@ -68,17 +87,28 @@ ENTRY(lowlevel_init) and r0, r0, #0x3 cmp r0, #0x0 beq primary_cpu - ldr r1, =ROM_BOOT_ROMRSV2 + /* only for secondary CPUs */ + ldr r1, =ROM_BOOT_ROMRSV2 @ The last data access to L2 cache + mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) + orr r0, r0, #CR_I @ Enable ICache + bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache must be disabled + mcr p15, 0, r0, c1, c0, 0 @ before jumping to Linux mov r0, #0 str r0, [r1] -0: wfe - ldr r0, [r1] + b 1f + /* + * L2 cache is shared among all the CPUs and it might be disabled by + * the primary one. Before that, the following 5 lines must be cached + * on the Icaches of the secondary CPUs. + */ +0: wfe @ kicked by Linux +1: ldr r0, [r1] cmp r0, #0 - beq 0b - bx r0 @ r0: entry point of U-Boot main for the secondary CPU + bxne r0 @ r0: Linux entry for secondary CPUs + b 0b primary_cpu: ldr r1, =ROM_BOOT_ROMRSV2 - ldr r0, =_start @ entry for the secondary CPU + ldr r0, =secondary_startup str r0, [r1] ldr r0, [r1] @ make sure str is complete before sev sev @ kick the secondary CPU diff --git a/arch/arm/mach-uniphier/smp.S b/arch/arm/mach-uniphier/smp.S deleted file mode 100644 index 18e3a9d..0000000 --- a/arch/arm/mach-uniphier/smp.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (C) 2013 Panasonic Corporation - * Author: Masahiro Yamada yamada.m@jp.panasonic.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <linux/linkage.h> -#include <asm/system.h> -#include <mach/led.h> -#include <mach/sbc-regs.h> - -/* Entry point of U-Boot main program for the secondary CPU */ -LENTRY(secondary_entry) - mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) - bic r0, r0, #(CR_C | CR_M) @ MMU and Dcache disable - mcr p15, 0, r0, c1, c0, 0 - mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs - mcr p15, 0, r0, c7, c5, 0 @ invalidate icache - dsb - led_write(C,0,,) - ldr r1, =ROM_BOOT_ROMRSV2 - mov r0, #0 - str r0, [r1] -0: wfe - ldr r4, [r1] @ r4: entry point for secondary CPUs - cmp r4, #0 - beq 0b - led_write(C, P, U, 1) - bx r4 @ secondary CPUs jump to linux -ENDPROC(secondary_entry) - -ENTRY(wakeup_secondary) - ldr r1, =ROM_BOOT_ROMRSV2 -0: ldr r0, [r1] - cmp r0, #0 - bne 0b - - /* set entry address and send event to the secondary CPU */ - ldr r0, =secondary_entry - str r0, [r1] - ldr r0, [r1] @ make sure store is complete - mov r0, #0x100 -0: subs r0, r0, #1 @ I don't know the reason, but without this wait - bne 0b @ fails to wake up the secondary CPU - sev - - /* wait until the secondary CPU reach to secondary_entry */ -0: ldr r0, [r1] - cmp r0, #0 - bne 0b - bx lr -ENDPROC(wakeup_secondary)

The callee (arch/arm/lib/cache-cp15.c) has a #ifdef CONFIG_SYS_DCACHE_OFF conditional. The same conditional in the caller (arch/arm/mach-uniphier/cache_uniphier.c) is redundant.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/cache_uniphier.c | 2 -- 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index c1e9164..d8b8228 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -122,7 +122,5 @@ void v7_outer_cache_disable(void)

void enable_caches(void) { -#ifndef CONFIG_SYS_DCACHE_OFF dcache_enable(); -#endif }