[U-Boot] [PATCH V4 0/2] Support for HTKW mcx board
Hi All,
these patches introduce support for HTKW mcx board (AM3517-based) including OMAP3 EHCI support.
Regards, Ilya.
Ilya Yanok (2): ehci-omap: driver for EHCI host on OMAP3 mcx: support for HTKW mcx board
MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 ++++ board/htkw/mcx/mcx.c | 91 +++++++++ board/htkw/mcx/mcx.h | 408 ++++++++++++++++++++++++++++++++++++++++ board/ti/beagle/beagle.c | 101 ---------- boards.cfg | 1 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-omap.c | 156 +++++++++++++++ include/configs/mcx.h | 371 ++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 3 + 10 files changed, 1073 insertions(+), 101 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 drivers/usb/host/ehci-omap.c create mode 100644 include/configs/mcx.h
Taken from Beagle code. Tested on mcx board (AM3517-based).
Signed-off-by: Ilya Yanok yanok@emcraft.com --- Changes from V3: - None Changes from V2: - None Changes from V1: - CONFIG_OMAP_EHCI_PHYx_RESET changed to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO - phy reset moved to separate function - Calls to gpio_set_value after gpio_direction_output removed
board/ti/beagle/beagle.c | 101 -------------------------- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-omap.c | 156 ++++++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 3 + 4 files changed, 160 insertions(+), 101 deletions(-) create mode 100644 drivers/usb/host/ehci-omap.c
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6a457cb..3d63028 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -42,15 +42,6 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> -#ifdef CONFIG_USB_EHCI -#include <usb.h> -#include <asm/arch/clocks.h> -#include <asm/arch/clocks_omap3.h> -#include <asm/arch/ehci_omap3.h> -/* from drivers/usb/host/ehci-core.h */ -extern struct ehci_hccr *hccr; -extern volatile struct ehci_hcor *hcor; -#endif #include "beagle.h" #include <command.h>
@@ -441,104 +432,12 @@ int board_mmc_init(bd_t *bis) #endif
#ifdef CONFIG_USB_EHCI - -#define GPIO_PHY_RESET 147 - -/* Reset is needed otherwise the kernel-driver will throw an error. */ -int ehci_hcd_stop(void) -{ - pr_debug("Resetting OMAP3 EHCI\n"); - gpio_set_value(GPIO_PHY_RESET, 0); - writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG); - /* disable USB clocks */ - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - sr32(&prcm_base->iclken_usbhost, 0, 1, 0); - sr32(&prcm_base->fclken_usbhost, 0, 2, 0); - sr32(&prcm_base->iclken3_core, 2, 1, 0); - sr32(&prcm_base->fclken3_core, 2, 1, 0); - return 0; -} - /* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) { if(val == 15) usb_stop(); } - -/* - * Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard. - * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37. - * See there for additional Copyrights. - */ -int ehci_hcd_init(void) -{ - pr_debug("Initializing OMAP3 ECHI\n"); - - /* Put the PHY in RESET */ - gpio_request(GPIO_PHY_RESET, ""); - gpio_direction_output(GPIO_PHY_RESET, 0); - gpio_set_value(GPIO_PHY_RESET, 0); - - /* Hold the PHY in RESET for enough time till DIR is high */ - /* Refer: ISSUE1 */ - udelay(10); - - struct prcm *prcm_base = (struct prcm *)PRCM_BASE; - /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */ - sr32(&prcm_base->iclken_usbhost, 0, 1, 1); - /* - * Enable USBHOST_48M_FCLK (USBHOST_FCLK1) - * and USBHOST_120M_FCLK (USBHOST_FCLK2) - */ - sr32(&prcm_base->fclken_usbhost, 0, 2, 3); - /* Enable USBTTL_ICLK */ - sr32(&prcm_base->iclken3_core, 2, 1, 1); - /* Enable USBTTL_FCLK */ - sr32(&prcm_base->fclken3_core, 2, 1, 1); - pr_debug("USB clocks enabled\n"); - - /* perform TLL soft reset, and wait until reset is complete */ - writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, - OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG); - /* Wait for TLL reset to complete */ - while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS) - & OMAP_USBTLL_SYSSTATUS_RESETDONE)); - pr_debug("TLL reset done\n"); - - writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | - OMAP_USBTLL_SYSCONFIG_SIDLEMODE | - OMAP_USBTLL_SYSCONFIG_CACTIVITY, - OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG); - - /* Put UHH in NoIdle/NoStandby mode */ - writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP - | OMAP_UHH_SYSCONFIG_SIDLEMODE - | OMAP_UHH_SYSCONFIG_CACTIVITY - | OMAP_UHH_SYSCONFIG_MIDLEMODE, - OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG); - - /* setup burst configurations */ - writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN - | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN - | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN, - OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG); - - /* - * Refer ISSUE1: - * Hold the PHY in RESET for enough time till - * PHY is settled and ready - */ - udelay(10); - gpio_set_value(GPIO_PHY_RESET, 1); - - hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE); - hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10); - - pr_debug("OMAP3 EHCI init done\n"); - return 0; -} - #endif /* CONFIG_USB_EHCI */
#ifndef CONFIG_SPL_BUILD diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 77e217f..975c3e5 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -43,6 +43,7 @@ endif COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o +COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c new file mode 100644 index 0000000..93d3bb7 --- /dev/null +++ b/drivers/usb/host/ehci-omap.c @@ -0,0 +1,156 @@ +/* + * (C) Copyright 2011 Ilya Yanok, Emcraft Systems + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * Derived from Beagle Board code by + * Sunil Kumar sunilsaini05@gmail.com + * Shashi Ranjan shashiranjanmca05@gmail.com + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include <common.h> +#include <usb.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clocks.h> +#include <asm/arch/clocks_omap3.h> +#include <asm/arch/ehci_omap3.h> +#include <asm/arch/sys_proto.h> +#include "ehci-core.h" + +inline int __board_usb_init(void) +{ + return 0; +} +int board_usb_init(void) __attribute__((weak, alias("__board_usb_init"))); + +#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \ + defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) +/* controls PHY(s) reset signal(s) */ +static inline void omap_ehci_phy_reset(int on, int delay) +{ + /* + * Refer ISSUE1: + * Hold the PHY in RESET for enough time till + * PHY is settled and ready + */ + if (delay && !on) + udelay(delay); +#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO + gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset"); + gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on); +#endif +#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO + gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset"); + gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on); +#endif + + /* Hold the PHY in RESET for enough time till DIR is high */ + /* Refer: ISSUE1 */ + if (delay && on) + udelay(delay); +} +#else +#define omap_ehci_phy_reset(on, delay) do {} while (0) +#endif + +/* Reset is needed otherwise the kernel-driver will throw an error. */ +int ehci_hcd_stop(void) +{ + debug("Resetting OMAP3 EHCI\n"); + omap_ehci_phy_reset(1, 0); + writel(OMAP_UHH_SYSCONFIG_SOFTRESET, + OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG); + /* disable USB clocks */ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + sr32(&prcm_base->iclken_usbhost, 0, 1, 0); + sr32(&prcm_base->fclken_usbhost, 0, 2, 0); + sr32(&prcm_base->iclken3_core, 2, 1, 0); + sr32(&prcm_base->fclken3_core, 2, 1, 0); + return 0; +} + +/* + * Initialize the OMAP3 EHCI controller and PHY. + * Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37. + * See there for additional Copyrights. + */ +int ehci_hcd_init(void) +{ + int ret; + + debug("Initializing OMAP3 EHCI\n"); + + ret = board_usb_init(); + if (ret < 0) + return ret; + + /* Put the PHY in RESET */ + omap_ehci_phy_reset(1, 10); + + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */ + sr32(&prcm_base->iclken_usbhost, 0, 1, 1); + /* + * Enable USBHOST_48M_FCLK (USBHOST_FCLK1) + * and USBHOST_120M_FCLK (USBHOST_FCLK2) + */ + sr32(&prcm_base->fclken_usbhost, 0, 2, 3); + /* Enable USBTTL_ICLK */ + sr32(&prcm_base->iclken3_core, 2, 1, 1); + /* Enable USBTTL_FCLK */ + sr32(&prcm_base->fclken3_core, 2, 1, 1); + debug("USB clocks enabled\n"); + + /* perform TLL soft reset, and wait until reset is complete */ + writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, + OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG); + /* Wait for TLL reset to complete */ + while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS) + & OMAP_USBTLL_SYSSTATUS_RESETDONE)) + ; + debug("TLL reset done\n"); + + writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | + OMAP_USBTLL_SYSCONFIG_SIDLEMODE | + OMAP_USBTLL_SYSCONFIG_CACTIVITY, + OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG); + + /* Put UHH in NoIdle/NoStandby mode */ + writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP + | OMAP_UHH_SYSCONFIG_SIDLEMODE + | OMAP_UHH_SYSCONFIG_CACTIVITY + | OMAP_UHH_SYSCONFIG_MIDLEMODE, + OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG); + + /* setup burst configurations */ + writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN + | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN + | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN, + OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG); + + omap_ehci_phy_reset(0, 10); + + hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE); + hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10); + + debug("OMAP3 EHCI init done\n"); + return 0; +} diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 91af8a0..b4d6443 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -129,6 +129,9 @@ /* USB EHCI */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX
Hi Remy,
could you please review this patch? It's waiting for your approval.
Regards, Ilya.
On 13.12.2011 03:15, Ilya Yanok wrote:
Taken from Beagle code. Tested on mcx board (AM3517-based).
Signed-off-by: Ilya Yanok yanok@emcraft.com
Changes from V3:
- None
Changes from V2:
- None
Changes from V1:
- CONFIG_OMAP_EHCI_PHYx_RESET changed to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO
- phy reset moved to separate function
- Calls to gpio_set_value after gpio_direction_output removed
board/ti/beagle/beagle.c | 101 -------------------------- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-omap.c | 156 ++++++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 3 + 4 files changed, 160 insertions(+), 101 deletions(-) create mode 100644 drivers/usb/host/ehci-omap.c
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6a457cb..3d63028 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -42,15 +42,6 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> -#ifdef CONFIG_USB_EHCI -#include <usb.h> -#include <asm/arch/clocks.h> -#include <asm/arch/clocks_omap3.h> -#include <asm/arch/ehci_omap3.h> -/* from drivers/usb/host/ehci-core.h */ -extern struct ehci_hccr *hccr; -extern volatile struct ehci_hcor *hcor; -#endif #include "beagle.h" #include <command.h>
@@ -441,104 +432,12 @@ int board_mmc_init(bd_t *bis) #endif
#ifdef CONFIG_USB_EHCI
-#define GPIO_PHY_RESET 147
-/* Reset is needed otherwise the kernel-driver will throw an error. */ -int ehci_hcd_stop(void) -{
- pr_debug("Resetting OMAP3 EHCI\n");
- gpio_set_value(GPIO_PHY_RESET, 0);
- writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
- /* disable USB clocks */
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- sr32(&prcm_base->iclken_usbhost, 0, 1, 0);
- sr32(&prcm_base->fclken_usbhost, 0, 2, 0);
- sr32(&prcm_base->iclken3_core, 2, 1, 0);
- sr32(&prcm_base->fclken3_core, 2, 1, 0);
- return 0;
-}
/* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) { if(val == 15) usb_stop(); }
-/*
- Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard.
- Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
- See there for additional Copyrights.
- */
-int ehci_hcd_init(void) -{
- pr_debug("Initializing OMAP3 ECHI\n");
- /* Put the PHY in RESET */
- gpio_request(GPIO_PHY_RESET, "");
- gpio_direction_output(GPIO_PHY_RESET, 0);
- gpio_set_value(GPIO_PHY_RESET, 0);
- /* Hold the PHY in RESET for enough time till DIR is high */
- /* Refer: ISSUE1 */
- udelay(10);
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
- sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
- /*
* Enable USBHOST_48M_FCLK (USBHOST_FCLK1)* and USBHOST_120M_FCLK (USBHOST_FCLK2)*/- sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
- /* Enable USBTTL_ICLK */
- sr32(&prcm_base->iclken3_core, 2, 1, 1);
- /* Enable USBTTL_FCLK */
- sr32(&prcm_base->fclken3_core, 2, 1, 1);
- pr_debug("USB clocks enabled\n");
- /* perform TLL soft reset, and wait until reset is complete */
- writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);- /* Wait for TLL reset to complete */
- while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
& OMAP_USBTLL_SYSSTATUS_RESETDONE));- pr_debug("TLL reset done\n");
- writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
OMAP_USBTLL_SYSCONFIG_SIDLEMODE |OMAP_USBTLL_SYSCONFIG_CACTIVITY,OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);- /* Put UHH in NoIdle/NoStandby mode */
- writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP
| OMAP_UHH_SYSCONFIG_SIDLEMODE| OMAP_UHH_SYSCONFIG_CACTIVITY| OMAP_UHH_SYSCONFIG_MIDLEMODE,OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);- /* setup burst configurations */
- writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);- /*
* Refer ISSUE1:* Hold the PHY in RESET for enough time till* PHY is settled and ready*/- udelay(10);
- gpio_set_value(GPIO_PHY_RESET, 1);
- hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
- hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
- pr_debug("OMAP3 EHCI init done\n");
- return 0;
-}
#endif /* CONFIG_USB_EHCI */
#ifndef CONFIG_SPL_BUILD diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 77e217f..975c3e5 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -43,6 +43,7 @@ endif COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o +COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c new file mode 100644 index 0000000..93d3bb7 --- /dev/null +++ b/drivers/usb/host/ehci-omap.c @@ -0,0 +1,156 @@ +/*
- (C) Copyright 2011 Ilya Yanok, Emcraft Systems
- (C) Copyright 2004-2008
- Texas Instruments, <www.ti.com>
- Derived from Beagle Board code by
- Sunil Kumar sunilsaini05@gmail.com
- Shashi Ranjan shashiranjanmca05@gmail.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#include <common.h> +#include <usb.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clocks.h> +#include <asm/arch/clocks_omap3.h> +#include <asm/arch/ehci_omap3.h> +#include <asm/arch/sys_proto.h> +#include "ehci-core.h"
+inline int __board_usb_init(void) +{
- return 0;
+} +int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
+#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
- defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
+/* controls PHY(s) reset signal(s) */ +static inline void omap_ehci_phy_reset(int on, int delay) +{
- /*
* Refer ISSUE1:* Hold the PHY in RESET for enough time till* PHY is settled and ready*/- if (delay && !on)
udelay(delay);+#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
- gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
+#endif +#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
- gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
+#endif
- /* Hold the PHY in RESET for enough time till DIR is high */
- /* Refer: ISSUE1 */
- if (delay && on)
udelay(delay);+} +#else +#define omap_ehci_phy_reset(on, delay) do {} while (0) +#endif
+/* Reset is needed otherwise the kernel-driver will throw an error. */ +int ehci_hcd_stop(void) +{
- debug("Resetting OMAP3 EHCI\n");
- omap_ehci_phy_reset(1, 0);
- writel(OMAP_UHH_SYSCONFIG_SOFTRESET,
OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);- /* disable USB clocks */
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- sr32(&prcm_base->iclken_usbhost, 0, 1, 0);
- sr32(&prcm_base->fclken_usbhost, 0, 2, 0);
- sr32(&prcm_base->iclken3_core, 2, 1, 0);
- sr32(&prcm_base->fclken3_core, 2, 1, 0);
- return 0;
+}
+/*
- Initialize the OMAP3 EHCI controller and PHY.
- Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
- See there for additional Copyrights.
- */
+int ehci_hcd_init(void) +{
- int ret;
- debug("Initializing OMAP3 EHCI\n");
- ret = board_usb_init();
- if (ret < 0)
return ret;- /* Put the PHY in RESET */
- omap_ehci_phy_reset(1, 10);
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
- sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
- /*
* Enable USBHOST_48M_FCLK (USBHOST_FCLK1)* and USBHOST_120M_FCLK (USBHOST_FCLK2)*/- sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
- /* Enable USBTTL_ICLK */
- sr32(&prcm_base->iclken3_core, 2, 1, 1);
- /* Enable USBTTL_FCLK */
- sr32(&prcm_base->fclken3_core, 2, 1, 1);
- debug("USB clocks enabled\n");
- /* perform TLL soft reset, and wait until reset is complete */
- writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);- /* Wait for TLL reset to complete */
- while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
& OMAP_USBTLL_SYSSTATUS_RESETDONE));- debug("TLL reset done\n");
- writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
OMAP_USBTLL_SYSCONFIG_SIDLEMODE |OMAP_USBTLL_SYSCONFIG_CACTIVITY,OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);- /* Put UHH in NoIdle/NoStandby mode */
- writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP
| OMAP_UHH_SYSCONFIG_SIDLEMODE| OMAP_UHH_SYSCONFIG_CACTIVITY| OMAP_UHH_SYSCONFIG_MIDLEMODE,OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);- /* setup burst configurations */
- writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);- omap_ehci_phy_reset(0, 10);
- hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
- hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
- debug("OMAP3 EHCI init done\n");
- return 0;
+} diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 91af8a0..b4d6443 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -129,6 +129,9 @@ /* USB EHCI */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX
Hi IIya Yanok,
Sorry for late comments.
On Tue, Dec 13, 2011 at 4:45 AM, Ilya Yanok yanok@emcraft.com wrote:
Taken from Beagle code. Tested on mcx board (AM3517-based).
Signed-off-by: Ilya Yanok yanok@emcraft.com
Changes from V3: - None Changes from V2: - None Changes from V1: - CONFIG_OMAP_EHCI_PHYx_RESET changed to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO - phy reset moved to separate function - Calls to gpio_set_value after gpio_direction_output removed
Here I see lot of stuff are just being moved from beagle board to new file ehci-omap.c , but echi-omap.c is not generic enough for re-use I think we should maintain clock handling and any gpio reset in board file itself and just implement stuff related to ehci only like tll reset and ulpi phy configuration or hsic mode configuration based on some data passed from board file.
So we can re-use most of ehci-omap.c, I have done a similar approach as said which is intending to provide generic ehci-omap.c usage, which I was planning to re-use for beagle board, But since you are at it already can we make ehci-omap.c more generic.
As we are planning to re-use ehci-omap.c for panda and other board support. Reference to patch done for panda initially.
http://patchwork.ozlabs.org/patch/131362/
One thing that I planning to do in this patch is moving all reg offsets from asm/ehci.h to include/asm/arch-omap4/ehci.h and retain only generic stuff in ehci.h thus we can have offsets from beagle from */arch-omap3/ehci.h and re-use most code from ehci-omap.c
board/ti/beagle/beagle.c | 101 -------------------------- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-omap.c | 156 ++++++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 3 + 4 files changed, 160 insertions(+), 101 deletions(-) create mode 100644 drivers/usb/host/ehci-omap.c
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6a457cb..3d63028 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -42,15 +42,6 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> -#ifdef CONFIG_USB_EHCI -#include <usb.h> -#include <asm/arch/clocks.h> -#include <asm/arch/clocks_omap3.h> -#include <asm/arch/ehci_omap3.h> -/* from drivers/usb/host/ehci-core.h */ -extern struct ehci_hccr *hccr; -extern volatile struct ehci_hcor *hcor; -#endif #include "beagle.h" #include <command.h>
@@ -441,104 +432,12 @@ int board_mmc_init(bd_t *bis) #endif
#ifdef CONFIG_USB_EHCI
-#define GPIO_PHY_RESET 147
-/* Reset is needed otherwise the kernel-driver will throw an error. */ -int ehci_hcd_stop(void) -{
- pr_debug("Resetting OMAP3 EHCI\n");
- gpio_set_value(GPIO_PHY_RESET, 0);
- writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
- /* disable USB clocks */
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- sr32(&prcm_base->iclken_usbhost, 0, 1, 0);
- sr32(&prcm_base->fclken_usbhost, 0, 2, 0);
- sr32(&prcm_base->iclken3_core, 2, 1, 0);
- sr32(&prcm_base->fclken3_core, 2, 1, 0);
- return 0;
-}
As said above only uhh reset should be done in ehci-omap and clock and gpio can be left in baird file itslef you can just implement ehci_omap_hcd_stop that will reset uhh.
/* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) { if(val == 15) usb_stop(); }
-/*
- Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard.
- Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
- See there for additional Copyrights.
- */
-int ehci_hcd_init(void) -{
- pr_debug("Initializing OMAP3 ECHI\n");
- /* Put the PHY in RESET */
- gpio_request(GPIO_PHY_RESET, "");
- gpio_direction_output(GPIO_PHY_RESET, 0);
- gpio_set_value(GPIO_PHY_RESET, 0);
- /* Hold the PHY in RESET for enough time till DIR is high */
- /* Refer: ISSUE1 */
- udelay(10);
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
- sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
- /*
- * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
- * and USBHOST_120M_FCLK (USBHOST_FCLK2)
- */
- sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
- /* Enable USBTTL_ICLK */
- sr32(&prcm_base->iclken3_core, 2, 1, 1);
- /* Enable USBTTL_FCLK */
- sr32(&prcm_base->fclken3_core, 2, 1, 1);
- pr_debug("USB clocks enabled\n");
same here also must be left in beagle board file and implement omap_ehci_hcd_init() which will reset uhh, tll and configure phy_ulpi mode.
- /* perform TLL soft reset, and wait until reset is complete */
- writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
- OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
- /* Wait for TLL reset to complete */
- while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
- & OMAP_USBTLL_SYSSTATUS_RESETDONE));
- pr_debug("TLL reset done\n");
- writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
- OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
- OMAP_USBTLL_SYSCONFIG_CACTIVITY,
- OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
- /* Put UHH in NoIdle/NoStandby mode */
- writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP
- | OMAP_UHH_SYSCONFIG_SIDLEMODE
- | OMAP_UHH_SYSCONFIG_CACTIVITY
- | OMAP_UHH_SYSCONFIG_MIDLEMODE,
- OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
- /* setup burst configurations */
- writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
- | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
- | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,
- OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);
- /*
- * Refer ISSUE1:
- * Hold the PHY in RESET for enough time till
- * PHY is settled and ready
- */
- udelay(10);
- gpio_set_value(GPIO_PHY_RESET, 1);
- hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
- hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
- pr_debug("OMAP3 EHCI init done\n");
- return 0;
-}
#endif /* CONFIG_USB_EHCI */
#ifndef CONFIG_SPL_BUILD diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 77e217f..975c3e5 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -43,6 +43,7 @@ endif COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o +COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c new file mode 100644 index 0000000..93d3bb7 --- /dev/null +++ b/drivers/usb/host/ehci-omap.c @@ -0,0 +1,156 @@ +/*
- (C) Copyright 2011 Ilya Yanok, Emcraft Systems
- (C) Copyright 2004-2008
- Texas Instruments, <www.ti.com>
- Derived from Beagle Board code by
- Sunil Kumar sunilsaini05@gmail.com
- Shashi Ranjan shashiranjanmca05@gmail.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#include <common.h> +#include <usb.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clocks.h> +#include <asm/arch/clocks_omap3.h> +#include <asm/arch/ehci_omap3.h>
if this can be renamed to just ehci.h it will be better from re-use perspective since I can add just ehci.h for omap4/5 in the arch folders and based on config used it will pickup the file used.
+#include <asm/arch/sys_proto.h> +#include "ehci-core.h"
+inline int __board_usb_init(void) +{
- return 0;
+} +int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
+#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
- defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
+/* controls PHY(s) reset signal(s) */ +static inline void omap_ehci_phy_reset(int on, int delay) +{
- /*
- * Refer ISSUE1:
- * Hold the PHY in RESET for enough time till
- * PHY is settled and ready
- */
- if (delay && !on)
- udelay(delay);
+#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
- gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
+#endif +#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
- gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
+#endif
- /* Hold the PHY in RESET for enough time till DIR is high */
- /* Refer: ISSUE1 */
- if (delay && on)
- udelay(delay);
+} +#else +#define omap_ehci_phy_reset(on, delay) do {} while (0) +#endif
+/* Reset is needed otherwise the kernel-driver will throw an error. */ +int ehci_hcd_stop(void) +{
- debug("Resetting OMAP3 EHCI\n");
- omap_ehci_phy_reset(1, 0);
- writel(OMAP_UHH_SYSCONFIG_SOFTRESET,
- OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
- /* disable USB clocks */
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- sr32(&prcm_base->iclken_usbhost, 0, 1, 0);
- sr32(&prcm_base->fclken_usbhost, 0, 2, 0);
- sr32(&prcm_base->iclken3_core, 2, 1, 0);
- sr32(&prcm_base->fclken3_core, 2, 1, 0);
- return 0;
+}
+/*
- Initialize the OMAP3 EHCI controller and PHY.
- Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
- See there for additional Copyrights.
- */
+int ehci_hcd_init(void) +{
- int ret;
- debug("Initializing OMAP3 EHCI\n");
- ret = board_usb_init();
- if (ret < 0)
- return ret;
- /* Put the PHY in RESET */
- omap_ehci_phy_reset(1, 10);
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
- sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
- /*
- * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
- * and USBHOST_120M_FCLK (USBHOST_FCLK2)
- */
- sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
- /* Enable USBTTL_ICLK */
- sr32(&prcm_base->iclken3_core, 2, 1, 1);
- /* Enable USBTTL_FCLK */
- sr32(&prcm_base->fclken3_core, 2, 1, 1);
- debug("USB clocks enabled\n");
- /* perform TLL soft reset, and wait until reset is complete */
- writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
- OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
- /* Wait for TLL reset to complete */
- while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
- & OMAP_USBTLL_SYSSTATUS_RESETDONE))
- ;
- debug("TLL reset done\n");
- writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
- OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
- OMAP_USBTLL_SYSCONFIG_CACTIVITY,
- OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
- /* Put UHH in NoIdle/NoStandby mode */
- writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP
- | OMAP_UHH_SYSCONFIG_SIDLEMODE
- | OMAP_UHH_SYSCONFIG_CACTIVITY
- | OMAP_UHH_SYSCONFIG_MIDLEMODE,
- OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
- /* setup burst configurations */
- writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
- | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
- | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,
- OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);
- omap_ehci_phy_reset(0, 10);
- hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
- hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
- debug("OMAP3 EHCI init done\n");
- return 0;
+} diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 91af8a0..b4d6443 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -129,6 +129,9 @@ /* USB EHCI */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */
Any reason for this?
Probably we are missing #define CONFIG_EHCI_DCACHE
Let me know if you intend to clean up it up or I can take up and re-base my stuff by moving back the clock and gpio stuff back to beagle board. or can we re-use ehci-omap.c done for panda for beagle?
-- Thanks, Govindraj.R
Hi Govindraj,
On 12/22/11 08:55, Govindraj wrote:
Hi IIya Yanok,
Sorry for late comments.
Better late than never...
On Tue, Dec 13, 2011 at 4:45 AM, Ilya Yanok yanok@emcraft.com wrote:
Taken from Beagle code. Tested on mcx board (AM3517-based).
Signed-off-by: Ilya Yanok yanok@emcraft.com
Changes from V3:
- None
Changes from V2:
- None
Changes from V1:
- CONFIG_OMAP_EHCI_PHYx_RESET changed to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO
- phy reset moved to separate function
- Calls to gpio_set_value after gpio_direction_output removed
Here I see lot of stuff are just being moved from beagle board to new file ehci-omap.c , but echi-omap.c is not generic enough for re-use I think we should maintain clock handling and any gpio reset in board file itself
Hmmm, not really... Current clock handling is SoC specific and not board specific, so if we are about to make this file generic for more then one SoC (e.g. OMAP4), then we should also introduce a per SoC clock handling files, and reuse them with various boards.
Probably the same should hold for the GPIO reset code, because otherwise code duplication is unavoidable.
and just implement stuff related to ehci only like tll reset and ulpi phy configuration or hsic mode configuration based on some data passed from board file.
So we can re-use most of ehci-omap.c, I have done a similar approach as said which is intending to provide generic ehci-omap.c usage, which I was planning to re-use for beagle board, But since you are at it already can we make ehci-omap.c more generic.
+1
As we are planning to re-use ehci-omap.c for panda and other board support. Reference to patch done for panda initially.
http://patchwork.ozlabs.org/patch/131362/
One thing that I planning to do in this patch is moving all reg offsets from asm/ehci.h to include/asm/arch-omap4/ehci.h and retain only generic stuff in ehci.h thus we can have offsets from beagle from */arch-omap3/ehci.h and re-use most code from ehci-omap.c
board/ti/beagle/beagle.c | 101 -------------------------- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-omap.c | 156 ++++++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 3 + 4 files changed, 160 insertions(+), 101 deletions(-) create mode 100644 drivers/usb/host/ehci-omap.c
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6a457cb..3d63028 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -42,15 +42,6 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> -#ifdef CONFIG_USB_EHCI -#include <usb.h> -#include <asm/arch/clocks.h> -#include <asm/arch/clocks_omap3.h> -#include <asm/arch/ehci_omap3.h> -/* from drivers/usb/host/ehci-core.h */ -extern struct ehci_hccr *hccr; -extern volatile struct ehci_hcor *hcor; -#endif #include "beagle.h" #include <command.h>
@@ -441,104 +432,12 @@ int board_mmc_init(bd_t *bis) #endif
#ifdef CONFIG_USB_EHCI
-#define GPIO_PHY_RESET 147
-/* Reset is needed otherwise the kernel-driver will throw an error. */ -int ehci_hcd_stop(void) -{
pr_debug("Resetting OMAP3 EHCI\n");gpio_set_value(GPIO_PHY_RESET, 0);writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);/* disable USB clocks */struct prcm *prcm_base = (struct prcm *)PRCM_BASE;sr32(&prcm_base->iclken_usbhost, 0, 1, 0);sr32(&prcm_base->fclken_usbhost, 0, 2, 0);sr32(&prcm_base->iclken3_core, 2, 1, 0);sr32(&prcm_base->fclken3_core, 2, 1, 0);return 0;-}
As said above only uhh reset should be done in ehci-omap and clock and gpio can be left in baird file itslef you can just implement ehci_omap_hcd_stop that will reset uhh.
Or add SoC specific ehci_clk_disable() and put the clock handling in it.
/* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) { if(val == 15) usb_stop(); }
-/*
- Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard.
- Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
- See there for additional Copyrights.
- */
-int ehci_hcd_init(void) -{
pr_debug("Initializing OMAP3 ECHI\n");/* Put the PHY in RESET */gpio_request(GPIO_PHY_RESET, "");gpio_direction_output(GPIO_PHY_RESET, 0);gpio_set_value(GPIO_PHY_RESET, 0);/* Hold the PHY in RESET for enough time till DIR is high *//* Refer: ISSUE1 */udelay(10);struct prcm *prcm_base = (struct prcm *)PRCM_BASE;/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */sr32(&prcm_base->iclken_usbhost, 0, 1, 1);/** Enable USBHOST_48M_FCLK (USBHOST_FCLK1)* and USBHOST_120M_FCLK (USBHOST_FCLK2)*/sr32(&prcm_base->fclken_usbhost, 0, 2, 3);/* Enable USBTTL_ICLK */sr32(&prcm_base->iclken3_core, 2, 1, 1);/* Enable USBTTL_FCLK */sr32(&prcm_base->fclken3_core, 2, 1, 1);pr_debug("USB clocks enabled\n");same here also must be left in beagle board file and implement omap_ehci_hcd_init() which will reset uhh, tll and configure phy_ulpi mode.
SoC specific ehci_clk_enable() should be better then in board code.
/* perform TLL soft reset, and wait until reset is complete */writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);/* Wait for TLL reset to complete */while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)& OMAP_USBTLL_SYSSTATUS_RESETDONE));pr_debug("TLL reset done\n");writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |OMAP_USBTLL_SYSCONFIG_SIDLEMODE |OMAP_USBTLL_SYSCONFIG_CACTIVITY,OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);/* Put UHH in NoIdle/NoStandby mode */writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP| OMAP_UHH_SYSCONFIG_SIDLEMODE| OMAP_UHH_SYSCONFIG_CACTIVITY| OMAP_UHH_SYSCONFIG_MIDLEMODE,OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);/* setup burst configurations */writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);/** Refer ISSUE1:* Hold the PHY in RESET for enough time till* PHY is settled and ready*/udelay(10);gpio_set_value(GPIO_PHY_RESET, 1);hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);pr_debug("OMAP3 EHCI init done\n");return 0;-}
#endif /* CONFIG_USB_EHCI */
#ifndef CONFIG_SPL_BUILD diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 77e217f..975c3e5 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -43,6 +43,7 @@ endif COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o +COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c new file mode 100644 index 0000000..93d3bb7 --- /dev/null +++ b/drivers/usb/host/ehci-omap.c @@ -0,0 +1,156 @@ +/*
- (C) Copyright 2011 Ilya Yanok, Emcraft Systems
- (C) Copyright 2004-2008
- Texas Instruments, <www.ti.com>
- Derived from Beagle Board code by
Sunil Kumar <sunilsaini05@gmail.com>
Shashi Ranjan <shashiranjanmca05@gmail.com>
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#include <common.h> +#include <usb.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clocks.h> +#include <asm/arch/clocks_omap3.h> +#include <asm/arch/ehci_omap3.h>
if this can be renamed to just ehci.h it will be better from re-use perspective since I can add just ehci.h for omap4/5 in the arch folders and based on config used it will pickup the file used.
+1
+#include <asm/arch/sys_proto.h> +#include "ehci-core.h"
+inline int __board_usb_init(void) +{
return 0;+} +int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
+#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)+/* controls PHY(s) reset signal(s) */ +static inline void omap_ehci_phy_reset(int on, int delay) +{
/** Refer ISSUE1:* Hold the PHY in RESET for enough time till* PHY is settled and ready*/if (delay && !on)udelay(delay);+#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);+#endif +#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);+#endif
/* Hold the PHY in RESET for enough time till DIR is high *//* Refer: ISSUE1 */if (delay && on)udelay(delay);+} +#else +#define omap_ehci_phy_reset(on, delay) do {} while (0) +#endif
+/* Reset is needed otherwise the kernel-driver will throw an error. */ +int ehci_hcd_stop(void) +{
debug("Resetting OMAP3 EHCI\n");omap_ehci_phy_reset(1, 0);writel(OMAP_UHH_SYSCONFIG_SOFTRESET,OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);/* disable USB clocks */struct prcm *prcm_base = (struct prcm *)PRCM_BASE;sr32(&prcm_base->iclken_usbhost, 0, 1, 0);sr32(&prcm_base->fclken_usbhost, 0, 2, 0);sr32(&prcm_base->iclken3_core, 2, 1, 0);sr32(&prcm_base->fclken3_core, 2, 1, 0);return 0;+}
+/*
- Initialize the OMAP3 EHCI controller and PHY.
- Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
- See there for additional Copyrights.
- */
+int ehci_hcd_init(void) +{
int ret;debug("Initializing OMAP3 EHCI\n");ret = board_usb_init();if (ret < 0)return ret;/* Put the PHY in RESET */omap_ehci_phy_reset(1, 10);struct prcm *prcm_base = (struct prcm *)PRCM_BASE;/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */sr32(&prcm_base->iclken_usbhost, 0, 1, 1);/** Enable USBHOST_48M_FCLK (USBHOST_FCLK1)* and USBHOST_120M_FCLK (USBHOST_FCLK2)*/sr32(&prcm_base->fclken_usbhost, 0, 2, 3);/* Enable USBTTL_ICLK */sr32(&prcm_base->iclken3_core, 2, 1, 1);/* Enable USBTTL_FCLK */sr32(&prcm_base->fclken3_core, 2, 1, 1);debug("USB clocks enabled\n");/* perform TLL soft reset, and wait until reset is complete */writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);/* Wait for TLL reset to complete */while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)& OMAP_USBTLL_SYSSTATUS_RESETDONE));debug("TLL reset done\n");writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |OMAP_USBTLL_SYSCONFIG_SIDLEMODE |OMAP_USBTLL_SYSCONFIG_CACTIVITY,OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);/* Put UHH in NoIdle/NoStandby mode */writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP| OMAP_UHH_SYSCONFIG_SIDLEMODE| OMAP_UHH_SYSCONFIG_CACTIVITY| OMAP_UHH_SYSCONFIG_MIDLEMODE,OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);/* setup burst configurations */writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);omap_ehci_phy_reset(0, 10);hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);debug("OMAP3 EHCI init done\n");return 0;+} diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 91af8a0..b4d6443 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -129,6 +129,9 @@ /* USB EHCI */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */
Any reason for this?
Probably we are missing #define CONFIG_EHCI_DCACHE
Let me know if you intend to clean up it up or I can take up and re-base my stuff by moving back the clock and gpio stuff back to beagle board.
Please, don't move the clocks handling code back to board file. It should not be there. It should be available to all boards having OMAP3 SoC. I think this also stands for OMAP4 boards unless it is so panda specific, which I think is not the case.
or can we re-use ehci-omap.c done for panda for beagle?
Agreed, but please, understand - the world is not only beagle and panda. You need to let other boards benefit from that code (that is the intension in generalizing stuff, right?) which is not board specific.
Hi Igor,
On Thu, Dec 22, 2011 at 1:44 PM, Igor Grinberg grinberg@compulab.co.il wrote:
Hi Govindraj,
On 12/22/11 08:55, Govindraj wrote:
Hi IIya Yanok,
Sorry for late comments.
Better late than never...
On Tue, Dec 13, 2011 at 4:45 AM, Ilya Yanok yanok@emcraft.com wrote:
Taken from Beagle code. Tested on mcx board (AM3517-based).
Signed-off-by: Ilya Yanok yanok@emcraft.com
Changes from V3: - None Changes from V2: - None Changes from V1: - CONFIG_OMAP_EHCI_PHYx_RESET changed to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO - phy reset moved to separate function - Calls to gpio_set_value after gpio_direction_output removed
Here I see lot of stuff are just being moved from beagle board to new file ehci-omap.c , but echi-omap.c is not generic enough for re-use I think we should maintain clock handling and any gpio reset in board file itself
Hmmm, not really... Current clock handling is SoC specific and not board specific, so if we are about to make this file generic for more then one SoC (e.g. OMAP4), then we should also introduce a per SoC clock handling files, and reuse them with various boards.
Probably the same should hold for the GPIO reset code, because otherwise code duplication is unavoidable.
yes true,
gpio reset needed for boards having ehci connected to a external hub can pass as flag with a gpio number from board file.
and just implement stuff related to ehci only like tll reset and ulpi phy configuration or hsic mode configuration based on some data passed from board file.
So we can re-use most of ehci-omap.c, I have done a similar approach as said which is intending to provide generic ehci-omap.c usage, which I was planning to re-use for beagle board, But since you are at it already can we make ehci-omap.c more generic.
+1
Thanks, Will wait for IIya Yanok's feedback on the approach to be followed (whether to re-base from this patch or use my series to clean up beagle).
As we are planning to re-use ehci-omap.c for panda and other board support. Reference to patch done for panda initially.
http://patchwork.ozlabs.org/patch/131362/
One thing that I planning to do in this patch is moving all reg offsets from asm/ehci.h to include/asm/arch-omap4/ehci.h and retain only generic stuff in ehci.h thus we can have offsets from beagle from */arch-omap3/ehci.h and re-use most code from ehci-omap.c
board/ti/beagle/beagle.c | 101 -------------------------- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-omap.c | 156 ++++++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 3 + 4 files changed, 160 insertions(+), 101 deletions(-) create mode 100644 drivers/usb/host/ehci-omap.c
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6a457cb..3d63028 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -42,15 +42,6 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> -#ifdef CONFIG_USB_EHCI -#include <usb.h> -#include <asm/arch/clocks.h> -#include <asm/arch/clocks_omap3.h> -#include <asm/arch/ehci_omap3.h> -/* from drivers/usb/host/ehci-core.h */ -extern struct ehci_hccr *hccr; -extern volatile struct ehci_hcor *hcor; -#endif #include "beagle.h" #include <command.h>
@@ -441,104 +432,12 @@ int board_mmc_init(bd_t *bis) #endif
#ifdef CONFIG_USB_EHCI
-#define GPIO_PHY_RESET 147
-/* Reset is needed otherwise the kernel-driver will throw an error. */ -int ehci_hcd_stop(void) -{
- pr_debug("Resetting OMAP3 EHCI\n");
- gpio_set_value(GPIO_PHY_RESET, 0);
- writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
- /* disable USB clocks */
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- sr32(&prcm_base->iclken_usbhost, 0, 1, 0);
- sr32(&prcm_base->fclken_usbhost, 0, 2, 0);
- sr32(&prcm_base->iclken3_core, 2, 1, 0);
- sr32(&prcm_base->fclken3_core, 2, 1, 0);
- return 0;
-}
As said above only uhh reset should be done in ehci-omap and clock and gpio can be left in baird file itslef you can just implement ehci_omap_hcd_stop that will reset uhh.
Or add SoC specific ehci_clk_disable() and put the clock handling in it.
probably the right method to do is as we did for panda,
Add to armv7/omap3/clock.c (soc specific code) to enable usb-host clocks.
as done in below patch for omap4 socs.
http://patchwork.ozlabs.org/patch/131365/
/* Call usb_stop() before starting the kernel */ void show_boot_progress(int val) { if(val == 15) usb_stop(); }
-/*
- Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard.
- Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
- See there for additional Copyrights.
- */
-int ehci_hcd_init(void) -{
- pr_debug("Initializing OMAP3 ECHI\n");
- /* Put the PHY in RESET */
- gpio_request(GPIO_PHY_RESET, "");
- gpio_direction_output(GPIO_PHY_RESET, 0);
- gpio_set_value(GPIO_PHY_RESET, 0);
- /* Hold the PHY in RESET for enough time till DIR is high */
- /* Refer: ISSUE1 */
- udelay(10);
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
- sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
- /*
- * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
- * and USBHOST_120M_FCLK (USBHOST_FCLK2)
- */
- sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
- /* Enable USBTTL_ICLK */
- sr32(&prcm_base->iclken3_core, 2, 1, 1);
- /* Enable USBTTL_FCLK */
- sr32(&prcm_base->fclken3_core, 2, 1, 1);
- pr_debug("USB clocks enabled\n");
same here also must be left in beagle board file and implement omap_ehci_hcd_init() which will reset uhh, tll and configure phy_ulpi mode.
SoC specific ehci_clk_enable() should be better then in board code.
yes probably or even better add to clock framework as done for omap4 (in patch work link shared above)
- /* perform TLL soft reset, and wait until reset is complete */
- writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
- OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
- /* Wait for TLL reset to complete */
- while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
- & OMAP_USBTLL_SYSSTATUS_RESETDONE));
- pr_debug("TLL reset done\n");
- writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
- OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
- OMAP_USBTLL_SYSCONFIG_CACTIVITY,
- OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
- /* Put UHH in NoIdle/NoStandby mode */
- writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP
- | OMAP_UHH_SYSCONFIG_SIDLEMODE
- | OMAP_UHH_SYSCONFIG_CACTIVITY
- | OMAP_UHH_SYSCONFIG_MIDLEMODE,
- OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
- /* setup burst configurations */
- writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
- | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
- | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,
- OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);
- /*
- * Refer ISSUE1:
- * Hold the PHY in RESET for enough time till
- * PHY is settled and ready
- */
- udelay(10);
- gpio_set_value(GPIO_PHY_RESET, 1);
- hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
- hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
- pr_debug("OMAP3 EHCI init done\n");
- return 0;
-}
#endif /* CONFIG_USB_EHCI */
#ifndef CONFIG_SPL_BUILD diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 77e217f..975c3e5 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -43,6 +43,7 @@ endif COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o +COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c new file mode 100644 index 0000000..93d3bb7 --- /dev/null +++ b/drivers/usb/host/ehci-omap.c @@ -0,0 +1,156 @@ +/*
- (C) Copyright 2011 Ilya Yanok, Emcraft Systems
- (C) Copyright 2004-2008
- Texas Instruments, <www.ti.com>
- Derived from Beagle Board code by
- Sunil Kumar sunilsaini05@gmail.com
- Shashi Ranjan shashiranjanmca05@gmail.com
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#include <common.h> +#include <usb.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clocks.h> +#include <asm/arch/clocks_omap3.h> +#include <asm/arch/ehci_omap3.h>
if this can be renamed to just ehci.h it will be better from re-use perspective since I can add just ehci.h for omap4/5 in the arch folders and based on config used it will pickup the file used.
+1
+#include <asm/arch/sys_proto.h> +#include "ehci-core.h"
+inline int __board_usb_init(void) +{
- return 0;
+} +int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
+#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
- defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
+/* controls PHY(s) reset signal(s) */ +static inline void omap_ehci_phy_reset(int on, int delay) +{
- /*
- * Refer ISSUE1:
- * Hold the PHY in RESET for enough time till
- * PHY is settled and ready
- */
- if (delay && !on)
- udelay(delay);
+#ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
- gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
+#endif +#ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
- gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
- gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
+#endif
- /* Hold the PHY in RESET for enough time till DIR is high */
- /* Refer: ISSUE1 */
- if (delay && on)
- udelay(delay);
+} +#else +#define omap_ehci_phy_reset(on, delay) do {} while (0) +#endif
+/* Reset is needed otherwise the kernel-driver will throw an error. */ +int ehci_hcd_stop(void) +{
- debug("Resetting OMAP3 EHCI\n");
- omap_ehci_phy_reset(1, 0);
- writel(OMAP_UHH_SYSCONFIG_SOFTRESET,
- OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
- /* disable USB clocks */
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- sr32(&prcm_base->iclken_usbhost, 0, 1, 0);
- sr32(&prcm_base->fclken_usbhost, 0, 2, 0);
- sr32(&prcm_base->iclken3_core, 2, 1, 0);
- sr32(&prcm_base->fclken3_core, 2, 1, 0);
- return 0;
+}
+/*
- Initialize the OMAP3 EHCI controller and PHY.
- Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
- See there for additional Copyrights.
- */
+int ehci_hcd_init(void) +{
- int ret;
- debug("Initializing OMAP3 EHCI\n");
- ret = board_usb_init();
- if (ret < 0)
- return ret;
- /* Put the PHY in RESET */
- omap_ehci_phy_reset(1, 10);
- struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
- /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
- sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
- /*
- * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
- * and USBHOST_120M_FCLK (USBHOST_FCLK2)
- */
- sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
- /* Enable USBTTL_ICLK */
- sr32(&prcm_base->iclken3_core, 2, 1, 1);
- /* Enable USBTTL_FCLK */
- sr32(&prcm_base->fclken3_core, 2, 1, 1);
- debug("USB clocks enabled\n");
- /* perform TLL soft reset, and wait until reset is complete */
- writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET,
- OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
- /* Wait for TLL reset to complete */
- while (!(readl(OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSSTATUS)
- & OMAP_USBTLL_SYSSTATUS_RESETDONE))
- ;
- debug("TLL reset done\n");
- writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
- OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
- OMAP_USBTLL_SYSCONFIG_CACTIVITY,
- OMAP3_USBTLL_BASE + OMAP_USBTLL_SYSCONFIG);
- /* Put UHH in NoIdle/NoStandby mode */
- writel(OMAP_UHH_SYSCONFIG_ENAWAKEUP
- | OMAP_UHH_SYSCONFIG_SIDLEMODE
- | OMAP_UHH_SYSCONFIG_CACTIVITY
- | OMAP_UHH_SYSCONFIG_MIDLEMODE,
- OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);
- /* setup burst configurations */
- writel(OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
- | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
- | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN,
- OMAP3_UHH_BASE + OMAP_UHH_HOSTCONFIG);
- omap_ehci_phy_reset(0, 10);
- hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE);
- hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE + 0x10);
- debug("OMAP3 EHCI init done\n");
- return 0;
+} diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 91af8a0..b4d6443 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -129,6 +129,9 @@ /* USB EHCI */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */
Any reason for this?
Probably we are missing #define CONFIG_EHCI_DCACHE
Let me know if you intend to clean up it up or I can take up and re-base my stuff by moving back the clock and gpio stuff back to beagle board.
Please, don't move the clocks handling code back to board file. It should not be there. It should be available to all boards having OMAP3 SoC. I think this also stands for OMAP4 boards unless it is so panda specific, which I think is not the case.
Sorry for confusion here, Actually it should be handled with soc specific clock framework.
or can we re-use ehci-omap.c done for panda for beagle?
Agreed, but please, understand - the world is not only beagle and panda. You need to let other boards benefit from that code (that is the intension in generalizing stuff, right?) which is not board specific.
Yes Agree.. :) intention is to re-use ehci-omap.c across some socs, and boards.
until IP block doesn't change for a new soc !!
-- Thanks, Govindraj.R
On 12/22/11 11:26, Govindraj wrote:
Hi Igor,
On Thu, Dec 22, 2011 at 1:44 PM, Igor Grinberg grinberg@compulab.co.il wrote:
Hi Govindraj,
On 12/22/11 08:55, Govindraj wrote:
Hi IIya Yanok,
[...]
On Tue, Dec 13, 2011 at 4:45 AM, Ilya Yanok yanok@emcraft.com wrote:
Taken from Beagle code. Tested on mcx board (AM3517-based).
Signed-off-by: Ilya Yanok yanok@emcraft.com
[...]
-/* Reset is needed otherwise the kernel-driver will throw an error. */ -int ehci_hcd_stop(void) -{
pr_debug("Resetting OMAP3 EHCI\n");gpio_set_value(GPIO_PHY_RESET, 0);writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG);/* disable USB clocks */struct prcm *prcm_base = (struct prcm *)PRCM_BASE;sr32(&prcm_base->iclken_usbhost, 0, 1, 0);sr32(&prcm_base->fclken_usbhost, 0, 2, 0);sr32(&prcm_base->iclken3_core, 2, 1, 0);sr32(&prcm_base->fclken3_core, 2, 1, 0);return 0;-}
As said above only uhh reset should be done in ehci-omap and clock and gpio can be left in baird file itslef you can just implement ehci_omap_hcd_stop that will reset uhh.
Or add SoC specific ehci_clk_disable() and put the clock handling in it.
probably the right method to do is as we did for panda,
Add to armv7/omap3/clock.c (soc specific code) to enable usb-host clocks.
as done in below patch for omap4 socs.
Hmmm... I don't like that patch - this is the right method... but only for panda! For panda it makes sense to enable the USB related clocks by default because it has many of its boot important peripherals wired to USB. That is not the case with majority of OMAP3 (and I bet with many other OMAP4) boards. Therefore, I think the USB clocks need to be turned on only if the board requests them to be turned on and not as a part of the default clock initialization by the PRCM subsystem (unless it is configurable in the board config file).
[...]
-/*
- Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard.
- Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37.
- See there for additional Copyrights.
- */
-int ehci_hcd_init(void) -{
pr_debug("Initializing OMAP3 ECHI\n");/* Put the PHY in RESET */gpio_request(GPIO_PHY_RESET, "");gpio_direction_output(GPIO_PHY_RESET, 0);gpio_set_value(GPIO_PHY_RESET, 0);/* Hold the PHY in RESET for enough time till DIR is high *//* Refer: ISSUE1 */udelay(10);struct prcm *prcm_base = (struct prcm *)PRCM_BASE;/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */sr32(&prcm_base->iclken_usbhost, 0, 1, 1);/** Enable USBHOST_48M_FCLK (USBHOST_FCLK1)* and USBHOST_120M_FCLK (USBHOST_FCLK2)*/sr32(&prcm_base->fclken_usbhost, 0, 2, 3);/* Enable USBTTL_ICLK */sr32(&prcm_base->iclken3_core, 2, 1, 1);/* Enable USBTTL_FCLK */sr32(&prcm_base->fclken3_core, 2, 1, 1);pr_debug("USB clocks enabled\n");same here also must be left in beagle board file and implement omap_ehci_hcd_init() which will reset uhh, tll and configure phy_ulpi mode.
SoC specific ehci_clk_enable() should be better then in board code.
yes probably or even better add to clock framework as done for omap4 (in patch work link shared above)
same comment as above
[...]
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 91af8a0..b4d6443 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -129,6 +129,9 @@ /* USB EHCI */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */
Any reason for this?
Probably we are missing #define CONFIG_EHCI_DCACHE
Let me know if you intend to clean up it up or I can take up and re-base my stuff by moving back the clock and gpio stuff back to beagle board.
Please, don't move the clocks handling code back to board file. It should not be there. It should be available to all boards having OMAP3 SoC. I think this also stands for OMAP4 boards unless it is so panda specific, which I think is not the case.
Sorry for confusion here, Actually it should be handled with soc specific clock framework.
Right, and also allow the "usb start/stop" commands do the job.
or can we re-use ehci-omap.c done for panda for beagle?
Agreed, but please, understand - the world is not only beagle and panda. You need to let other boards benefit from that code (that is the intension in generalizing stuff, right?) which is not board specific.
Yes Agree.. :) intention is to re-use ehci-omap.c across some socs, and boards.
until IP block doesn't change for a new soc !!
On Thu, Dec 22, 2011 at 3:29 PM, Igor Grinberg grinberg@compulab.co.il wrote:
On 12/22/11 11:26, Govindraj wrote:
Hi Igor,
[...]
probably the right method to do is as we did for panda,
Add to armv7/omap3/clock.c (soc specific code) to enable usb-host clocks.
as done in below patch for omap4 socs.
Hmmm... I don't like that patch - this is the right method... but only for panda! For panda it makes sense to enable the USB related clocks by default because it has many of its boot important peripherals wired to USB. That is not the case with majority of OMAP3 (and I bet with many other OMAP4) boards. Therefore, I think the USB clocks need to be turned on only if the board requests them to be turned on and not as a part of the default clock initialization by the PRCM subsystem (unless it is configurable in the board config file).
okay, I thought nothing wrong in keeping them enabled by default. since all un-used clocks will be gated once kernel is loaded. Am I missing some thing here?
so as discussed earlier we can add ehci_omap3_clock_init into ehci-omap.c that can be used from all omap3 socs.
-- Thanks, Govindraj.R
On 12/22/11 12:49, Govindraj wrote:
On Thu, Dec 22, 2011 at 3:29 PM, Igor Grinberg grinberg@compulab.co.il wrote:
On 12/22/11 11:26, Govindraj wrote:
Hi Igor,
[...]
probably the right method to do is as we did for panda,
Add to armv7/omap3/clock.c (soc specific code) to enable usb-host clocks.
as done in below patch for omap4 socs.
Hmmm... I don't like that patch - this is the right method... but only for panda! For panda it makes sense to enable the USB related clocks by default because it has many of its boot important peripherals wired to USB. That is not the case with majority of OMAP3 (and I bet with many other OMAP4) boards. Therefore, I think the USB clocks need to be turned on only if the board requests them to be turned on and not as a part of the default clock initialization by the PRCM subsystem (unless it is configurable in the board config file).
okay, I thought nothing wrong in keeping them enabled by default. since all un-used clocks will be gated once kernel is loaded. Am I missing some thing here?
May be there is nothing *too* wrong except for power consumption or may be some other things I can't think of right now... But, you should not rely on what will happen when kernel is loaded. Also, you should not assume, that the Linux kernel will be loaded at all... There are other OSes around that can also use U-Boot as a boot loader. Also, there are stand alone applications that do not use any OS at all... We are in the embedded world also, not just mobile... (And if we are talking about mobile, then power consumption is important).
so as discussed earlier we can add ehci_omap3_clock_init into ehci-omap.c that can be used from all omap3 socs.
This is a bit confusing... Let's try it that way: 1) ehci-omap.c should have common OMAP (OMAP3/4/5...) settings 2) ehci-omap.c should call ehci_clk_{enable|disable}() which should be implemented in a SoC *dependent* way (e.g. armv7/omap{3|4}/clock.c) 3) board specific stuff (e.g. PHY reset GPIO) should be passed to the common code to avoid code duplication. 4) probably, some other things that I've forgotten...
On Thu, Dec 22, 2011 at 4:48 PM, Igor Grinberg grinberg@compulab.co.il wrote:
On 12/22/11 12:49, Govindraj wrote:
On Thu, Dec 22, 2011 at 3:29 PM, Igor Grinberg grinberg@compulab.co.il wrote:
On 12/22/11 11:26, Govindraj wrote:
Hi Igor,
[...]
probably the right method to do is as we did for panda,
Add to armv7/omap3/clock.c (soc specific code) to enable usb-host clocks.
as done in below patch for omap4 socs.
Hmmm... I don't like that patch - this is the right method... but only for panda! For panda it makes sense to enable the USB related clocks by default because it has many of its boot important peripherals wired to USB. That is not the case with majority of OMAP3 (and I bet with many other OMAP4) boards. Therefore, I think the USB clocks need to be turned on only if the board requests them to be turned on and not as a part of the default clock initialization by the PRCM subsystem (unless it is configurable in the board config file).
okay, I thought nothing wrong in keeping them enabled by default. since all un-used clocks will be gated once kernel is loaded. Am I missing some thing here?
May be there is nothing *too* wrong except for power consumption or may be some other things I can't think of right now... But, you should not rely on what will happen when kernel is loaded. Also, you should not assume, that the Linux kernel will be loaded at all... There are other OSes around that can also use U-Boot as a boot loader. Also, there are stand alone applications that do not use any OS at all... We are in the embedded world also, not just mobile... (And if we are talking about mobile, then power consumption is important).
Yes Agree..
so as discussed earlier we can add ehci_omap3_clock_init into ehci-omap.c that can be used from all omap3 socs.
This is a bit confusing... Let's try it that way:
- ehci-omap.c should have common OMAP (OMAP3/4/5...) settings
- ehci-omap.c should call ehci_clk_{enable|disable}() which should
be implemented in a SoC *dependent* way (e.g. armv7/omap{3|4}/clock.c) 3) board specific stuff (e.g. PHY reset GPIO) should be passed to the common code to avoid code duplication. 4) probably, some other things that I've forgotten...
Looks fine.
I will start on the above discussed stuff on top of this patch.
-- Thanks, Govindraj.R
Hi Govindraj,
On 22.12.2011 10:55, Govindraj wrote:
Signed-off-by: Ilya Yanok yanok@emcraft.com
Changes from V3:
- None
Changes from V2:
- None
Changes from V1:
- CONFIG_OMAP_EHCI_PHYx_RESET changed to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO
- phy reset moved to separate function
- Calls to gpio_set_value after gpio_direction_output removed
Here I see lot of stuff are just being moved from beagle board to new file ehci-omap.c , but echi-omap.c is not generic enough for re-use I think we should maintain clock handling and any gpio reset in board file itself and just implement stuff related to ehci only like tll reset and ulpi phy configuration or hsic mode configuration based on some data passed from board file.
I can just say that I agree with Igor on his points. If think we should minimize board code, if something is not board-specific (like clocks) or is generic enough (like ULPI PHY GPIO reset) we should definitely try to put such code in some common place and only provide some values via board configuration.
So we can re-use most of ehci-omap.c, I have done a similar approach as said which is intending to provide generic ehci-omap.c usage, which I was planning to re-use for beagle board, But since you are at it already can we make ehci-omap.c more generic.
As we are planning to re-use ehci-omap.c for panda and other board support. Reference to patch done for panda initially.
Yes, I've seen your patches, it will be great to have common OMAP EHCI driver.
One thing that I planning to do in this patch is moving all reg offsets from asm/ehci.h to include/asm/arch-omap4/ehci.h and retain only generic stuff in ehci.h thus we can have offsets from beagle from */arch-omap3/ehci.h and
Hm. I don't really work with OMAP4 but do the offsets differ so much? Probably it makes sense to have some common header plus SoC specific part?
+#include <asm/arch/ehci_omap3.h>
if this can be renamed to just ehci.h it will be better from re-use perspective since I can add just ehci.h for omap4/5 in the arch folders and based on config used it will pickup the file used.
Surely we can rename it.
#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */
Any reason for this?
Yes, common USB code is not cache-aware anyway so you have to disable dcache before working with USB anyway.
I've send a patch for USB base support a while ago (see http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/114235 ) but it only fixes common/usb.c. Upper layers have to be fixed too.
Let me know if you intend to clean up it up or I can take up and re-base my stuff by moving back the clock and gpio stuff back to beagle board. or can we re-use ehci-omap.c done for panda for beagle?
Surely you can take it. I'd glad to see common OMAP EHCI driver.
Regards, Ilya.
Hi All,
2011/12/22 Ilya Yanok yanok@emcraft.com:
Hi Govindraj,
On 22.12.2011 10:55, Govindraj wrote:
Signed-off-by: Ilya Yanok yanok@emcraft.com
Changes from V3: - None Changes from V2: - None Changes from V1: - CONFIG_OMAP_EHCI_PHYx_RESET changed to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO - phy reset moved to separate function - Calls to gpio_set_value after gpio_direction_output removed
To me the status of this patch is not clear. Do you want this patch to be applied, and than rework the comments in a later patch? Or can we apply a cleaned up ehci-omap patch directly?
Kind regards,
Remy
On Sun, Jan 15, 2012 at 1:40 PM, Remy Bohmer linux@bohmer.net wrote:
Hi All,
2011/12/22 Ilya Yanok yanok@emcraft.com:
Hi Govindraj,
On 22.12.2011 10:55, Govindraj wrote:
Signed-off-by: Ilya Yanok yanok@emcraft.com
Changes from V3: - None Changes from V2: - None Changes from V1: - CONFIG_OMAP_EHCI_PHYx_RESET changed to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO - phy reset moved to separate function - Calls to gpio_set_value after gpio_direction_output removed
To me the status of this patch is not clear. Do you want this patch to be applied, and than rework the comments in a later patch? Or can we apply a cleaned up ehci-omap patch directly?
This has been superseded by Govindraj's series of patches that cover omap3/4.
On Mon, Jan 16, 2012 at 3:34 AM, Tom Rini tom.rini@gmail.com wrote:
On Sun, Jan 15, 2012 at 1:40 PM, Remy Bohmer linux@bohmer.net wrote:
Hi All,
2011/12/22 Ilya Yanok yanok@emcraft.com:
Hi Govindraj,
On 22.12.2011 10:55, Govindraj wrote:
Signed-off-by: Ilya Yanok yanok@emcraft.com
Changes from V3: - None Changes from V2: - None Changes from V1: - CONFIG_OMAP_EHCI_PHYx_RESET changed to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO - phy reset moved to separate function - Calls to gpio_set_value after gpio_direction_output removed
To me the status of this patch is not clear. Do you want this patch to be applied, and than rework the comments in a later patch? Or can we apply a cleaned up ehci-omap patch directly?
This has been superseded by Govindraj's series of patches that cover omap3/4.
Th v2 patch series [1] posted is based on top of this patch.
-- Thanks, Govindraj.R
[1]: PATCH v2 0/4] Clean up ehci-omap and extend support for omap3/4 socs
http://lists.denx.de/pipermail/u-boot/2012-January/114844.html
On 16/01/2012 08:58, Govindraj wrote:
Th v2 patch series [1] posted is based on top of this patch.
If I understand well, we need in any case Ilya's patch. In this case, it is maybe worth to merge Ilya's patch in the meanwhile (and please drop my patch that remove USB support from TAM3517 boards).
Best regards, Stefano
On Mon, Jan 16, 2012 at 3:27 PM, Stefano Babic sbabic@denx.de wrote:
On 16/01/2012 08:58, Govindraj wrote:
Th v2 patch series [1] posted is based on top of this patch.
If I understand well, we need in any case Ilya's patch. In this case, it is maybe worth to merge Ilya's patch in the meanwhile (and please drop my patch that remove USB support from TAM3517 boards).
Yes correct we have to pull in this patch.
Tom, Will you be taking this through omap tree?
-- Thanks, Govindraj.R
On 17/01/2012 07:14, Govindraj wrote:
On Mon, Jan 16, 2012 at 3:27 PM, Stefano Babic sbabic@denx.de wrote:
On 16/01/2012 08:58, Govindraj wrote:
Th v2 patch series [1] posted is based on top of this patch.
If I understand well, we need in any case Ilya's patch. In this case, it is maybe worth to merge Ilya's patch in the meanwhile (and please drop my patch that remove USB support from TAM3517 boards).
Yes correct we have to pull in this patch.
Tom, Will you be taking this through omap tree?
Tom,
do you see any problem about merging this patch ? It fixes the build problem on the mt_ventoux board, and there is still a Ilya's patch (mcx: support for HTKW mcx board) waiting for it
http://patchwork.ozlabs.org/patch/131431/
Stefano
On Wed, Jan 25, 2012 at 3:32 AM, Stefano Babic sbabic@denx.de wrote:
On 17/01/2012 07:14, Govindraj wrote:
On Mon, Jan 16, 2012 at 3:27 PM, Stefano Babic sbabic@denx.de wrote:
On 16/01/2012 08:58, Govindraj wrote:
Th v2 patch series [1] posted is based on top of this patch.
If I understand well, we need in any case Ilya's patch. In this case, it is maybe worth to merge Ilya's patch in the meanwhile (and please drop my patch that remove USB support from TAM3517 boards).
Yes correct we have to pull in this patch.
Tom, Will you be taking this through omap tree?
Tom,
do you see any problem about merging this patch ? It fixes the build problem on the mt_ventoux board, and there is still a Ilya's patch (mcx: support for HTKW mcx board) waiting for it
My only concern is that I would really like to wait for the cleanup / fixup series to be complete before we pull this change in as well.
On Thu, Jan 26, 2012 at 2:19 AM, Tom Rini tom.rini@gmail.com wrote:
On Wed, Jan 25, 2012 at 3:32 AM, Stefano Babic sbabic@denx.de wrote:
On 17/01/2012 07:14, Govindraj wrote:
On Mon, Jan 16, 2012 at 3:27 PM, Stefano Babic sbabic@denx.de wrote:
On 16/01/2012 08:58, Govindraj wrote:
Th v2 patch series [1] posted is based on top of this patch.
If I understand well, we need in any case Ilya's patch. In this case, it is maybe worth to merge Ilya's patch in the meanwhile (and please drop my patch that remove USB support from TAM3517 boards).
Yes correct we have to pull in this patch.
Tom, Will you be taking this through omap tree?
Tom,
do you see any problem about merging this patch ? It fixes the build problem on the mt_ventoux board, and there is still a Ilya's patch (mcx: support for HTKW mcx board) waiting for it
My only concern is that I would really like to wait for the cleanup / fixup series to be complete before we pull this change in as well.
Yes thanks,
I am working on some comments from Igor to make use of ulpi frame work for soft phy reset for ulpi phy. (reference: http://www.mail-archive.com/u-boot@lists.denx.de/msg76076.html)
Will shortly repost the changes along with this patch re-based on latest commit.
-- Thanks, Govindraj.R
On 27/01/2012 10:07, Govindraj wrote:
My only concern is that I would really like to wait for the cleanup / fixup series to be complete before we pull this change in as well.
Yes thanks,
I am working on some comments from Igor to make use of ulpi frame work for soft phy reset for ulpi phy. (reference: http://www.mail-archive.com/u-boot@lists.denx.de/msg76076.html)
Will shortly repost the changes along with this patch re-based on latest commit.
Thanks, this is the best solution.
Stefano
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Requires updated mach-types file.
Signed-off-by: Ilya Yanok yanok@emcraft.com
--- I'm sorry for non-consistent version history, I will give links to my previous posts along with version numbers.
The last ("Support for HTKW mcx") series: Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118530
- Comment for misc_init_r function fixed - Added check for gpio_request return value. - Removed #if defined(CONFIG_GENERIC_MMC) around board_mmc_init - CONFIG_USE_IRQ and related stuff removed from config - CONFIG_OMAP3_MICRON_DDR removed - CONFIG_SYS_MAXRAGS changed 32 -> 16 - Incorrect multiline comments (/*--- ones) fixed - CONFIG_SPL_MAX_SIZE rewritten 0xB400 -> (45 << 10) - CONFIG_SPL_NAND_WORKSPACE removed
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/116548
- None
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/115026
- Calls to gpio_set_value after gpio_direction_output removed - Minor style problem (tab instead of space) fixed
SPL series: Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112892
- OMAP EHCI support enabled in config - MMC SPL support enabled in config
"DaVinci EMAC and HTKW mcx support" series: Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112884
- NAND SPL support enabled in config
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112317
- removed dead code from board/htkw/mcx/Makefile as Mike suggested - removed EMAC reset (now done in generic cpu_eth_init()) - removed some unsuned defines from configuration header
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111197
- various style fixes to make checkpatch (almost) happy - FSF address removed from GPL comments - CONFIG_SYS_TEXT_BASE moved to configuration header, config.mk droped - CONFIG_MACH_TYPE is used instead of setting mach type from board code - i2c_init removed from misc_init_r - cpu_eth_init removed (added to generic place by another patch) - CONTROL_PADCONF defines removed - Fixed boolean config options not to have a value - CONFIG_MUSB_* and related defines removed
MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 91 +++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 371 ++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 913 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.h
diff --git a/MAINTAINERS b/MAINTAINERS index a56ca10..c7fcc10 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -903,6 +903,10 @@ Richard Woodruff r-woodruff2@ti.com
omap2420h4 ARM1136EJS
+Ilya Yanok yanok@emcraft.com + + mcx ARM ARMV7 (AM35x SoC) + Syed Mohammed Khasim sm.khasim@gmail.com Sughosh Ganu urwithsughosh@gmail.com
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile new file mode 100644 index 0000000..4c8db10 --- /dev/null +++ b/board/htkw/mcx/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c new file mode 100644 index 0000000..163ae98 --- /dev/null +++ b/board/htkw/mcx/mcx.c @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on ti/evm/evm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/omap_gpio.h> +#include "errno.h" +#include <i2c.h> +#include "mcx.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: late init. + */ +int misc_init_r(void) +{ + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_MCX(); +} + +#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + +#ifdef CONFIG_USB_EHCI_OMAP +#define USB_HOST_PWR_EN 132 +int board_usb_init(void) +{ + if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) { + puts("Failed to get USB_HOST_PWR_EN pin\n"); + return -ENODEV; + } + gpio_direction_output(USB_HOST_PWR_EN, 1); + + return 0; +} +#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h new file mode 100644 index 0000000..d675a48 --- /dev/null +++ b/board/htkw/mcx/mcx.h @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on ti/evm/evm.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "HTKW mcx Board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_MCX() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly0*/\ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly1*/\ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \ + /* GPIO_43 LCD buffer enable */ \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \ + /* GPIO_57 TS_PenIRQn */\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \ + /* GPIO_58 ETHERNET RESET */\ + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \ + /* GPIO_61 SD-CARD CD */ \ + MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \ + /* GPIO_62 Nand write protect, keep enabled */ \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ + /* GPIO_65 SD-CARD WP */\ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \ + /* GPIO_131 LCD Enable */ \ + MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \ + /* GPIO_132 USB host Enable */\ + MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \ + /* GPIO_133 HDMI PD */\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \ + /* GPIO_152 USB phy2 reset */\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \ + /* GPIO_153 */\ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \ + /* GPIO_154 USB phy1 reset */\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \ + /* GPIO_155 TS_BUSY */\ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat7 */\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat4 */\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat5 */\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat6 */\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat3 */\ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ + /* HDQ */\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \ + /* SYS_nRESWARM */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\ + /* ETK (ES2 onwards) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_stp */ \ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_clk */\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + +#endif diff --git a/boards.cfg b/boards.cfg index 1e5b3e0..ac606d2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -210,6 +210,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 omap5_evm arm armv7 omap5_evm ti omap5 diff --git a/include/configs/mcx.h b/include/configs/mcx.h new file mode 100644 index 0000000..eb381d7 --- /dev/null +++ b/include/configs/mcx.h @@ -0,0 +1,371 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on omap3_evm_config.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */ + +#define CONFIG_MACH_TYPE MACH_TYPE_MCX + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +#define CONFIG_OF_LIBFDT +#define CONFIG_FIT + +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/* + * DDR related + */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C + +/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "mcx # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/* + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ + 48, 49, 50, 51, 52, 53, 54, 55,\ + 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 + +/* + * ethernet support + * + */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +#endif /* __CONFIG_H */
On Mon, Dec 12, 2011 at 4:15 PM, Ilya Yanok yanok@emcraft.com wrote:
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Requires updated mach-types file.
Just define the MACH_ID locally for now so it builds still please. Also, some problems:
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{
- omap_mmc_init(0);
- return 0;
+} +#endif
That should just be return omap_mmc_init(0);
[snip to config file]
+#define CONFIG_SYS_TEXT_BASE 0x80008000
[snip]
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
You're able to have CONFIG_SYS_TEXT_BASE that low and not have the corruption problem devkit8000 had?
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
IIRC you don't need this define since this SPL says you write u-boot.img to NAND not u-boot.bin
Hi Tom,
On 13.12.2011 22:52, Tom Rini wrote:
On Mon, Dec 12, 2011 at 4:15 PM, Ilya Yanok yanok@emcraft.com wrote:
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Requires updated mach-types file.
Just define the MACH_ID locally for now so it builds still please.
Ok, will do.
Also, some problems:
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{
omap_mmc_init(0);return 0;+} +#endif
That should just be return omap_mmc_init(0);
Surely. I've been told about this one already but forgot to fix it. Sorry.
[snip to config file]
+#define CONFIG_SYS_TEXT_BASE 0x80008000
[snip]
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
You're able to have CONFIG_SYS_TEXT_BASE that low and not have the corruption problem devkit8000 had?
Hm. What corruption problem?
+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
IIRC you don't need this define since this SPL says you write u-boot.img to NAND not u-boot.bin
Right.
Regards, Ilya.
Hi Tom,
On 13.12.2011 22:52, Tom Rini wrote:
+#define CONFIG_SYS_TEXT_BASE 0x80008000
[snip]
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
You're able to have CONFIG_SYS_TEXT_BASE that low and not have the corruption problem devkit8000 had?
No, I can't see any problems. I have to say I can't do _real_ MMC boot, as my board lacks the required jumper, so I'm testing it but starting SPL from NAND, rewriting omap3_boot_device to be MMC with BDI and running it further. It reads u-boot.img from MMC and starts it without any problem.
Regards, Ilya.
On Tue, Dec 13, 2011 at 12:13 PM, Ilya Yanok yanok@emcraft.com wrote:
Hi Tom,
On 13.12.2011 22:52, Tom Rini wrote:
+#define CONFIG_SYS_TEXT_BASE 0x80008000
[snip]
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
You're able to have CONFIG_SYS_TEXT_BASE that low and not have the corruption problem devkit8000 had?
No, I can't see any problems. I have to say I can't do _real_ MMC boot, as my board lacks the required jumper, so I'm testing it but starting SPL from NAND, rewriting omap3_boot_device to be MMC with BDI and running it further. It reads u-boot.img from MMC and starts it without any problem.
Well, is it just your board that's missing the jumper, or the MCX HTWK lacks the jumper? If the latter, just drop the MMC bits out :)
Hi Tom,
On 13.12.2011 23:30, Tom Rini wrote:
+#define CONFIG_SYS_TEXT_BASE 0x80008000
[snip]
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
You're able to have CONFIG_SYS_TEXT_BASE that low and not have the corruption problem devkit8000 had?
No, I can't see any problems. I have to say I can't do _real_ MMC boot, as my board lacks the required jumper, so I'm testing it but starting SPL from NAND, rewriting omap3_boot_device to be MMC with BDI and running it further. It reads u-boot.img from MMC and starts it without any problem.
Well, is it just your board that's missing the jumper, or the MCX HTWK lacks the jumper? If the latter, just drop the MMC bits out :)
I can't ;) this was an explicit requirement.
As for the devkit8000 boot problem, I have BSS set up close to the top of the RAM. Probably that's the reason I don't see any problems.
Unfortunately, I can't recall why I had moved BSS... It clashed with something but I don't remember the details.
Regards, Ilya.
On Tue, Dec 13, 2011 at 12:44 PM, Ilya Yanok yanok@emcraft.com wrote:
Hi Tom,
On 13.12.2011 23:30, Tom Rini wrote:
+#define CONFIG_SYS_TEXT_BASE 0x80008000
[snip]
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
You're able to have CONFIG_SYS_TEXT_BASE that low and not have the corruption problem devkit8000 had?
No, I can't see any problems. I have to say I can't do _real_ MMC boot, as my board lacks the required jumper, so I'm testing it but starting SPL from NAND, rewriting omap3_boot_device to be MMC with BDI and running it further. It reads u-boot.img from MMC and starts it without any problem.
Well, is it just your board that's missing the jumper, or the MCX HTWK lacks the jumper? If the latter, just drop the MMC bits out :)
I can't ;) this was an explicit requirement.
As for the devkit8000 boot problem, I have BSS set up close to the top of the RAM. Probably that's the reason I don't see any problems.
Unfortunately, I can't recall why I had moved BSS... It clashed with something but I don't remember the details.
OK. I _want_ to put this into my /next branch (and thanks for working over all of the issues that've popped up since you first posted the series) but I also would like to try and keep differences for difference sake out of the SPL implementations since I know other folks are starting to look at the code and port their custom boards or in-tree boards and I'm sure they'll go "why does X place things here and Y there and my board isn't working?". So if you can try and recall what the clash was (and we can comment it, or maybe it was the FAT thing :)) I'd really appreciate it.
Hi Tom,
On 14.12.2011 01:47, Tom Rini wrote:
As for the devkit8000 boot problem, I have BSS set up close to the top of the RAM. Probably that's the reason I don't see any problems.
Unfortunately, I can't recall why I had moved BSS... It clashed with something but I don't remember the details.
OK. I _want_ to put this into my /next branch (and thanks for working over all of the issues that've popped up since you first posted the series) but I also would like to try and keep differences for difference sake out of the SPL implementations since I know other folks are starting to look at the code and port their custom boards or in-tree boards and I'm sure they'll go "why does X place things here and Y there and my board isn't working?". So if you can try and recall what the clash was (and we can comment it, or maybe it was the FAT thing :)) I'd really appreciate it.
I see. I've looked through my old commit histories but haven't found anything interesting. All I can say that it wasn't FAT cause I've changed BSS location before I've even started playing with MMC SPL.
Probably I just didn't want to change TEXT_BASE... Ah, now I recall. I tried to make SPL working without breaking the board, so I loaded SPL to SRAM with BDI and tried to make it work with the u-boot.bin I had in NAND. That's why I had to preserve TEXT_BASE and move BSS instead. So that seems unrelated to the problem you observe on devkit8000...
Regards, Ilya.
On Tue, Dec 13, 2011 at 5:06 PM, Ilya Yanok yanok@emcraft.com wrote:
Hi Tom,
On 14.12.2011 01:47, Tom Rini wrote:
As for the devkit8000 boot problem, I have BSS set up close to the top of the RAM. Probably that's the reason I don't see any problems.
Unfortunately, I can't recall why I had moved BSS... It clashed with something but I don't remember the details.
OK. I _want_ to put this into my /next branch (and thanks for working over all of the issues that've popped up since you first posted the series) but I also would like to try and keep differences for difference sake out of the SPL implementations since I know other folks are starting to look at the code and port their custom boards or in-tree boards and I'm sure they'll go "why does X place things here and Y there and my board isn't working?". So if you can try and recall what the clash was (and we can comment it, or maybe it was the FAT thing :)) I'd really appreciate it.
I see. I've looked through my old commit histories but haven't found anything interesting. All I can say that it wasn't FAT cause I've changed BSS location before I've even started playing with MMC SPL.
Probably I just didn't want to change TEXT_BASE... Ah, now I recall. I tried to make SPL working without breaking the board, so I loaded SPL to SRAM with BDI and tried to make it work with the u-boot.bin I had in NAND. That's why I had to preserve TEXT_BASE and move BSS instead. So that seems unrelated to the problem you observe on devkit8000...
Ah-ha! Whenever I hit that point I always went "oh, right, I forgot to adjust CONFIG_SYS_TEXT_BASE" :) So, would you mind either adding a comment that says in effect what you've got here "Keep at ... so that we can still be loaded by non-SPL loaders" or whack everything around and match the am3517 crane/evm and the omap3 boards? Thanks!
Hi Tom,
On 14.12.2011 06:48, Tom Rini wrote:
Probably I just didn't want to change TEXT_BASE... Ah, now I recall. I tried to make SPL working without breaking the board, so I loaded SPL to SRAM with BDI and tried to make it work with the u-boot.bin I had in NAND. That's why I had to preserve TEXT_BASE and move BSS instead. So that seems unrelated to the problem you observe on devkit8000...
Ah-ha! Whenever I hit that point I always went "oh, right, I forgot to adjust CONFIG_SYS_TEXT_BASE" :) So, would you mind either adding a comment that says in effect what you've got here "Keep at ... so that we can still be loaded by non-SPL loaders" or whack everything around and match the am3517 crane/evm and the omap3 boards? Thanks!
Ok, I put a comment about TEXT_BASE and SPL_{MALLOC,BSS}.
Regards, Ilya.
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Signed-off-by: Ilya Yanok yanok@emcraft.com
--- I'm sorry for non-consistent version history, I will give links to my previous posts along with version numbers.
The last ("Support for HTKW mcx") series: Changes from V4 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120148
- board_mmc_init return value fixed - machine id added locally - CONFIG_SYS_NAND_U_BOOT_SIZE removed
Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118530
- Comment for misc_init_r function fixed - Added check for gpio_request return value. - Removed #if defined(CONFIG_GENERIC_MMC) around board_mmc_init - CONFIG_USE_IRQ and related stuff removed from config - CONFIG_OMAP3_MICRON_DDR removed - CONFIG_SYS_MAXRAGS changed 32 -> 16 - Incorrect multiline comments (/*--- ones) fixed - CONFIG_SPL_MAX_SIZE rewritten 0xB400 -> (45 << 10) - CONFIG_SPL_NAND_WORKSPACE removed
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/116548
- None
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/115026
- Calls to gpio_set_value after gpio_direction_output removed - Minor style problem (tab instead of space) fixed
SPL series: Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112892
- OMAP EHCI support enabled in config - MMC SPL support enabled in config
"DaVinci EMAC and HTKW mcx support" series: Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112884
- NAND SPL support enabled in config
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112317
- removed dead code from board/htkw/mcx/Makefile as Mike suggested - removed EMAC reset (now done in generic cpu_eth_init()) - removed some unsuned defines from configuration header
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111197
- various style fixes to make checkpatch (almost) happy - FSF address removed from GPL comments - CONFIG_SYS_TEXT_BASE moved to configuration header, config.mk droped - CONFIG_MACH_TYPE is used instead of setting mach type from board code - i2c_init removed from misc_init_r - cpu_eth_init removed (added to generic place by another patch) - CONTROL_PADCONF defines removed - Fixed boolean config options not to have a value - CONFIG_MUSB_* and related defines removed
MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 90 +++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 371 ++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 912 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.h
diff --git a/MAINTAINERS b/MAINTAINERS index a56ca10..c7fcc10 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -903,6 +903,10 @@ Richard Woodruff r-woodruff2@ti.com
omap2420h4 ARM1136EJS
+Ilya Yanok yanok@emcraft.com + + mcx ARM ARMV7 (AM35x SoC) + Syed Mohammed Khasim sm.khasim@gmail.com Sughosh Ganu urwithsughosh@gmail.com
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile new file mode 100644 index 0000000..4c8db10 --- /dev/null +++ b/board/htkw/mcx/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c new file mode 100644 index 0000000..43fb9ed --- /dev/null +++ b/board/htkw/mcx/mcx.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on ti/evm/evm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/omap_gpio.h> +#include "errno.h" +#include <i2c.h> +#include "mcx.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: late init. + */ +int misc_init_r(void) +{ + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_MCX(); +} + +#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0); +} +#endif + +#ifdef CONFIG_USB_EHCI_OMAP +#define USB_HOST_PWR_EN 132 +int board_usb_init(void) +{ + if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) { + puts("Failed to get USB_HOST_PWR_EN pin\n"); + return -ENODEV; + } + gpio_direction_output(USB_HOST_PWR_EN, 1); + + return 0; +} +#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h new file mode 100644 index 0000000..d675a48 --- /dev/null +++ b/board/htkw/mcx/mcx.h @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on ti/evm/evm.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "HTKW mcx Board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_MCX() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly0*/\ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly1*/\ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \ + /* GPIO_43 LCD buffer enable */ \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \ + /* GPIO_57 TS_PenIRQn */\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \ + /* GPIO_58 ETHERNET RESET */\ + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \ + /* GPIO_61 SD-CARD CD */ \ + MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \ + /* GPIO_62 Nand write protect, keep enabled */ \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ + /* GPIO_65 SD-CARD WP */\ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \ + /* GPIO_131 LCD Enable */ \ + MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \ + /* GPIO_132 USB host Enable */\ + MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \ + /* GPIO_133 HDMI PD */\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \ + /* GPIO_152 USB phy2 reset */\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \ + /* GPIO_153 */\ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \ + /* GPIO_154 USB phy1 reset */\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \ + /* GPIO_155 TS_BUSY */\ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat7 */\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat4 */\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat5 */\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat6 */\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat3 */\ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ + /* HDQ */\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \ + /* SYS_nRESWARM */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\ + /* ETK (ES2 onwards) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_stp */ \ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_clk */\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + +#endif diff --git a/boards.cfg b/boards.cfg index 1e5b3e0..ac606d2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -210,6 +210,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 omap5_evm arm armv7 omap5_evm ti omap5 diff --git a/include/configs/mcx.h b/include/configs/mcx.h new file mode 100644 index 0000000..9c2069c --- /dev/null +++ b/include/configs/mcx.h @@ -0,0 +1,371 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on omap3_evm_config.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */ + +#define MACH_TYPE_MCX 3656 +#define CONFIG_MACH_TYPE MACH_TYPE_MCX + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +#define CONFIG_OF_LIBFDT +#define CONFIG_FIT + +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/* + * DDR related + */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C + +/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "mcx # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/* + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ + 48, 49, 50, 51, 52, 53, 54, 55,\ + 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * ethernet support + * + */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +#endif /* __CONFIG_H */
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Signed-off-by: Ilya Yanok yanok@emcraft.com
--- I'm sorry for non-consistent version history, I will give links to my previous posts along with version numbers.
The last ("Support for HTKW mcx") series: Changes from V5 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120254
- added comments on CONFIG_SYS_TEXT_BASE and SPL_{MALLOC,BSS}
Changes from V4 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120148
- board_mmc_init return value fixed - machine id added locally - CONFIG_SYS_NAND_U_BOOT_SIZE removed
Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118530
- Comment for misc_init_r function fixed - Added check for gpio_request return value. - Removed #if defined(CONFIG_GENERIC_MMC) around board_mmc_init - CONFIG_USE_IRQ and related stuff removed from config - CONFIG_OMAP3_MICRON_DDR removed - CONFIG_SYS_MAXRAGS changed 32 -> 16 - Incorrect multiline comments (/*--- ones) fixed - CONFIG_SPL_MAX_SIZE rewritten 0xB400 -> (45 << 10) - CONFIG_SPL_NAND_WORKSPACE removed
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/116548
- None
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/115026
- Calls to gpio_set_value after gpio_direction_output removed - Minor style problem (tab instead of space) fixed
SPL series: Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112892
- OMAP EHCI support enabled in config - MMC SPL support enabled in config
"DaVinci EMAC and HTKW mcx support" series: Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112884
- NAND SPL support enabled in config
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112317
- removed dead code from board/htkw/mcx/Makefile as Mike suggested - removed EMAC reset (now done in generic cpu_eth_init()) - removed some unsuned defines from configuration header
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111197
- various style fixes to make checkpatch (almost) happy - FSF address removed from GPL comments - CONFIG_SYS_TEXT_BASE moved to configuration header, config.mk droped - CONFIG_MACH_TYPE is used instead of setting mach type from board code - i2c_init removed from misc_init_r - cpu_eth_init removed (added to generic place by another patch) - CONTROL_PADCONF defines removed - Fixed boolean config options not to have a value - CONFIG_MUSB_* and related defines removed
MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 90 +++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 376 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 917 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.h
diff --git a/MAINTAINERS b/MAINTAINERS index a56ca10..c7fcc10 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -903,6 +903,10 @@ Richard Woodruff r-woodruff2@ti.com
omap2420h4 ARM1136EJS
+Ilya Yanok yanok@emcraft.com + + mcx ARM ARMV7 (AM35x SoC) + Syed Mohammed Khasim sm.khasim@gmail.com Sughosh Ganu urwithsughosh@gmail.com
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile new file mode 100644 index 0000000..4c8db10 --- /dev/null +++ b/board/htkw/mcx/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c new file mode 100644 index 0000000..43fb9ed --- /dev/null +++ b/board/htkw/mcx/mcx.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on ti/evm/evm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/omap_gpio.h> +#include "errno.h" +#include <i2c.h> +#include "mcx.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: late init. + */ +int misc_init_r(void) +{ + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_MCX(); +} + +#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0); +} +#endif + +#ifdef CONFIG_USB_EHCI_OMAP +#define USB_HOST_PWR_EN 132 +int board_usb_init(void) +{ + if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) { + puts("Failed to get USB_HOST_PWR_EN pin\n"); + return -ENODEV; + } + gpio_direction_output(USB_HOST_PWR_EN, 1); + + return 0; +} +#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h new file mode 100644 index 0000000..d675a48 --- /dev/null +++ b/board/htkw/mcx/mcx.h @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on ti/evm/evm.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "HTKW mcx Board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_MCX() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly0*/\ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly1*/\ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \ + /* GPIO_43 LCD buffer enable */ \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \ + /* GPIO_57 TS_PenIRQn */\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \ + /* GPIO_58 ETHERNET RESET */\ + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \ + /* GPIO_61 SD-CARD CD */ \ + MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \ + /* GPIO_62 Nand write protect, keep enabled */ \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ + /* GPIO_65 SD-CARD WP */\ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \ + /* GPIO_131 LCD Enable */ \ + MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \ + /* GPIO_132 USB host Enable */\ + MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \ + /* GPIO_133 HDMI PD */\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \ + /* GPIO_152 USB phy2 reset */\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \ + /* GPIO_153 */\ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \ + /* GPIO_154 USB phy1 reset */\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \ + /* GPIO_155 TS_BUSY */\ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat7 */\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat4 */\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat5 */\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat6 */\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat3 */\ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ + /* HDQ */\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \ + /* SYS_nRESWARM */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\ + /* ETK (ES2 onwards) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_stp */ \ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_clk */\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + +#endif diff --git a/boards.cfg b/boards.cfg index 1e5b3e0..ac606d2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -210,6 +210,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 omap5_evm arm armv7 omap5_evm ti omap5 diff --git a/include/configs/mcx.h b/include/configs/mcx.h new file mode 100644 index 0000000..cf58257 --- /dev/null +++ b/include/configs/mcx.h @@ -0,0 +1,376 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on omap3_evm_config.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */ + +#define MACH_TYPE_MCX 3656 +#define CONFIG_MACH_TYPE MACH_TYPE_MCX + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +#define CONFIG_OF_LIBFDT +#define CONFIG_FIT + +/* + * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader + * and older u-boot.bin with the new U-Boot SPL. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/* + * DDR related + */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C + +/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "mcx # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/* + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ + 48, 49, 50, 51, 52, 53, 54, 55,\ + 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * ethernet support + * + */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +#endif /* __CONFIG_H */
Hi Tom,
any news on this?
I'm getting a little bit jealous ;) Stefano's TAM3517 patches (which were originally based on these series) are already accepted while mine are not...
Regards, Ilya.
On 14.12.2011 20:05, Ilya Yanok wrote:
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Signed-off-by: Ilya Yanok yanok@emcraft.com
I'm sorry for non-consistent version history, I will give links to my previous posts along with version numbers.
The last ("Support for HTKW mcx") series: Changes from V5 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120254
- added comments on CONFIG_SYS_TEXT_BASE and SPL_{MALLOC,BSS}
Changes from V4 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120148
- board_mmc_init return value fixed
- machine id added locally
- CONFIG_SYS_NAND_U_BOOT_SIZE removed
Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118530
- Comment for misc_init_r function fixed
- Added check for gpio_request return value.
- Removed #if defined(CONFIG_GENERIC_MMC) around board_mmc_init
- CONFIG_USE_IRQ and related stuff removed from config
- CONFIG_OMAP3_MICRON_DDR removed
- CONFIG_SYS_MAXRAGS changed 32 -> 16
- Incorrect multiline comments (/*--- ones) fixed
- CONFIG_SPL_MAX_SIZE rewritten 0xB400 -> (45 << 10)
- CONFIG_SPL_NAND_WORKSPACE removed
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/116548
- None
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/115026
- Calls to gpio_set_value after gpio_direction_output removed
- Minor style problem (tab instead of space) fixed
SPL series: Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112892
- OMAP EHCI support enabled in config
- MMC SPL support enabled in config
"DaVinci EMAC and HTKW mcx support" series: Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112884
- NAND SPL support enabled in config
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112317
- removed dead code from board/htkw/mcx/Makefile as Mike suggested
- removed EMAC reset (now done in generic cpu_eth_init())
- removed some unsuned defines from configuration header
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111197
- various style fixes to make checkpatch (almost) happy
- FSF address removed from GPL comments
- CONFIG_SYS_TEXT_BASE moved to configuration header, config.mk droped
- CONFIG_MACH_TYPE is used instead of setting mach type from board code
- i2c_init removed from misc_init_r
- cpu_eth_init removed (added to generic place by another patch)
- CONTROL_PADCONF defines removed
- Fixed boolean config options not to have a value
- CONFIG_MUSB_* and related defines removed
MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 90 +++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 376 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 917 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.h
diff --git a/MAINTAINERS b/MAINTAINERS index a56ca10..c7fcc10 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -903,6 +903,10 @@ Richard Woodruff r-woodruff2@ti.com
omap2420h4 ARM1136EJS
+Ilya Yanok yanok@emcraft.com
- mcx ARM ARMV7 (AM35x SoC)
Syed Mohammed Khasim sm.khasim@gmail.com Sughosh Ganu urwithsughosh@gmail.com
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile new file mode 100644 index 0000000..4c8db10 --- /dev/null +++ b/board/htkw/mcx/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +#
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o
+SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS))
+$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c new file mode 100644 index 0000000..43fb9ed --- /dev/null +++ b/board/htkw/mcx/mcx.c @@ -0,0 +1,90 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on ti/evm/evm.c
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/omap_gpio.h> +#include "errno.h" +#include <i2c.h> +#include "mcx.h"
+DECLARE_GLOBAL_DATA_PTR;
+/*
- Routine: board_init
- Description: Early hardware init.
- */
+int board_init(void) +{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
- return 0;
+}
+/*
- Routine: misc_init_r
- Description: late init.
- */
+int misc_init_r(void) +{
- dieid_num_r();
- return 0;
+}
+/*
- Routine: set_muxconf_regs
- Description: Setting up the configuration Mux registers specific to the
hardware. Many pins need to be moved from protect to primary
mode.- */
+void set_muxconf_regs(void) +{
- MUX_MCX();
+}
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{
- return omap_mmc_init(0);
+} +#endif
+#ifdef CONFIG_USB_EHCI_OMAP +#define USB_HOST_PWR_EN 132 +int board_usb_init(void) +{
- if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) {
puts("Failed to get USB_HOST_PWR_EN pin\n");return -ENODEV;- }
- gpio_direction_output(USB_HOST_PWR_EN, 1);
- return 0;
+} +#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h new file mode 100644 index 0000000..d675a48 --- /dev/null +++ b/board/htkw/mcx/mcx.h @@ -0,0 +1,408 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on ti/evm/evm.h
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_
+const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "HTKW mcx Board",
- "NAND",
+};
+/*
- IEN - Input Enable
- IDIS - Input Disable
- PTD - Pull type Down
- PTU - Pull type Up
- DIS - Pull type selection is inactive
- EN - Pull type selection is active
- M0 - Mode 0
- The commented string gives the final mux configuration for that pin
- */
+#define MUX_MCX() \
- /* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_CKE0), (M0)) \
- MUX_VAL(CP(SDRC_CKE1), (M0)) \
- MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly0*/\- MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly1*/\- /* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \
/* GPIO_43 LCD buffer enable */ \- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \
/* GPIO_57 TS_PenIRQn */\- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \
/* GPIO_58 ETHERNET RESET */\- MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \
/* GPIO_61 SD-CARD CD */ \- MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
/* GPIO_62 Nand write protect, keep enabled */ \- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
/* GPIO_65 SD-CARD WP */\- /* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
- /* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \
- /* MMC */\
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \
/* GPIO_131 LCD Enable */ \- MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \
/* GPIO_132 USB host Enable */\- MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \
/* GPIO_133 HDMI PD */\- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\
- /* McBSP */\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\
- \
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\
- \
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \
/* GPIO_152 USB phy2 reset */\- MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \
/* GPIO_153 */\- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \
/* GPIO_154 USB phy1 reset */\- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \
/* GPIO_155 TS_BUSY */\- /* UART */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
- /* I2C */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
- /* McSPI */\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat7 */\- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat4 */\- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat5 */\- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat6 */\- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat3 */\- /* CCDC */\
- MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \
- /* RMII */\
- MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
- MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
- MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
- MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
- /* HECC */\
- MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \
- /* HSUSB */\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
- /* HDQ */\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
- /* Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \
/* SYS_nRESWARM */\- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \
- \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
- /* JTAG */\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\
- /* ETK (ES2 onwards) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_stp */ \- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_clk */\- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
- /* Die to Die */\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
+#endif diff --git a/boards.cfg b/boards.cfg index 1e5b3e0..ac606d2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -210,6 +210,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 omap5_evm arm armv7 omap5_evm ti omap5 diff --git a/include/configs/mcx.h b/include/configs/mcx.h new file mode 100644 index 0000000..cf58257 --- /dev/null +++ b/include/configs/mcx.h @@ -0,0 +1,376 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on omap3_evm_config.h
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+/*
- High Level Configuration Options
- */
+#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */
+#define MACH_TYPE_MCX 3656 +#define CONFIG_MACH_TYPE MACH_TYPE_MCX
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
+#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h>
+#define CONFIG_OF_LIBFDT +#define CONFIG_FIT
+/*
- Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
- and older u-boot.bin with the new U-Boot SPL.
- */
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+/*
- Display CPU and Board information
- */
+#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO
+/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1)
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG
+/*
- Size of malloc() pool
- */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/*
- DDR related
- */
+#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
+/*
- Hardware drivers
- */
+/*
- NS16550 Configuration
- */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+/*
- select serial console configuration
- */
+#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */
+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}+#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION
+/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+/* commands to include */ +#include <config_cmd_default.h>
+#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C
+/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/*
- Board NAND Info.
- */
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access *//* nand at CS0 */+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
+/* Environment information */ +#define CONFIG_BOOTDELAY 10
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
- "mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk0p2 rw " \"rootfstype=ext3 rootwait\0" \- "nandargs=setenv bootargs console=${console} " \
"root=/dev/mtdblock4 rw " \"rootfstype=jffs2\0" \- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \"bootm ${loadaddr}\0" \- "nandboot=echo Booting from nand ...; " \
"run nandargs; " \"nand read ${loadaddr} 280000 400000; " \"bootm ${loadaddr}\0" \+#define CONFIG_BOOTCOMMAND \
- "if mmc init; then " \
"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loaduimage; then " \"run mmcboot; " \"else run nandboot; " \"fi; " \"fi; " \- "else run nandboot; fi"
+#define CONFIG_AUTO_COMPLETE +/*
- Miscellaneous configurable options
- */
+#define V_PROMPT "mcx # "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_MAXARGS 16 /* max number of command */
/* args */+/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */+/*
- AM3517 has 12 GP timers, they can be driven by the system clock
- (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- This rate is divided by a local divisor.
- */
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000
+/*
- Stack sizes
- The stack sizes are set up in start.S using the settings below
- */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+/*
- Physical Memory Map
- */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+/*
- FLASH and environment organization
- */
+/* **** PISMO SUPPORT *** */
+/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+/*
- CFI FLASH driver setup
- */
+/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)+#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \GENERATED_GBL_DATA_SIZE)+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
48, 49, 50, 51, 52, 53, 54, 55,\56, 57, 58, 59, 60, 61, 62, 63}+#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
CONFIG_SYS_NAND_ECCSIZE)+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
CONFIG_SYS_NAND_ECCSTEPS)+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/*
- ethernet support
- */
+#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif
+#endif /* __CONFIG_H */
On Mon, Dec 19, 2011 at 3:55 PM, Ilya Yanok yanok@emcraft.com wrote:
Hi Tom,
any news on this?
I'm getting a little bit jealous ;) Stefano's TAM3517 patches (which were originally based on these series) are already accepted while mine are not...
1/2 is held up on USB review. If you want to split out the USB part of your board until Remy can comment on it I'd be happy to put this into u-boot-ti/next.
Regards, Ilya.
On 14.12.2011 20:05, Ilya Yanok wrote:
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Signed-off-by: Ilya Yanok yanok@emcraft.com
I'm sorry for non-consistent version history, I will give links to my previous posts along with version numbers.
The last ("Support for HTKW mcx") series: Changes from V5 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120254
- added comments on CONFIG_SYS_TEXT_BASE and SPL_{MALLOC,BSS}
Changes from V4 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120148
- board_mmc_init return value fixed - machine id added locally - CONFIG_SYS_NAND_U_BOOT_SIZE removed
Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118530
- Comment for misc_init_r function fixed - Added check for gpio_request return value. - Removed #if defined(CONFIG_GENERIC_MMC) around board_mmc_init - CONFIG_USE_IRQ and related stuff removed from config - CONFIG_OMAP3_MICRON_DDR removed - CONFIG_SYS_MAXRAGS changed 32 -> 16 - Incorrect multiline comments (/*--- ones) fixed - CONFIG_SPL_MAX_SIZE rewritten 0xB400 -> (45 << 10) - CONFIG_SPL_NAND_WORKSPACE removed
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/116548
- None
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/115026
- Calls to gpio_set_value after gpio_direction_output removed - Minor style problem (tab instead of space) fixed
SPL series: Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112892
- OMAP EHCI support enabled in config - MMC SPL support enabled in config
"DaVinci EMAC and HTKW mcx support" series: Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112884
- NAND SPL support enabled in config
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112317
- removed dead code from board/htkw/mcx/Makefile as Mike suggested - removed EMAC reset (now done in generic cpu_eth_init()) - removed some unsuned defines from configuration header
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111197
- various style fixes to make checkpatch (almost) happy - FSF address removed from GPL comments - CONFIG_SYS_TEXT_BASE moved to configuration header, config.mk droped - CONFIG_MACH_TYPE is used instead of setting mach type from board code - i2c_init removed from misc_init_r - cpu_eth_init removed (added to generic place by another patch) - CONTROL_PADCONF defines removed - Fixed boolean config options not to have a value - CONFIG_MUSB_* and related defines removed
MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 90 +++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 376 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 917 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.h
diff --git a/MAINTAINERS b/MAINTAINERS index a56ca10..c7fcc10 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -903,6 +903,10 @@ Richard Woodruff r-woodruff2@ti.com
omap2420h4 ARM1136EJS
+Ilya Yanok yanok@emcraft.com
- mcx ARM ARMV7 (AM35x SoC)
Syed Mohammed Khasim sm.khasim@gmail.com Sughosh Ganu urwithsughosh@gmail.com
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile new file mode 100644 index 0000000..4c8db10 --- /dev/null +++ b/board/htkw/mcx/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +#
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o
+SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS))
+$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c new file mode 100644 index 0000000..43fb9ed --- /dev/null +++ b/board/htkw/mcx/mcx.c @@ -0,0 +1,90 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on ti/evm/evm.c
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/omap_gpio.h> +#include "errno.h" +#include <i2c.h> +#include "mcx.h"
+DECLARE_GLOBAL_DATA_PTR;
+/*
- Routine: board_init
- Description: Early hardware init.
- */
+int board_init(void) +{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
- return 0;
+}
+/*
- Routine: misc_init_r
- Description: late init.
- */
+int misc_init_r(void) +{
- dieid_num_r();
- return 0;
+}
+/*
- Routine: set_muxconf_regs
- Description: Setting up the configuration Mux registers specific to the
- hardware. Many pins need to be moved from protect to primary
- mode.
- */
+void set_muxconf_regs(void) +{
- MUX_MCX();
+}
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{
- return omap_mmc_init(0);
+} +#endif
+#ifdef CONFIG_USB_EHCI_OMAP +#define USB_HOST_PWR_EN 132 +int board_usb_init(void) +{
- if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) {
- puts("Failed to get USB_HOST_PWR_EN pin\n");
- return -ENODEV;
- }
- gpio_direction_output(USB_HOST_PWR_EN, 1);
- return 0;
+} +#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h new file mode 100644 index 0000000..d675a48 --- /dev/null +++ b/board/htkw/mcx/mcx.h @@ -0,0 +1,408 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on ti/evm/evm.h
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_
+const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "HTKW mcx Board",
- "NAND",
+};
+/*
- IEN - Input Enable
- IDIS - Input Disable
- PTD - Pull type Down
- PTU - Pull type Up
- DIS - Pull type selection is inactive
- EN - Pull type selection is active
- M0 - Mode 0
- The commented string gives the final mux configuration for that pin
- */
+#define MUX_MCX() \
- /* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_CKE0), (M0)) \
- MUX_VAL(CP(SDRC_CKE1), (M0)) \
- MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
- /*sdrc_strben_dly0*/\
- MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
- /*sdrc_strben_dly1*/\
- /* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \
- /* GPIO_43 LCD buffer enable */ \
- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \
- /* GPIO_57 TS_PenIRQn */\
- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \
- /* GPIO_58 ETHERNET RESET */\
- MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \
- /* GPIO_61 SD-CARD CD */ \
- MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
- /* GPIO_62 Nand write protect, keep enabled */ \
- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
- /* GPIO_65 SD-CARD WP */\
- /* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
- /* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \
- /* MMC */\
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \
- /* GPIO_131 LCD Enable */ \
- MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \
- /* GPIO_132 USB host Enable */\
- MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \
- /* GPIO_133 HDMI PD */\
- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\
- /* McBSP */\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\
- \
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\
- \
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \
- /* GPIO_152 USB phy2 reset */\
- MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \
- /* GPIO_153 */\
- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \
- /* GPIO_154 USB phy1 reset */\
- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \
- /* GPIO_155 TS_BUSY */\
- /* UART */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
- /* I2C */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
- /* McSPI */\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
- /* HSUSB2_dat7 */\
- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
- /* HSUSB2_dat4 */\
- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
- /* HSUSB2_dat5 */\
- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
- /* HSUSB2_dat6 */\
- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
- /* HSUSB2_dat3 */\
- /* CCDC */\
- MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \
- /* RMII */\
- MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
- MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
- MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
- MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
- /* HECC */\
- MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \
- /* HSUSB */\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
- /* HDQ */\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
- /* Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \
- /* SYS_nRESWARM */\
- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \
- \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
- /* JTAG */\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\
- /* ETK (ES2 onwards) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
- /* hsusb1_stp */ \
- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
- /* hsusb1_clk */\
- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
- /* Die to Die */\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
+#endif diff --git a/boards.cfg b/boards.cfg index 1e5b3e0..ac606d2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -210,6 +210,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 omap5_evm arm armv7 omap5_evm ti omap5 diff --git a/include/configs/mcx.h b/include/configs/mcx.h new file mode 100644 index 0000000..cf58257 --- /dev/null +++ b/include/configs/mcx.h @@ -0,0 +1,376 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on omap3_evm_config.h
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+/*
- High Level Configuration Options
- */
+#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */
+#define MACH_TYPE_MCX 3656 +#define CONFIG_MACH_TYPE MACH_TYPE_MCX
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
+#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h>
+#define CONFIG_OF_LIBFDT +#define CONFIG_FIT
+/*
- Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
- and older u-boot.bin with the new U-Boot SPL.
- */
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+/*
- Display CPU and Board information
- */
+#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO
+/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1)
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG
+/*
- Size of malloc() pool
- */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/*
- DDR related
- */
+#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
+/*
- Hardware drivers
- */
+/*
- NS16550 Configuration
- */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+/*
- select serial console configuration
- */
+#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */
+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
+#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION
+/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+/* commands to include */ +#include <config_cmd_default.h>
+#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C
+/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/*
- Board NAND Info.
- */
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
- /* to access nand */
+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
- /* to access */
- /* nand at CS0 */
+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
- /* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
+/* Environment information */ +#define CONFIG_BOOTDELAY 10
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext3 rootwait\0" \
- "nandargs=setenv bootargs console=${console} " \
- "root=/dev/mtdblock4 rw " \
- "rootfstype=jffs2\0" \
- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source ${loadaddr}\0" \
- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 280000 400000; " \
- "bootm ${loadaddr}\0" \
+#define CONFIG_BOOTCOMMAND \
- "if mmc init; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loaduimage; then " \
- "run mmcboot; " \
- "else run nandboot; " \
- "fi; " \
- "fi; " \
- "else run nandboot; fi"
+#define CONFIG_AUTO_COMPLETE +/*
- Miscellaneous configurable options
- */
+#define V_PROMPT "mcx # "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
- sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command */
- /* args */
+/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
- 0x01F00000) /* 31MB */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
- /* address */
+/*
- AM3517 has 12 GP timers, they can be driven by the system clock
- (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- This rate is divided by a local divisor.
- */
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000
+/*
- Stack sizes
- The stack sizes are set up in start.S using the settings below
- */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+/*
- Physical Memory Map
- */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+/*
- FLASH and environment organization
- */
+/* **** PISMO SUPPORT *** */
+/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+/*
- CFI FLASH driver setup
- */
+/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
- CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
- CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
- 48, 49, 50, 51, 52, 53, 54, 55,\
- 56, 57, 58, 59, 60, 61, 62, 63}
+#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
- CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/*
- ethernet support
- */
+#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif
+#endif /* __CONFIG_H */
Hi Tom,
On 20.12.2011 02:56, Tom Rini wrote:
I'm getting a little bit jealous ;) Stefano's TAM3517 patches (which were originally based on these series) are already accepted while mine are not...
1/2 is held up on USB review. If you want to split out the USB part of your board until Remy can comment on it I'd be happy to put this into u-boot-ti/next.
Well, let's wait for review results. BTW, TAM3517 actually uses the same ehci-omap driver from 1/2 ;)
Regards, Ilya.
Hi all,
On Mon, 19 Dec 2011 15:56:12 -0700 Tom Rini tom.rini@gmail.com wrote:
On Mon, Dec 19, 2011 at 3:55 PM, Ilya Yanok yanok@emcraft.com wrote:
Hi Tom,
any news on this?
I'm getting a little bit jealous ;) Stefano's TAM3517 patches (which were originally based on these series) are already accepted while mine are not...
1/2 is held up on USB review. If you want to split out the USB part of your board until Remy can comment on it I'd be happy to put this into u-boot-ti/next.
I'm not sure whether Remy is aware of this patch. It is delegated to Remy on patchwork, but the state of the patch is "New".
Ilya, did you Cc Remy when sending v4 1/2 patch? Probably it would make sense to ping Remy.
Anatolij
Hi Anatolij,
On 20.12.2011 03:12, Anatolij Gustschin wrote:
1/2 is held up on USB review. If you want to split out the USB part of your board until Remy can comment on it I'd be happy to put this into u-boot-ti/next.
I'm not sure whether Remy is aware of this patch. It is delegated to Remy on patchwork, but the state of the patch is "New".
Ilya, did you Cc Remy when sending v4 1/2 patch? Probably it would make sense to ping Remy.
Yes, this makes sense. Will do.
Regards, Ilya.
From: Ilya Yanok yanok@emcraft.com
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Signed-off-by: Ilya Yanok yanok@emcraft.com Signed-off-by: Stefano Babic sbabic@denx.de CC: Tom Rini tom.rini@gmail.com Cc: Detlev Zundel dzu@denx.de --- Changes from V6: - rebased on current u-boot-ti - applied and tested on top of EHCI Gavindraj's patches - uses ULPI framework
Changes from V5 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120254
- added comments on CONFIG_SYS_TEXT_BASE and SPL_{MALLOC,BSS}
Changes from V4 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120148
- board_mmc_init return value fixed - machine id added locally - CONFIG_SYS_NAND_U_BOOT_SIZE removed
Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118530
- Comment for misc_init_r function fixed - Added check for gpio_request return value. - Removed #if defined(CONFIG_GENERIC_MMC) around board_mmc_init - CONFIG_USE_IRQ and related stuff removed from config - CONFIG_OMAP3_MICRON_DDR removed - CONFIG_SYS_MAXRAGS changed 32 -> 16 - Incorrect multiline comments (/*--- ones) fixed - CONFIG_SPL_MAX_SIZE rewritten 0xB400 -> (45 << 10) - CONFIG_SPL_NAND_WORKSPACE removed
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/116548
- None
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/115026
- Calls to gpio_set_value after gpio_direction_output removed - Minor style problem (tab instead of space) fixed
SPL series: Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112892
- OMAP EHCI support enabled in config - MMC SPL support enabled in config
"DaVinci EMAC and HTKW mcx support" series: Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112884
- NAND SPL support enabled in config
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112317
- removed dead code from board/htkw/mcx/Makefile as Mike suggested - removed EMAC reset (now done in generic cpu_eth_init()) - removed some unsuned defines from configuration header
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111197
- various style fixes to make checkpatch (almost) happy - FSF address removed from GPL comments - CONFIG_SYS_TEXT_BASE moved to configuration header, config.mk droped - CONFIG_MACH_TYPE is used instead of setting mach type from board code - i2c_init removed from misc_init_r - cpu_eth_init removed (added to generic place by another patch) - CONTROL_PADCONF defines removed - Fixed boolean config options not to have a value - CONFIG_MUSB_* and related defines removed
MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 122 ++++++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 378 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 951 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.h
diff --git a/MAINTAINERS b/MAINTAINERS index a8e56bb..7e52f50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -920,6 +920,10 @@ Richard Woodruff r-woodruff2@ti.com
omap2420h4 ARM1136EJS
+Ilya Yanok yanok@emcraft.com + + mcx ARM ARMV7 (AM35x SoC) + Syed Mohammed Khasim sm.khasim@gmail.com Sughosh Ganu urwithsughosh@gmail.com
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile new file mode 100644 index 0000000..4c8db10 --- /dev/null +++ b/board/htkw/mcx/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c new file mode 100644 index 0000000..dcc8707 --- /dev/null +++ b/board/htkw/mcx/mcx.c @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on ti/evm/evm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/omap_gpio.h> +#include "errno.h" +#include <i2c.h> +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/ehci-omap.h> +#endif +#include "mcx.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USB_EHCI +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_EHCI_PORT_MODE_PHY, +}; + +int ehci_hcd_init(void) +{ + int ret; + + ret = omap_ehci_hcd_init(&usbhs_bdata); + if (ret < 0) + return ret; + + return 0; +} + +int ehci_hcd_stop(void) +{ + int ret; + + ret = omap_ehci_hcd_stop(); + return ret; +} +#endif + + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: late init. + */ +int misc_init_r(void) +{ + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_MCX(); +} + +#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0); +} +#endif + +#ifdef CONFIG_USB_EHCI_OMAP +#define USB_HOST_PWR_EN 132 +int board_usb_init(void) +{ + if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) { + puts("Failed to get USB_HOST_PWR_EN pin\n"); + return -ENODEV; + } + gpio_direction_output(USB_HOST_PWR_EN, 1); + + return 0; +} +#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h new file mode 100644 index 0000000..d675a48 --- /dev/null +++ b/board/htkw/mcx/mcx.h @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on ti/evm/evm.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "HTKW mcx Board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_MCX() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly0*/\ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly1*/\ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \ + /* GPIO_43 LCD buffer enable */ \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \ + /* GPIO_57 TS_PenIRQn */\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \ + /* GPIO_58 ETHERNET RESET */\ + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \ + /* GPIO_61 SD-CARD CD */ \ + MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \ + /* GPIO_62 Nand write protect, keep enabled */ \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ + /* GPIO_65 SD-CARD WP */\ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \ + /* GPIO_131 LCD Enable */ \ + MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \ + /* GPIO_132 USB host Enable */\ + MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \ + /* GPIO_133 HDMI PD */\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \ + /* GPIO_152 USB phy2 reset */\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \ + /* GPIO_153 */\ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \ + /* GPIO_154 USB phy1 reset */\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \ + /* GPIO_155 TS_BUSY */\ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat7 */\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat4 */\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat5 */\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat6 */\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat3 */\ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ + /* HDQ */\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \ + /* SYS_nRESWARM */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\ + /* ETK (ES2 onwards) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_stp */ \ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_clk */\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + +#endif diff --git a/boards.cfg b/boards.cfg index 1f264b1..70809ca 100644 --- a/boards.cfg +++ b/boards.cfg @@ -214,6 +214,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 tricorder arm armv7 tricorder corscience omap3 twister arm armv7 twister technexion omap3 omap4_panda arm armv7 panda ti omap4 diff --git a/include/configs/mcx.h b/include/configs/mcx.h new file mode 100644 index 0000000..0940e86 --- /dev/null +++ b/include/configs/mcx.h @@ -0,0 +1,378 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on omap3_evm_config.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */ + +#define MACH_TYPE_MCX 3656 +#define CONFIG_MACH_TYPE MACH_TYPE_MCX + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +#define CONFIG_OF_LIBFDT +#define CONFIG_FIT + +/* + * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader + * and older u-boot.bin with the new U-Boot SPL. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/* + * DDR related + */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C + +/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "mcx # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/* + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ + 48, 49, 50, 51, 52, 53, 54, 55,\ + 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * ethernet support + * + */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +#endif /* __CONFIG_H */
Hi Stefano,
Cc'd Govindraj.
On 02/05/12 16:57, Stefano Babic wrote:
From: Ilya Yanok yanok@emcraft.com
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Signed-off-by: Ilya Yanok yanok@emcraft.com Signed-off-by: Stefano Babic sbabic@denx.de CC: Tom Rini tom.rini@gmail.com Cc: Detlev Zundel dzu@denx.de
[...]
diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c new file mode 100644 index 0000000..dcc8707 --- /dev/null +++ b/board/htkw/mcx/mcx.c
[...]
+#ifdef CONFIG_USB_EHCI +static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_EHCI_PORT_MODE_PHY,
This looks wrong, as port3 is TLL only, so it cannot have a PHY, or am I missing something?
+};
+int ehci_hcd_init(void) +{
- int ret;
- ret = omap_ehci_hcd_init(&usbhs_bdata);
- if (ret < 0)
return ret;- return 0;
+}
return omap_ehci_hcd_init(&usbhs_bdata); ?
+int ehci_hcd_stop(void) +{
- int ret;
- ret = omap_ehci_hcd_stop();
- return ret;
+}
same here: return omap_ehci_hcd_stop(); ?
[...]
From: Ilya Yanok yanok@emcraft.com
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Signed-off-by: Ilya Yanok yanok@emcraft.com Signed-off-by: Stefano Babic sbabic@denx.de CC: Tom Rini tom.rini@gmail.com Cc: Detlev Zundel dzu@denx.de --- Changes since V7: - do not use temporary variable to return values (Igor Grinberg) - port 2 is TTL, cannot be PHY (Igor Grinberg)
Changes from V6: - rebased on current u-boot-ti - applied and tested on top of EHCI Gavindraj's patches - uses ULPI framework
Changes from V5 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120254
- added comments on CONFIG_SYS_TEXT_BASE and SPL_{MALLOC,BSS}
Changes from V4 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120148
- board_mmc_init return value fixed - machine id added locally - CONFIG_SYS_NAND_U_BOOT_SIZE removed
Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118530
- Comment for misc_init_r function fixed - Added check for gpio_request return value. - Removed #if defined(CONFIG_GENERIC_MMC) around board_mmc_init - CONFIG_USE_IRQ and related stuff removed from config - CONFIG_OMAP3_MICRON_DDR removed - CONFIG_SYS_MAXRAGS changed 32 -> 16 - Incorrect multiline comments (/*--- ones) fixed - CONFIG_SPL_MAX_SIZE rewritten 0xB400 -> (45 << 10) - CONFIG_SPL_NAND_WORKSPACE removed
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/116548
- None
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/115026
- Calls to gpio_set_value after gpio_direction_output removed - Minor style problem (tab instead of space) fixed
SPL series: Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112892
- OMAP EHCI support enabled in config - MMC SPL support enabled in config
"DaVinci EMAC and HTKW mcx support" series: Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112884
- NAND SPL support enabled in config
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112317
- removed dead code from board/htkw/mcx/Makefile as Mike suggested - removed EMAC reset (now done in generic cpu_eth_init()) - removed some unsuned defines from configuration header
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111197
- various style fixes to make checkpatch (almost) happy - FSF address removed from GPL comments - CONFIG_SYS_TEXT_BASE moved to configuration header, config.mk droped - CONFIG_MACH_TYPE is used instead of setting mach type from board code - i2c_init removed from misc_init_r - cpu_eth_init removed (added to generic place by another patch) - CONTROL_PADCONF defines removed - Fixed boolean config options not to have a value - CONFIG_MUSB_* and related defines removed
MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 112 +++++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 378 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 941 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.h
diff --git a/MAINTAINERS b/MAINTAINERS index a8e56bb..7e52f50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -920,6 +920,10 @@ Richard Woodruff r-woodruff2@ti.com
omap2420h4 ARM1136EJS
+Ilya Yanok yanok@emcraft.com + + mcx ARM ARMV7 (AM35x SoC) + Syed Mohammed Khasim sm.khasim@gmail.com Sughosh Ganu urwithsughosh@gmail.com
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile new file mode 100644 index 0000000..4c8db10 --- /dev/null +++ b/board/htkw/mcx/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c new file mode 100644 index 0000000..e593b43 --- /dev/null +++ b/board/htkw/mcx/mcx.c @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on ti/evm/evm.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/omap_gpio.h> +#include "errno.h" +#include <i2c.h> +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/ehci-omap.h> +#endif +#include "mcx.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_USB_EHCI +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, +}; + +int ehci_hcd_init(void) +{ + return omap_ehci_hcd_init(&usbhs_bdata); +} + +int ehci_hcd_stop(void) +{ + return omap_ehci_hcd_stop(); +} +#endif + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +/* + * Routine: misc_init_r + * Description: late init. + */ +int misc_init_r(void) +{ + dieid_num_r(); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_MCX(); +} + +#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0); +} +#endif + +#ifdef CONFIG_USB_EHCI_OMAP +#define USB_HOST_PWR_EN 132 +int board_usb_init(void) +{ + if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) { + puts("Failed to get USB_HOST_PWR_EN pin\n"); + return -ENODEV; + } + gpio_direction_output(USB_HOST_PWR_EN, 1); + + return 0; +} +#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h new file mode 100644 index 0000000..d675a48 --- /dev/null +++ b/board/htkw/mcx/mcx.h @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on ti/evm/evm.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_ + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "HTKW mcx Board", + "NAND", +}; + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_MCX() \ + /* SDRC */\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly0*/\ + MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \ + /*sdrc_strben_dly1*/\ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \ + /* GPIO_43 LCD buffer enable */ \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \ + /* GPIO_57 TS_PenIRQn */\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \ + /* GPIO_58 ETHERNET RESET */\ + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \ + /* GPIO_61 SD-CARD CD */ \ + MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \ + /* GPIO_62 Nand write protect, keep enabled */ \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \ + /* GPIO_65 SD-CARD WP */\ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \ + /* GPIO_131 LCD Enable */ \ + MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \ + /* GPIO_132 USB host Enable */\ + MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \ + /* GPIO_133 HDMI PD */\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \ + /* GPIO_152 USB phy2 reset */\ + MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \ + /* GPIO_153 */\ + MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \ + /* GPIO_154 USB phy1 reset */\ + MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \ + /* GPIO_155 TS_BUSY */\ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat7 */\ + MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat4 */\ + MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat5 */\ + MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat6 */\ + MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \ + /* HSUSB2_dat3 */\ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ + MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ + /* HDQ */\ + MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \ + /* SYS_nRESWARM */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\ + /* ETK (ES2 onwards) */\ + MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_stp */ \ + MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \ + /* hsusb1_clk */\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + +#endif diff --git a/boards.cfg b/boards.cfg index 1f264b1..70809ca 100644 --- a/boards.cfg +++ b/boards.cfg @@ -214,6 +214,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 tricorder arm armv7 tricorder corscience omap3 twister arm armv7 twister technexion omap3 omap4_panda arm armv7 panda ti omap4 diff --git a/include/configs/mcx.h b/include/configs/mcx.h new file mode 100644 index 0000000..0940e86 --- /dev/null +++ b/include/configs/mcx.h @@ -0,0 +1,378 @@ +/* + * Copyright (C) 2011 Ilya Yanok, Emcraft Systems + * + * Based on omap3_evm_config.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */ + +#define MACH_TYPE_MCX 3656 +#define CONFIG_MACH_TYPE MACH_TYPE_MCX + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +#define CONFIG_OF_LIBFDT +#define CONFIG_FIT + +/* + * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader + * and older u-boot.bin with the new U-Boot SPL. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/* + * DDR related + */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C + +/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "mcx # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * AM3517 has 12 GP timers, they can be driven by the system clock + * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). + * This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/* + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ + 48, 49, 50, 51, 52, 53, 54, 55,\ + 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * ethernet support + * + */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +#endif /* __CONFIG_H */
On 02/08/12 11:30, Stefano Babic wrote:
From: Ilya Yanok yanok@emcraft.com
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Signed-off-by: Ilya Yanok yanok@emcraft.com Signed-off-by: Stefano Babic sbabic@denx.de CC: Tom Rini tom.rini@gmail.com Cc: Detlev Zundel dzu@denx.de
Acked-by: Igor Grinberg grinberg@compulab.co.il
Changes since V7:
- do not use temporary variable to return values (Igor Grinberg)
- port 2 is TTL, cannot be PHY (Igor Grinberg)
Changes from V6:
- rebased on current u-boot-ti
- applied and tested on top of EHCI Gavindraj's patches
- uses ULPI framework
Changes from V5 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120254
- added comments on CONFIG_SYS_TEXT_BASE and SPL_{MALLOC,BSS}
Changes from V4 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/120148
- board_mmc_init return value fixed
- machine id added locally
- CONFIG_SYS_NAND_U_BOOT_SIZE removed
Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/118530
- Comment for misc_init_r function fixed
- Added check for gpio_request return value.
- Removed #if defined(CONFIG_GENERIC_MMC) around board_mmc_init
- CONFIG_USE_IRQ and related stuff removed from config
- CONFIG_OMAP3_MICRON_DDR removed
- CONFIG_SYS_MAXRAGS changed 32 -> 16
- Incorrect multiline comments (/*--- ones) fixed
- CONFIG_SPL_MAX_SIZE rewritten 0xB400 -> (45 << 10)
- CONFIG_SPL_NAND_WORKSPACE removed
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/116548
- None
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/115026
- Calls to gpio_set_value after gpio_direction_output removed
- Minor style problem (tab instead of space) fixed
SPL series: Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112892
- OMAP EHCI support enabled in config
- MMC SPL support enabled in config
"DaVinci EMAC and HTKW mcx support" series: Changes from V3 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112884
- NAND SPL support enabled in config
Changes from V2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112317
- removed dead code from board/htkw/mcx/Makefile as Mike suggested
- removed EMAC reset (now done in generic cpu_eth_init())
- removed some unsuned defines from configuration header
Changes from V1 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/111197
- various style fixes to make checkpatch (almost) happy
- FSF address removed from GPL comments
- CONFIG_SYS_TEXT_BASE moved to configuration header, config.mk droped
- CONFIG_MACH_TYPE is used instead of setting mach type from board code
- i2c_init removed from misc_init_r
- cpu_eth_init removed (added to generic place by another patch)
- CONTROL_PADCONF defines removed
- Fixed boolean config options not to have a value
- CONFIG_MUSB_* and related defines removed
MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 112 +++++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 378 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 941 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.h
diff --git a/MAINTAINERS b/MAINTAINERS index a8e56bb..7e52f50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -920,6 +920,10 @@ Richard Woodruff r-woodruff2@ti.com
omap2420h4 ARM1136EJS
+Ilya Yanok yanok@emcraft.com
- mcx ARM ARMV7 (AM35x SoC)
Syed Mohammed Khasim sm.khasim@gmail.com Sughosh Ganu urwithsughosh@gmail.com
diff --git a/board/htkw/mcx/Makefile b/board/htkw/mcx/Makefile new file mode 100644 index 0000000..4c8db10 --- /dev/null +++ b/board/htkw/mcx/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +#
+include $(TOPDIR)/config.mk
+LIB = $(obj)lib$(BOARD).o
+COBJS := $(BOARD).o
+SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS))
+$(LIB): $(obj).depend $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
+#########################################################################
+# defines $(obj).depend target +include $(SRCTREE)/rules.mk
+sinclude $(obj).depend diff --git a/board/htkw/mcx/mcx.c b/board/htkw/mcx/mcx.c new file mode 100644 index 0000000..e593b43 --- /dev/null +++ b/board/htkw/mcx/mcx.c @@ -0,0 +1,112 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on ti/evm/evm.c
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/omap_gpio.h> +#include "errno.h" +#include <i2c.h> +#ifdef CONFIG_USB_EHCI +#include <usb.h> +#include <asm/ehci-omap.h> +#endif +#include "mcx.h"
+DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_USB_EHCI +static struct omap_usbhs_board_data usbhs_bdata = {
- .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
- .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+int ehci_hcd_init(void) +{
- return omap_ehci_hcd_init(&usbhs_bdata);
+}
+int ehci_hcd_stop(void) +{
- return omap_ehci_hcd_stop();
+} +#endif
+/*
- Routine: board_init
- Description: Early hardware init.
- */
+int board_init(void) +{
- gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
- return 0;
+}
+/*
- Routine: misc_init_r
- Description: late init.
- */
+int misc_init_r(void) +{
- dieid_num_r();
- return 0;
+}
+/*
- Routine: set_muxconf_regs
- Description: Setting up the configuration Mux registers specific to the
hardware. Many pins need to be moved from protect to primary
mode.- */
+void set_muxconf_regs(void) +{
- MUX_MCX();
+}
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) +int board_mmc_init(bd_t *bis) +{
- return omap_mmc_init(0);
+} +#endif
+#ifdef CONFIG_USB_EHCI_OMAP +#define USB_HOST_PWR_EN 132 +int board_usb_init(void) +{
- if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) {
puts("Failed to get USB_HOST_PWR_EN pin\n");return -ENODEV;- }
- gpio_direction_output(USB_HOST_PWR_EN, 1);
- return 0;
+} +#endif diff --git a/board/htkw/mcx/mcx.h b/board/htkw/mcx/mcx.h new file mode 100644 index 0000000..d675a48 --- /dev/null +++ b/board/htkw/mcx/mcx.h @@ -0,0 +1,408 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on ti/evm/evm.h
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_
+const omap3_sysinfo sysinfo = {
- DDR_DISCRETE,
- "HTKW mcx Board",
- "NAND",
+};
+/*
- IEN - Input Enable
- IDIS - Input Disable
- PTD - Pull type Down
- PTU - Pull type Up
- DIS - Pull type selection is inactive
- EN - Pull type selection is active
- M0 - Mode 0
- The commented string gives the final mux configuration for that pin
- */
+#define MUX_MCX() \
- /* SDRC */\
- MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(SDRC_CKE0), (M0)) \
- MUX_VAL(CP(SDRC_CKE1), (M0)) \
- MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly0*/\- MUX_VAL(CP(STRBEN_DLY1), (IEN | PTD | EN | M0)) \
/*sdrc_strben_dly1*/\- /* GPMC */\
- MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_A10), (IDIS | PTU | DIS | M4)) \
/* GPIO_43 LCD buffer enable */ \- MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) \
/* GPIO_57 TS_PenIRQn */\- MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) \
/* GPIO_58 ETHERNET RESET */\- MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | DIS | M4)) \
/* GPIO_61 SD-CARD CD */ \- MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | EN | M4)) \
/* GPIO_62 Nand write protect, keep enabled */ \- MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
/* GPIO_65 SD-CARD WP */\- /* DSS */\
- MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\
- MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
- /* CAMERA */\
- MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) \
- /* MMC */\
- MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
- \
- MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(MMC2_CMD), (IDIS | PTD | DIS | M4)) \
/* GPIO_131 LCD Enable */ \- MUX_VAL(CP(MMC2_DAT0), (IDIS | PTD | DIS | M4)) \
/* GPIO_132 USB host Enable */\- MUX_VAL(CP(MMC2_DAT1), (IDIS | PTD | DIS | M4)) \
/* GPIO_133 HDMI PD */\- MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4))\
- /* McBSP */\
- MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\
- MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\
- \
- MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\
- \
- MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) \
/* GPIO_152 USB phy2 reset */\- MUX_VAL(CP(MCBSP4_DR), (IEN | PTU | EN | M4)) \
/* GPIO_153 */\- MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) \
/* GPIO_154 USB phy1 reset */\- MUX_VAL(CP(MCBSP4_FSX), (IEN | PTU | EN | M4)) \
/* GPIO_155 TS_BUSY */\- /* UART */\
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
- \
- MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \
- MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
- /* I2C */\
- MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
- /* McSPI */\
- MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat7 */\- MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat4 */\- MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat5 */\- MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat6 */\- MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) \
/* HSUSB2_dat3 */\- /* CCDC */\
- MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | EN | M4)) \
- /* RMII */\
- MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
- MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
- MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
- MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
- MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
- MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
- /* HECC */\
- MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(HECC1_RXD), (IEN | PTD | EN | M4)) \
- /* HSUSB */\
- MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
- MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
- /* HDQ */\
- MUX_VAL(CP(HDQ_SIO), (IEN | PTD | EN | M4)) \
- /* Control and debug */\
- MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \
- MUX_VAL(CP(SYS_NRESWARM), (IEN | PTU | DIS | M4)) \
/* SYS_nRESWARM */\- MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \
- \
- MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\
- MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4))\
- /* JTAG */\
- MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \
- MUX_VAL(CP(JTAG_EMU1), (IEN | PTU | EN | M4))\
- /* ETK (ES2 onwards) */\
- MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_stp */ \- MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)) \
/* hsusb1_clk */\- MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \
- MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \
- MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M4)) \
- /* Die to Die */\
- MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \
- MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \
- MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \
- MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \
+#endif diff --git a/boards.cfg b/boards.cfg index 1f264b1..70809ca 100644 --- a/boards.cfg +++ b/boards.cfg @@ -214,6 +214,7 @@ omap3_evm_quick_mmc arm armv7 evm ti omap3_evm_quick_nand arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 tricorder arm armv7 tricorder corscience omap3 twister arm armv7 twister technexion omap3 omap4_panda arm armv7 panda ti omap4 diff --git a/include/configs/mcx.h b/include/configs/mcx.h new file mode 100644 index 0000000..0940e86 --- /dev/null +++ b/include/configs/mcx.h @@ -0,0 +1,378 @@ +/*
- Copyright (C) 2011 Ilya Yanok, Emcraft Systems
- Based on omap3_evm_config.h
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc.
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+/*
- High Level Configuration Options
- */
+#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */
+#define MACH_TYPE_MCX 3656 +#define CONFIG_MACH_TYPE MACH_TYPE_MCX
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
+#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h>
+#define CONFIG_OF_LIBFDT +#define CONFIG_FIT
+/*
- Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
- and older u-boot.bin with the new U-Boot SPL.
- */
+#define CONFIG_SYS_TEXT_BASE 0x80008000
+/*
- Display CPU and Board information
- */
+#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO
+/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1)
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG
+/*
- Size of malloc() pool
- */
+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/*
- DDR related
- */
+#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
+/*
- Hardware drivers
- */
+/*
- NS16550 Configuration
- */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+/*
- select serial console configuration
- */
+#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */
+/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}+#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION
+/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+/* commands to include */ +#include <config_cmd_default.h>
+#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
+#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C
+/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/*
- Board NAND Info.
- */
+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
/* to access nand */+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access *//* nand at CS0 */+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
/* NAND devices */+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
+#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
+/* Environment information */ +#define CONFIG_BOOTDELAY 10
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x82000000\0" \
- "console=ttyO2,115200n8\0" \
- "mmcargs=setenv bootargs console=${console} " \
"root=/dev/mmcblk0p2 rw " \"rootfstype=ext3 rootwait\0" \- "nandargs=setenv bootargs console=${console} " \
"root=/dev/mtdblock4 rw " \"rootfstype=jffs2\0" \- "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \- "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
- "mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \"bootm ${loadaddr}\0" \- "nandboot=echo Booting from nand ...; " \
"run nandargs; " \"nand read ${loadaddr} 280000 400000; " \"bootm ${loadaddr}\0" \+#define CONFIG_BOOTCOMMAND \
- "if mmc init; then " \
"if run loadbootscript; then " \"run bootscript; " \"else " \"if run loaduimage; then " \"run mmcboot; " \"else run nandboot; " \"fi; " \"fi; " \- "else run nandboot; fi"
+#define CONFIG_AUTO_COMPLETE +/*
- Miscellaneous configurable options
- */
+#define V_PROMPT "mcx # "
+#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_MAXARGS 16 /* max number of command */
/* args */+/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
0x01F00000) /* 31MB */+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
/* address */+/*
- AM3517 has 12 GP timers, they can be driven by the system clock
- (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
- This rate is divided by a local divisor.
- */
+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000
+/*
- Stack sizes
- The stack sizes are set up in start.S using the settings below
- */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+/*
- Physical Memory Map
- */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+/*
- FLASH and environment organization
- */
+/* **** PISMO SUPPORT *** */
+/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M
+#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
+/*
- CFI FLASH driver setup
- */
+/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
+/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)+#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \GENERATED_GBL_DATA_SIZE)+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE (45 << 10) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
48, 49, 50, 51, 52, 53, 54, 55,\56, 57, 58, 59, 60, 61, 62, 63}+#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3
+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
CONFIG_SYS_NAND_ECCSIZE)+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
CONFIG_SYS_NAND_ECCSTEPS)+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/*
- ethernet support
- */
+#if defined(CONFIG_CMD_NET) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif
+#endif /* __CONFIG_H */
participants (7)
-
Anatolij Gustschin -
Govindraj -
Igor Grinberg -
Ilya Yanok -
Remy Bohmer -
Stefano Babic -
Tom Rini